Changeset 13013 in vbox for trunk/src/VBox/VMM/VMMAll

Timestamp:

Oct 6, 2008 2:48:49 PM (16 years ago)

Author:

vboxsync

Message:

infrastructure work for X2APIC support

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• EMAll.cpp (modified) (3 diffs)
• PDMAll.cpp (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/EMAll.cpp

@@ -34 +34 @@
 #include "EMInternal.h"
 #include <VBox/vm.h>
+#include <VBox/vmm.h>
 #include <VBox/hwaccm.h>
 #include <VBox/tm.h>
@@ -2576 +2577 @@
 #endif
     default:
-        /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
-        val = 0;
-        break;
+        /* In X2APIC specification this range is reserved for APIC control. */ 
+        if ((pRegFrame->ecx >= MSR_IA32_APIC_START) && (pRegFrame->ecx < MSR_IA32_APIC_END))
+        {
+            rc = PDMApicRDMSR(pVM, VMMGetCpuId(pVM), pRegFrame->ecx, &val);
+        } 
+        else 
+        {
+            /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
+            val = 0;
+            break;
+        }
     }
     Log(("EMInterpretRdmsr %s (%x) -> val=%VX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
-    pRegFrame->eax = (uint32_t) val;
-    pRegFrame->edx = (uint32_t) (val >> 32ULL);
-    return VINF_SUCCESS;
+    if (rc == VINF_SUCCESS) 
+    {
+        pRegFrame->eax = (uint32_t) val;
+        pRegFrame->edx = (uint32_t) (val >> 32ULL);
+    }
+    return rc;
 }
 
@@ -2714 +2726 @@
 
     default:
+        /* In X2APIC specification this range is reserved for APIC control. */ 
+        if ((pRegFrame->ecx >=  MSR_IA32_APIC_START) && (pRegFrame->ecx <  MSR_IA32_APIC_END))
+        {
+            return PDMApicWRMSR(pVM, VMMGetCpuId(pVM), pRegFrame->ecx, val);
+        }
         /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
         break;

trunk/src/VBox/VMM/VMMAll/PDMAll.cpp

@@ -253 +253 @@
 }
 
+/**
+ * WRMSR in APIC range.
+ *
+ * @returns VBox status code.
+ * @param   pVM             VM handle.
+ * @param   iCpu            Target CPU.
+ * @param   u32Reg          MSR to write.
+ * @param   u64Value        Value to write.
+ */
+VMMDECL(int) PDMApicWRMSR(PVM pVM, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value)
+{
+    if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
+    {
+        Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnWRMSR));
+        pdmLock(pVM);
+        pVM->pdm.s.Apic.CTX_SUFF(pfnWRMSR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), iCpu, u32Reg, u64Value);
+        pdmUnlock(pVM);
+        return VINF_SUCCESS;
+    }
+    return VERR_PDM_NO_APIC_INSTANCE;
+}
+
+/**
+ * RDMSR in APIC range.
+ *
+ * @returns VBox status code.
+ * @param   pVM             VM handle.
+ * @param   iCpu            Target CPU.
+ * @param   u32Reg          MSR to read.
+ * @param   pu64Value       Value read.
+ */
+VMMDECL(int) PDMApicRDMSR(PVM pVM, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value)
+{
+    if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
+    {
+        Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnRDMSR));
+        pdmLock(pVM);
+        pVM->pdm.s.Apic.CTX_SUFF(pfnRDMSR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), iCpu, u32Reg, pu64Value);
+        pdmUnlock(pVM);
+        return VINF_SUCCESS;
+    }
+    return VERR_PDM_NO_APIC_INSTANCE;
+}
+
 
 /**