Changeset 13037 in vbox

Timestamp:

Oct 7, 2008 11:10:32 AM (16 years ago)

Author:

vboxsync

Message:

EPT updates

Location:

trunk/src/VBox/VMM/VMMR0

Files:

• HWVMXR0.cpp (modified) (3 diffs)
• PGMR0.cpp (modified) (3 diffs)

trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

@@ -1007 +1007 @@
         /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
         val |= X86_CR0_PE | X86_CR0_PG;
-        if (!pVM->hwaccm.s.fNestedPaging)
+        if (pVM->hwaccm.s.fNestedPaging)
+        {
+            if (!(pCtx->cr0 & X86_CR0_PG))
+            {
+                /* Reenable cr3 read/write monitoring as our identity mapped page table is active. */
+                pVM->hwaccm.s.vmx.proc_ctls |=   VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT 
+                                               | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
+            }
+            else
+            {
+                /* Disable cr3 read/write monitoring as we don't need it for EPT. */
+                pVM->hwaccm.s.vmx.proc_ctls &=  ~(  VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT 
+                                                  | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
+            }
+            rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
+            AssertRC(rc);
+        }
+        else
         {
             /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
@@ -2353 +2370 @@
                 break;
             case 3:
-                Assert(!pVM->hwaccm.s.fNestedPaging);
+                Assert(!pVM->hwaccm.s.fNestedPaging || !(pCtx->cr0 & X86_CR0_PG));
                 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
                 break;
@@ -2381 +2398 @@
             STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
 
-            Assert(!pVM->hwaccm.s.fNestedPaging || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
+            Assert(!pVM->hwaccm.s.fNestedPaging || !(pCtx->cr0 & X86_CR0_PG) || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
 
             /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */

trunk/src/VBox/VMM/VMMR0/PGMR0.cpp

@@ -44 +44 @@
 #undef PGM_BTH_NAME
 
+#define PGM_BTH_NAME(name)          PGM_BTH_NAME_EPT_PROT(name)
+#include "PGMR0Bth.h"
+#undef PGM_BTH_NAME
+
 __END_DECLS
 
@@ -82 +86 @@
     STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = NULL; } );
 
-    /* AMD uses the host's paging mode; Intel's version is on the todo list */
-    AssertMsg(enmShwPagingMode == PGMMODE_32_BIT || enmShwPagingMode == PGMMODE_PAE || enmShwPagingMode == PGMMODE_PAE_NX || enmShwPagingMode == PGMMODE_AMD64 || enmShwPagingMode == PGMMODE_AMD64_NX, ("enmShwPagingMode=%d\n", enmShwPagingMode));
+    /* AMD uses the host's paging mode; Intel has a single mode (EPT). */
+    AssertMsg(enmShwPagingMode == PGMMODE_32_BIT || enmShwPagingMode == PGMMODE_PAE || enmShwPagingMode == PGMMODE_PAE_NX || enmShwPagingMode == PGMMODE_AMD64 || enmShwPagingMode == PGMMODE_AMD64_NX || enmShwPagingMode == PGMMODE_EPT, ("enmShwPagingMode=%d\n", enmShwPagingMode));
 
 #ifdef VBOX_WITH_STATISTICS
@@ -144 +148 @@
         rc = PGM_BTH_NAME_AMD64_PROT(Trap0eHandler)(pVM, uErr, pRegFrame, pvFault);
         break;
+    case PGMMODE_EPT:
+        rc = PGM_BTH_NAME_EPT_PROT(Trap0eHandler)(pVM, uErr, pRegFrame, pvFault);
+        break;
     default:
         AssertFailed();