VirtualBox

Changeset 13074 in vbox


Ignore:
Timestamp:
Oct 8, 2008 12:16:57 PM (16 years ago)
Author:
vboxsync
Message:
  • remaining bits of x2APIC, some SMP refinements in LAPIC
Location:
trunk
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/pdmdev.h

    r13020 r13074  
    996996     * @returns VBox status code.
    997997     * @param   pDevIns         Device instance of the APIC.
    998      * @param   iCpu            Target CPU.
     998     * @param   idCpu           Target CPU.
    999999     * @param   u32Reg          MSR to write.
    10001000     * @param   u64Value        Value to write.
    10011001     */
    1002     DECLR3CALLBACKMEMBER(uint32_t, pfnWriteMSRR3, (PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value));
     1002    DECLR3CALLBACKMEMBER(uint32_t, pfnWriteMSRR3, (PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value));
    10031003
    10041004    /**
    … …  
    10071007     * @returns VBox status code.
    10081008     * @param   pDevIns         Device instance of the APIC.
    1009      * @param   iCpu            Target CPU.
     1009     * @param   idCpu           Target CPU.
    10101010     * @param   u32Reg          MSR to read.
    10111011     * @param   pu64Value       Value read.
    10121012     */
    1013     DECLR3CALLBACKMEMBER(uint32_t, pfnReadMSRR3, (PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value));
     1013    DECLR3CALLBACKMEMBER(uint32_t, pfnReadMSRR3, (PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value));
    10141014
    10151015    /**

  • trunk/src/VBox/Devices/PC/DevAPIC.cpp

    r13020 r13074  
    4444#define MSR_IA32_APICBASE_BSP           (1<<8)
    4545#define MSR_IA32_APICBASE_ENABLE        (1<<11)
     46#ifdef VBOX
     47#define MSR_IA32_APICBASE_X2ENABLE      (1<<10)
     48#endif
    4649#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
    4750
    … …  
    180183#ifdef VBOX
    181184#define APIC_MAX_PATCH_ATTEMPTS         100
     185
     186typedef uint32_t PhysApicId;
     187typedef uint32_t LogApicId;
    182188#endif
    183189
    … …  
    187193#endif /* !VBOX */
    188194    uint32_t apicbase;
     195#ifdef VBOX
     196    /* Task priority register (interrupt level) */
     197    uint32_t   tpr;
     198    /* Logical APIC id */
     199    LogApicId  id;
     200    /* Physical APIC id */
     201    PhysApicId phys_id;
     202    /** @todo: is it logical or physical? Not really used anyway now. */
     203    PhysApicId arb_id;
     204#else
     205    uint8_t tpr;
    189206    uint8_t id;
    190207    uint8_t arb_id;
    191 #ifdef VBOX
    192     uint32_t tpr;
    193 #else
    194     uint8_t tpr;
    195208#endif
    196209    uint32_t spurious_vec;
    … …  
    203216    uint32_t esr; /* error register */
    204217    uint32_t icr[2];
    205 
    206218    uint32_t divide_conf;
    207219    int count_shift;
    … …  
    289301    RTRCPTR         pLapicsRC;
    290302
    291     /** Alignment */
    292     uint32_t Alignment0;
     303    /** APIC specification version in this virtual hardware configuration. */
     304    PDMAPICVERSION  enmVersion;
    293305
    294306    /** Number of attempts made to optimize TPR accesses. */
    … …  
    307319} APICDeviceInfo;
    308320
     321static void apic_eoi(APICDeviceInfo *dev, APICState* s);
     322static void apic_deliver(APICDeviceInfo* dev, APICState *s,
     323                         uint8_t dest, uint8_t dest_mode,
     324                         uint8_t delivery_mode, uint8_t vector_num,
     325                         uint8_t polarity, uint8_t trigger_mode);
     326static void apic_timer_update(APICDeviceInfo* dev, APICState *s,
     327                              int64_t current_time);
     328static int apic_get_arb_pri(APICState *s);
     329static int apic_get_ppr(APICState *s);
     330static uint32_t apic_get_current_count(APICDeviceInfo* dev, APICState *s);
     331
     332
    309333DECLINLINE(APICState*) getLapicById(APICDeviceInfo* dev, VMCPUID id)
    310334{
    … …  
    322346DECLINLINE(VMCPUID) getCpuFromLapic(APICDeviceInfo* dev, APICState *s)
    323347{
    324     /* for now we assume LAPIC id == CPU id */
    325     return VMCPUID(s->id);
     348    /* for now we assume LAPIC physical id == CPU id */
     349    return VMCPUID(s->phys_id);
    326350}
    327351
    … …  
    338362}
    339363
     364DECLINLINE(uint32_t) getApicEnableBits(APICDeviceInfo* dev)
     365{
     366    switch (dev->enmVersion)
     367    {
     368        case PDMAPICVERSION_NONE:
     369            return 0;
     370        case PDMAPICVERSION_APIC:
     371            return MSR_IA32_APICBASE_ENABLE;
     372        case PDMAPICVERSION_X2APIC:
     373            return MSR_IA32_APICBASE_ENABLE | MSR_IA32_APICBASE_X2ENABLE ;
     374        default:
     375            AssertMsgFailed(("Unsuported APIC version %d\n", dev->enmVersion));
     376            return 0;
     377    }
     378}
     379
     380DECLINLINE(PDMAPICVERSION) getApicMode(APICState *apic)
     381{
     382    switch (((apic->apicbase) >> 10) & 0x3)
     383    {
     384        case 0:
     385            return PDMAPICVERSION_NONE;
     386        case 1:
     387        default:
     388            /* Invalid */
     389            return PDMAPICVERSION_NONE;
     390        case 2:
     391            return PDMAPICVERSION_APIC;
     392        case 3:
     393            return PDMAPICVERSION_X2APIC;
     394    }
     395}
    340396
    341397#endif /* VBOX */
    … …  
    399455            if (d >= 0)
    400456            {
    401                 APICState* apic = LAPIC_BASE(dev) + d;
     457                APICState* apic = getLapicById(dev, d);
    402458                apic_set_irq(dev, apic, vector_num, trigger_mode);
    403459            }
    … …  
    480536    /* APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR); */
    481537    /** @todo If this change is valid immediately, then we should change the MMIO registration! */
    482     s->apicbase = (val & 0xfffff000) |
    483         (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
    484     /* if disabled, cannot be enabled again (until reset) */
    485     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
    486         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
    487         s->spurious_vec &= ~APIC_SV_ENABLE;
    488 
    489         /* Clear any pending APIC interrupt action flag. */
    490         cpuClearInterrupt(dev, s);
    491         dev->CTX_SUFF(pApicHlp)->pfnChangeFeature(pDevIns, PDMAPICVERSION_NONE);
     538    /* We cannot change if this CPU is BSP or not by writing to MSR - it's hardwired */
     539    PDMAPICVERSION oldMode = getApicMode(s);
     540    s->apicbase =
     541            (val & 0xfffff000) | /* base */
     542            (val & getApicEnableBits(dev)) | /* mode */
     543            (s->apicbase & MSR_IA32_APICBASE_BSP) /* keep BSP bit */;
     544    PDMAPICVERSION newMode = getApicMode(s);
     545   
     546    if (oldMode != newMode)
     547    {
     548        switch (newMode)
     549        {
     550            case PDMAPICVERSION_NONE:
     551            {
     552                s->spurious_vec &= ~APIC_SV_ENABLE;
     553                /* Clear any pending APIC interrupt action flag. */
     554                cpuClearInterrupt(dev, s);
     555                /** @todo: why do we do that? */
     556                dev->CTX_SUFF(pApicHlp)->pfnChangeFeature(pDevIns, PDMAPICVERSION_NONE);
     557                break;
     558            }
     559            case PDMAPICVERSION_APIC:
     560                /** @todo: map MMIO ranges, if needed */
     561                break;
     562            case PDMAPICVERSION_X2APIC:
     563                /** @todo: unmap MMIO ranges of this APIC, according to the spec */
     564                break;
     565            default:
     566                break;
     567        }
    492568    }
    493569    /* APIC_UNLOCK(dev); */
    … …  
    581657}
    582658
    583 PDMBOTHCBDECL(uint32_t) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value)
     659PDMBOTHCBDECL(uint32_t) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value)
    584660{
    585661    APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
    586     u32Reg -= MSR_IA32_APIC_START;
    587     LogRel(("nike: WRMSR on %d: to %x written %llx\n", iCpu, u32Reg, u64Value));
    588     return 0;
    589 }
    590 PDMBOTHCBDECL(uint32_t) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value)
     662   
     663    if (dev->enmVersion < PDMAPICVERSION_X2APIC)
     664        return VERR_EM_INTERPRETER;
     665
     666    uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
     667    //LogRel(("nike: WRMSR on %d: to %x written %llx\n", idCpu, index, u64Value));
     668
     669    APICState* apic = getLapicById(dev, idCpu);
     670
     671    switch (index)
     672    {
     673        case 0x02:
     674            apic->id = (u64Value >> 24);
     675            break;
     676        case 0x03:
     677            break;
     678        case 0x08:
     679            apic_update_tpr(dev, apic, u64Value);
     680            break;
     681        case 0x09: case 0x0a:
     682            Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
     683            break;
     684        case 0x0b: /* EOI */
     685            apic_eoi(dev, apic);
     686            break;
     687        case 0x0d:
     688            apic->log_dest = u64Value >> 24;
     689            break;
     690        case 0x0e:
     691            apic->dest_mode = u64Value >> 28;
     692            break;
     693        case 0x0f:
     694            apic->spurious_vec = u64Value & 0x1ff;
     695            apic_update_irq(dev, apic);
     696            break;
     697        case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
     698        case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
     699        case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
     700        case 0x28:
     701            Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
     702            break;
     703
     704        case 0x30:
     705            /* Here one of the differences with regular APIC: ICR is single 64-bit register */
     706            apic->icr[0] = (uint32_t)u64Value;
     707            apic->icr[1] = (uint32_t)(u64Value >> 32);
     708            apic_deliver(dev, apic, (apic->icr[1] >> 24) & 0xff, (apic->icr[0] >> 11) & 1,
     709                         (apic->icr[0] >>  8) & 7, (apic->icr[0] & 0xff),
     710                         (apic->icr[0] >> 14) & 1, (apic->icr[0] >> 15) & 1);
     711            break;
     712        case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
     713        {
     714            int n = index - 0x32;
     715            apic->lvt[n] = u64Value;
     716            if (n == APIC_LVT_TIMER)
     717                apic_timer_update(dev, apic, TMTimerGet(apic->CTX_SUFF(pTimer)));
     718        }
     719        break;
     720        case 0x38:
     721            apic->initial_count = u64Value;
     722            apic->initial_count_load_time = TMTimerGet(apic->CTX_SUFF(pTimer));
     723            apic_timer_update(dev, apic, apic->initial_count_load_time);
     724            break;
     725        case 0x39:
     726            Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
     727            break;
     728        case 0x3e:
     729        {
     730            int v;
     731            apic->divide_conf = u64Value & 0xb;
     732            v = (apic->divide_conf & 3) | ((apic->divide_conf >> 1) & 4);
     733            apic->count_shift = (v + 1) & 7;
     734            break;
     735        }
     736        case 0x3f:
     737        {
     738            /* Self IPI, see x2APIC book 2.4.5 */
     739            int vector = u64Value & 0xff;
     740            apic_bus_deliver(dev,
     741                             1 << getLapicById(dev, idCpu)->id /* Self */,
     742                             0 /* Delivery mode - fixed */,
     743                             vector,
     744                             0 /* Polarity - conform to the bus */,
     745                             0 /* Trigger mode - edge */);
     746            break;
     747        }
     748        default:
     749            AssertMsgFailed(("apicWriteMSR: unknown index %x\n", index));
     750            apic->esr |= ESR_ILLEGAL_ADDRESS;
     751            break;
     752    }
     753
     754    return VINF_SUCCESS;
     755}
     756PDMBOTHCBDECL(uint32_t) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value)
    591757{
    592758    APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
    593     u32Reg -= MSR_IA32_APIC_START;
    594     LogRel(("nike: RDMSR on %d: read from %x\n", iCpu, u32Reg));
    595     *pu64Value = 0;
    596     return 0;
     759
     760    if (dev->enmVersion < PDMAPICVERSION_X2APIC)
     761        return VERR_EM_INTERPRETER;
     762
     763    uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
     764    //LogRel(("nike: RDMSR on %d: read from %x\n", idCpu, index));
     765    APICState* apic = getLapicById(dev, idCpu);
     766    uint64_t val;
     767
     768    switch (index)
     769    {
     770        case 0x02: /* id */
     771            val = apic->id << 24;
     772            break;
     773        case 0x03: /* version */
     774            val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
     775            break;
     776        case 0x08:
     777            val = apic->tpr;
     778            break;
     779        case 0x09:
     780            val = apic_get_arb_pri(apic);
     781            break;
     782        case 0x0a:
     783            /* ppr */
     784            val = apic_get_ppr(apic);
     785            break;
     786        case 0x0b:
     787            val = 0;
     788            break;
     789        case 0x0d:
     790            val = apic->log_dest << 24;
     791            break;
     792        case 0x0e:
     793            /* Bottom 28 bits are always 1 */
     794            val = (apic->dest_mode << 28) | 0xfffffff;
     795            break;
     796        case 0x0f:
     797            val = apic->spurious_vec;
     798        break;
     799        case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
     800            val = apic->isr[index & 7];
     801            break;
     802        case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
     803            val = apic->tmr[index & 7];
     804            break;
     805        case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
     806            val = apic->irr[index & 7];
     807            break;
     808        case 0x28:
     809            val = apic->esr;
     810            break;
     811        case 0x30:
     812            /* Here one of the differences with regular APIC: ICR is single 64-bit register */
     813            val = ((uint64_t)apic->icr[0x31] << 32) | apic->icr[0x30];
     814            break;
     815        case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
     816            val = apic->lvt[index - 0x32];
     817            break;
     818        case 0x38:
     819            val = apic->initial_count;
     820            break;
     821        case 0x39:
     822            val = apic_get_current_count(dev, apic);
     823            break;
     824        case 0x3e:
     825            val = apic->divide_conf;
     826            break;
     827        case 0x3f:
     828            /* Self IPI register is write only */
     829            Log(("apicReadMSR: read from write-only register %d ignored\n", index));
     830            break;
     831        default:
     832            AssertMsgFailed(("apicReadMSR: unknown index %x\n", index));
     833            apic->esr |= ESR_ILLEGAL_ADDRESS;
     834            val = 0;
     835            break;
     836    }
     837    *pu64Value = val;
     838    return VINF_SUCCESS;
    597839}
    598840
    … …  
    13051547
    13061548    qemu_put_be32s(f, &s->apicbase);
     1549#ifdef VBOX
     1550    qemu_put_be32s(f, &s->id);
     1551    qemu_put_be32s(f, &s->phys_id);
     1552    qemu_put_be32s(f, &s->arb_id);
     1553    qemu_put_be32s(f, &s->tpr);
     1554#else
    13071555    qemu_put_8s(f, &s->id);
    13081556    qemu_put_8s(f, &s->arb_id);
    1309 #ifdef VBOX
    1310     qemu_put_be32s(f, &s->tpr);
    1311 #else
    13121557    qemu_put_8s(f, &s->tpr);
    13131558#endif
    … …  
    13421587    int i;
    13431588
    1344     if (version_id != 1)
     1589    if (version_id != 2)
    13451590        return -EINVAL;
    13461591
    13471592    /* XXX: what if the base changes? (registered memory regions) */
    13481593    qemu_get_be32s(f, &s->apicbase);
     1594#ifdef VBOX
     1595    qemu_get_be32s(f, &s->id);
     1596    qemu_get_be32s(f, &s->phys_id);
     1597    qemu_get_be32s(f, &s->arb_id);
     1598    qemu_get_be32s(f, &s->tpr);
     1599#else
    13491600    qemu_get_8s(f, &s->id);
    13501601    qemu_get_8s(f, &s->arb_id);
    1351 #ifdef VBOX
    1352     qemu_get_be32s(f, &s->tpr);
    1353 #else
    13541602    qemu_get_8s(f, &s->tpr);
    13551603#endif
    … …  
    18552103    s->arb_id = 0;
    18562104    /* Reset should re-enable the APIC. */
    1857     s->apicbase = 0xfee00000 | MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE;
    1858     dev->pApicHlpR3->pfnChangeFeature(dev->pDevInsR3, PDMAPICVERSION_APIC);
     2105    s->apicbase = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
     2106    if (s->phys_id == 0)
     2107        s->apicbase |= MSR_IA32_APICBASE_BSP;
     2108    dev->pApicHlpR3->pfnChangeFeature(dev->pDevInsR3, dev->enmVersion);
    18592109    /* Clear any pending APIC interrupt action flag. */
    18602110    cpuClearInterrupt(dev, s);
    … …  
    18822132    int i;
    18832133    memset(apic, 0, sizeof(*apic));
    1884     apic->apicbase  = UINT32_C(0xfee00000) | MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE;
     2134    apic->apicbase = UINT32_C(0xfee00000) | MSR_IA32_APICBASE_ENABLE;
     2135    /* Mark first CPU as BSP */
     2136    if (id == 0)
     2137        apic->apicbase |= MSR_IA32_APICBASE_BSP;
    18852138    for (i = 0; i < APIC_LVT_NB; i++)
    18862139        apic->lvt[i] = 1 << 16; /* mask LVT */
    18872140    apic->spurious_vec = 0xff;
    1888     apic->id = id;
     2141    apic->phys_id = apic->id = id;
    18892142}
    18902143
    … …  
    19442197     * Init the data.
    19452198     */
    1946     pThis->pDevInsR3 = pDevIns;
    1947     pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
    1948     pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
    1949     pThis->cCpus     = cCpus;
     2199    pThis->pDevInsR3  = pDevIns;
     2200    pThis->pDevInsR0  = PDMDEVINS_2_R0PTR(pDevIns);
     2201    pThis->pDevInsRC  = PDMDEVINS_2_RCPTR(pDevIns);
     2202    pThis->cCpus      = cCpus;
     2203    /* Use PDMAPICVERSION_X2APIC to activate x2APIC mode */
     2204    pThis->enmVersion = PDMAPICVERSION_APIC;
    19502205
    19512206    PVM pVM = PDMDevHlpGetVM(pDevIns);
    … …  
    20452300        {
    20462301            LogRel(("Activating Local APIC\n"));
    2047             pThis->pApicHlpR3->pfnChangeFeature(pDevIns, PDMAPICVERSION_APIC);
     2302            pThis->pApicHlpR3->pfnChangeFeature(pDevIns, pThis->enmVersion);
    20482303        }
    20492304    }
    … …  
    20942349     * Saved state.
    20952350     */
    2096     rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version */,
     2351    rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 2 /* version */,
    20972352                              sizeof(*pThis), NULL, apicSaveExec, NULL, NULL, apicLoadExec, NULL);
    20982353    if (RT_FAILURE(rc))

  • trunk/src/VBox/VMM/PDMInternal.h

    r13020 r13074  
    410410    DECLR3CALLBACKMEMBER(uint8_t,   pfnGetTPRR3,(PPDMDEVINS pDevIns));
    411411    /** @copydoc PDMAPICREG::pfnWriteMSRR3 */
    412     DECLR3CALLBACKMEMBER(uint32_t,  pfnWriteMSRR3, (PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value));
     412    DECLR3CALLBACKMEMBER(uint32_t,  pfnWriteMSRR3, (PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value));
    413413    /** @copydoc PDMAPICREG::pfnReadMSRR3 */
    414     DECLR3CALLBACKMEMBER(uint32_t,  pfnReadMSRR3, (PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value));
     414    DECLR3CALLBACKMEMBER(uint32_t,  pfnReadMSRR3, (PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value));
    415415    /** @copydoc PDMAPICREG::pfnBusDeliverR3 */
    416416    DECLR3CALLBACKMEMBER(void,      pfnBusDeliverR3,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
    … …  
    432432    DECLR0CALLBACKMEMBER(uint8_t,   pfnGetTPRR0,(PPDMDEVINS pDevIns));
    433433     /** @copydoc PDMAPICREG::pfnWriteMSRR3 */
    434     DECLR0CALLBACKMEMBER(uint32_t,  pfnWriteMSRR0, (PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value));
     434    DECLR0CALLBACKMEMBER(uint32_t,  pfnWriteMSRR0, (PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value));
    435435    /** @copydoc PDMAPICREG::pfnReadMSRR3 */
    436     DECLR0CALLBACKMEMBER(uint32_t,  pfnReadMSRR0, (PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value));
     436    DECLR0CALLBACKMEMBER(uint32_t,  pfnReadMSRR0, (PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value));
    437437    /** @copydoc PDMAPICREG::pfnBusDeliverR3 */
    438438    DECLR0CALLBACKMEMBER(void,      pfnBusDeliverR0,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
    … …  
    454454    DECLRCCALLBACKMEMBER(uint8_t,   pfnGetTPRRC,(PPDMDEVINS pDevIns));
    455455    /** @copydoc PDMAPICREG::pfnWriteMSRR3 */
    456     DECLRCCALLBACKMEMBER(uint32_t,  pfnWriteMSRRC, (PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value));
     456    DECLRCCALLBACKMEMBER(uint32_t,  pfnWriteMSRRC, (PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value));
    457457    /** @copydoc PDMAPICREG::pfnReadMSRR3 */
    458     DECLRCCALLBACKMEMBER(uint32_t,  pfnReadMSRRC, (PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value));
     458    DECLRCCALLBACKMEMBER(uint32_t,  pfnReadMSRRC, (PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value));
    459459    /** @copydoc PDMAPICREG::pfnBusDeliverR3 */
    460460    DECLRCCALLBACKMEMBER(void,      pfnBusDeliverRC,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
Note: See TracChangeset for help on using the changeset viewer.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette