Changeset 13702 in vbox for trunk/include/VBox
- Timestamp:
- Oct 31, 2008 12:03:32 AM (16 years ago)
- svn:sync-xref-src-repo-rev:
- 38668
- Location:
- trunk/include/VBox
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/err.h
r13515 r13702 101 101 * resolved there it will enter guru meditation. */ 102 102 #define VINF_EM_DBG_HYPER_ASSERTION 1103 103 /** Hit a ring-0 assertion on EMT. 104 * EM will enter guru mediation state when. */ 105 #define VINF_EM_DBG_RING0_ASSERTION 1104 103 106 /** Indicating that the VM should be suspended for debugging because 104 107 * the developer wants to inspect the VM state. */ 105 #define VINF_EM_DBG_STOP 110 4108 #define VINF_EM_DBG_STOP 1105 106 109 /** Indicating success single stepping and that EM should report that 107 110 * event to the debugger. */ 108 #define VINF_EM_DBG_STEPPED 110 5111 #define VINF_EM_DBG_STEPPED 1106 109 112 /** Indicating that a breakpoint was hit and that EM should notify the debugger 110 113 * and in the event there is no debugger fail fatally. */ 111 #define VINF_EM_DBG_BREAKPOINT 110 6114 #define VINF_EM_DBG_BREAKPOINT 1107 112 115 /** Indicating that EM should single step an instruction. 113 116 * The instruction is stepped in the current execution mode (RAW/REM). */ 114 #define VINF_EM_DBG_STEP 110 7117 #define VINF_EM_DBG_STEP 1108 115 118 /** Indicating that the VM is being turned off and that the EM should 116 119 * exit to the VM awaiting the destruction request. */ 117 #define VINF_EM_OFF 110 8120 #define VINF_EM_OFF 1109 118 121 /** Indicating that the VM has been reset and that scheduling goes 119 122 * back to startup defaults. */ 120 #define VINF_EM_RESET 11 09123 #define VINF_EM_RESET 1110 121 124 /** Indicating that the VM has been suspended and that the the thread 122 125 * should wait for request telling it what to do next. */ 123 #define VINF_EM_SUSPEND 111 0126 #define VINF_EM_SUSPEND 1111 124 127 /** Indicating that the VM has executed a halt instruction and that 125 128 * the emulation thread should wait for an interrupt before resuming 126 129 * execution. */ 127 #define VINF_EM_HALT 111 1130 #define VINF_EM_HALT 1112 128 131 /** Indicating that the VM has been resumed and that the thread should 129 132 * start executing. */ 130 #define VINF_EM_RESUME 111 2133 #define VINF_EM_RESUME 1113 131 134 /** Indicating that we've got an out-of-memory condition and that we need 132 135 * to take the appropriate actions to deal with this. … … 136 139 * with an out-of-memory condition, and even if that should happen the condition 137 140 * will be rediscovered before executing any more code. */ 138 #define VINF_EM_NO_MEMORY 111 3141 #define VINF_EM_NO_MEMORY 1114 139 142 /** The fatal variant of VINF_EM_NO_MEMORY. */ 140 #define VERR_EM_NO_MEMORY (-111 3)143 #define VERR_EM_NO_MEMORY (-1114) 141 144 /** Indicating that a rescheduling to recompiled execution. 142 145 * Typically caused by raw-mode executing code which is difficult/slow 143 146 * to virtualize rawly. 144 147 * @remarks Important to have a higher priority (lower number) than the other rescheduling status codes. */ 145 #define VINF_EM_RESCHEDULE_REM 111 4148 #define VINF_EM_RESCHEDULE_REM 1115 146 149 /** Indicating that a rescheduling to vmx-mode execution. 147 150 * Typically caused by REM detecting that hardware-accelerated raw-mode execution is possible. */ 148 #define VINF_EM_RESCHEDULE_HWACC 111 5151 #define VINF_EM_RESCHEDULE_HWACC 1116 149 152 /** Indicating that a rescheduling to raw-mode execution. 150 153 * Typically caused by REM detecting that raw-mode execution is possible. 151 154 * @remarks Important to have a higher priority (lower number) than VINF_EM_RESCHEDULE. */ 152 #define VINF_EM_RESCHEDULE_RAW 111 6155 #define VINF_EM_RESCHEDULE_RAW 1117 153 156 /** Indicating that a rescheduling now is required. Typically caused by 154 157 * interrupts having changed the EIP. */ 155 #define VINF_EM_RESCHEDULE 111 7158 #define VINF_EM_RESCHEDULE 1118 156 159 /** PARAV call */ 157 #define VINF_EM_RESCHEDULE_PARAV 111 8160 #define VINF_EM_RESCHEDULE_PARAV 1119 158 161 /** Last scheduling related status code. (inclusive) */ 159 #define VINF_EM_LAST 111 8162 #define VINF_EM_LAST 1119 160 163 161 164 /** Reason for leaving GC: Guest trap which couldn't be handled in GC. 162 165 * The trap is generally forwared to the REM and executed there. */ 163 #define VINF_EM_RAW_GUEST_TRAP 112 0166 #define VINF_EM_RAW_GUEST_TRAP 1121 164 167 /** Reason for leaving GC: Interrupted by external interrupt. 165 168 * The interrupt needed to be handled by the host OS. */ 166 #define VINF_EM_RAW_INTERRUPT 112 1169 #define VINF_EM_RAW_INTERRUPT 1122 167 170 /** Reason for leaving GC: Interrupted by external interrupt while in hypervisor code. 168 171 * The interrupt needed to be handled by the host OS and hypervisor execution must be 169 172 * resumed. VM state is not complete at this point. */ 170 #define VINF_EM_RAW_INTERRUPT_HYPER 112 2173 #define VINF_EM_RAW_INTERRUPT_HYPER 1123 171 174 /** Reason for leaving GC: A Ring switch was attempted. 172 175 * Normal cause of action is to execute this in REM. */ 173 #define VINF_EM_RAW_RING_SWITCH 112 3176 #define VINF_EM_RAW_RING_SWITCH 1124 174 177 /** Reason for leaving GC: A Ring switch was attempted using software interrupt. 175 178 * Normal cause of action is to execute this in REM. */ 176 #define VINF_EM_RAW_RING_SWITCH_INT 112 4179 #define VINF_EM_RAW_RING_SWITCH_INT 1125 177 180 /** Reason for leaving GC: A privileged instruction was attempted executed. 178 181 * Normal cause of action is to execute this in REM. */ 179 #define VINF_EM_RAW_EXCEPTION_PRIVILEGED 112 5182 #define VINF_EM_RAW_EXCEPTION_PRIVILEGED 1126 180 183 181 184 /** Reason for leaving GC: Emulate instruction. */ 182 #define VINF_EM_RAW_EMULATE_INSTR 112 6185 #define VINF_EM_RAW_EMULATE_INSTR 1127 183 186 /** Reason for leaving GC: Unhandled TSS write. 184 187 * Recompiler gets control. */ 185 #define VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT 112 7188 #define VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT 1128 186 189 /** Reason for leaving GC: Unhandled LDT write. 187 190 * Recompiler gets control. */ 188 #define VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT 112 8191 #define VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT 1129 189 192 /** Reason for leaving GC: Unhandled IDT write. 190 193 * Recompiler gets control. */ 191 #define VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT 11 29194 #define VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT 1130 192 195 /** Reason for leaving GC: Unhandled GDT write. 193 196 * Recompiler gets control. */ 194 #define VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT 113 0197 #define VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT 1131 195 198 /** Reason for leaving GC: Unhandled Page Directory write. 196 199 * Recompiler gets control. */ 197 #define VINF_EM_RAW_EMULATE_INSTR_PD_FAULT 113 1200 #define VINF_EM_RAW_EMULATE_INSTR_PD_FAULT 1132 198 201 /** Reason for leaving GC: jump inside generated patch jump. 199 202 * Fatal error. */ 200 #define VERR_EM_RAW_PATCH_CONFLICT (-113 2)203 #define VERR_EM_RAW_PATCH_CONFLICT (-1133) 201 204 /** Reason for leaving GC: Hlt instruction. 202 205 * Recompiler gets control. */ 203 #define VINF_EM_RAW_EMULATE_INSTR_HLT 113 3206 #define VINF_EM_RAW_EMULATE_INSTR_HLT 1134 204 207 /** Reason for leaving GC: Ring-3 operation pending. */ 205 #define VINF_EM_RAW_TO_R3 113 4208 #define VINF_EM_RAW_TO_R3 1135 206 209 /** Reason for leaving GC: Timer pending. */ 207 #define VINF_EM_RAW_TIMER_PENDING 113 5210 #define VINF_EM_RAW_TIMER_PENDING 1136 208 211 /** Reason for leaving GC: Interrupt pending (guest). */ 209 #define VINF_EM_RAW_INTERRUPT_PENDING 113 6212 #define VINF_EM_RAW_INTERRUPT_PENDING 1137 210 213 /** Reason for leaving GC: Encountered a stale selector. */ 211 #define VINF_EM_RAW_STALE_SELECTOR 113 7214 #define VINF_EM_RAW_STALE_SELECTOR 1138 212 215 /** Reason for leaving GC: The IRET resuming guest code trapped. */ 213 #define VINF_EM_RAW_IRET_TRAP 113 8216 #define VINF_EM_RAW_IRET_TRAP 1139 214 217 /** The interpreter was unable to deal with the instruction at hand. */ 215 218 #define VERR_EM_INTERPRETER (-1148) -
trunk/include/VBox/err.mac
r10375 r13702 19 19 %define VINF_EM_DBG_HYPER_BREAKPOINT 1102 20 20 %define VINF_EM_DBG_HYPER_ASSERTION 1103 21 %define VINF_EM_DBG_STOP 1104 22 %define VINF_EM_DBG_STEPPED 1105 23 %define VINF_EM_DBG_BREAKPOINT 1106 24 %define VINF_EM_DBG_STEP 1107 25 %define VINF_EM_OFF 1108 26 %define VINF_EM_RESET 1109 27 %define VINF_EM_SUSPEND 1110 28 %define VINF_EM_HALT 1111 29 %define VINF_EM_RESUME 1112 30 %define VINF_EM_NO_MEMORY 1113 31 %define VERR_EM_NO_MEMORY (-1113) 32 %define VINF_EM_RESCHEDULE_REM 1114 33 %define VINF_EM_RESCHEDULE_HWACC 1115 34 %define VINF_EM_RESCHEDULE_RAW 1116 35 %define VINF_EM_RESCHEDULE 1117 36 %define VINF_EM_LAST 1117 37 %define VINF_EM_RAW_GUEST_TRAP 1120 38 %define VINF_EM_RAW_INTERRUPT 1121 39 %define VINF_EM_RAW_INTERRUPT_HYPER 1122 40 %define VINF_EM_RAW_RING_SWITCH 1123 41 %define VINF_EM_RAW_RING_SWITCH_INT 1124 42 %define VINF_EM_RAW_EXCEPTION_PRIVILEGED 1125 43 %define VINF_EM_RAW_EMULATE_INSTR 1126 44 %define VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT 1127 45 %define VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT 1128 46 %define VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT 1129 47 %define VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT 1130 48 %define VINF_EM_RAW_EMULATE_INSTR_PD_FAULT 1131 49 %define VERR_EM_RAW_PATCH_CONFLICT (-1132) 50 %define VINF_EM_RAW_EMULATE_INSTR_HLT 1133 51 %define VINF_EM_RAW_TO_R3 1134 52 %define VINF_EM_RAW_TIMER_PENDING 1135 53 %define VINF_EM_RAW_INTERRUPT_PENDING 1136 54 %define VINF_EM_RAW_STALE_SELECTOR 1137 55 %define VINF_EM_RAW_IRET_TRAP 1138 21 %define VINF_EM_DBG_RING0_ASSERTION 1104 22 %define VINF_EM_DBG_STOP 1105 23 %define VINF_EM_DBG_STEPPED 1106 24 %define VINF_EM_DBG_BREAKPOINT 1107 25 %define VINF_EM_DBG_STEP 1108 26 %define VINF_EM_OFF 1109 27 %define VINF_EM_RESET 1110 28 %define VINF_EM_SUSPEND 1111 29 %define VINF_EM_HALT 1112 30 %define VINF_EM_RESUME 1113 31 %define VINF_EM_NO_MEMORY 1114 32 %define VERR_EM_NO_MEMORY (-1114) 33 %define VINF_EM_RESCHEDULE_REM 1115 34 %define VINF_EM_RESCHEDULE_HWACC 1116 35 %define VINF_EM_RESCHEDULE_RAW 1117 36 %define VINF_EM_RESCHEDULE 1118 37 %define VINF_EM_RESCHEDULE_PARAV 1119 38 %define VINF_EM_LAST 1119 39 %define VINF_EM_RAW_GUEST_TRAP 1121 40 %define VINF_EM_RAW_INTERRUPT 1122 41 %define VINF_EM_RAW_INTERRUPT_HYPER 1123 42 %define VINF_EM_RAW_RING_SWITCH 1124 43 %define VINF_EM_RAW_RING_SWITCH_INT 1125 44 %define VINF_EM_RAW_EXCEPTION_PRIVILEGED 1126 45 %define VINF_EM_RAW_EMULATE_INSTR 1127 46 %define VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT 1128 47 %define VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT 1129 48 %define VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT 1130 49 %define VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT 1131 50 %define VINF_EM_RAW_EMULATE_INSTR_PD_FAULT 1132 51 %define VERR_EM_RAW_PATCH_CONFLICT (-1133) 52 %define VINF_EM_RAW_EMULATE_INSTR_HLT 1134 53 %define VINF_EM_RAW_TO_R3 1135 54 %define VINF_EM_RAW_TIMER_PENDING 1136 55 %define VINF_EM_RAW_INTERRUPT_PENDING 1137 56 %define VINF_EM_RAW_STALE_SELECTOR 1138 57 %define VINF_EM_RAW_IRET_TRAP 1139 56 58 %define VERR_EM_INTERPRETER (-1148) 57 59 %define VERR_EM_INTERNAL_ERROR (-1149) … … 343 345 %define VERR_VDI_BLOCK_FREE (-3215) 344 346 %define VERR_VDI_VALUE_NOT_FOUND (-3216) 347 %define VERR_VDI_UNKNOWN_CFG_VALUES (-3217) 348 %define VINF_VDI_ASYNC_IO_FINISHED 3218 349 %define VERR_VDI_ASYNC_IO_IN_PROGRESS (-3219) 345 350 %define VERR_VBGL_NOT_INITIALIZED (-3300) 346 351 %define VERR_VBGL_INVALID_ADDR (-3301) … … 358 363 %define VERR_INTNET_FLT_IF_BUSY (-3601) 359 364 %define VERR_INTNET_FLT_IF_FAILED (-3602) 365 %define VERR_INTNET_INCOMPATIBLE_TRUNK (-3603) 366 %define VERR_INTNET_INCOMPATIBLE_FLAGS (-3604) 360 367 %define VERR_SUPDRV_COMPONENT_NOT_FOUND (-3700) 361 368 %define VERR_SUPDRV_INTERFACE_NOT_SUPPORTED (-3701) … … 392 399 %define VERR_VMX_X86_CR4_VMXE_CLEARED (-4012) 393 400 %define VERR_VMX_MSR_LOCKED_OR_DISABLED (-4013) 401 %define VERR_VMX_INVALID_GUEST_STATE (-4014) 402 %define VERR_VMX_UNEXPECTED_EXIT_CODE (-4015) 403 %define VERR_VMX_UNEXPECTED_EXCEPTION (-4016) 404 %define VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE (-4017) 394 405 %define VERR_SVM_UNABLE_TO_START_VM (-4050) 395 406 %define VERR_SVM_ILLEGAL_EFER_MSR (-4051) … … 398 409 %define VERR_HWACCM_UNKNOWN_CPU (-4100) 399 410 %define VERR_HWACCM_NO_CPUID (-4101) 411 %define VERR_HWACCM_SUSPEND_PENDING (-4102) 400 412 %define VERR_DIS_INVALID_OPCODE (-4200) 401 413 %define VERR_DIS_GEN_FAILURE (-4201) … … 405 417 %define VERR_WEB_INVALID_OBJECT_ID (-4303) 406 418 %define VERR_WEB_UNSUPPORTED_INTERFACE (-4304) 419 %define VINF_PARAV_SWITCH_TO_HOST 4400 407 420 %include "iprt/err.mac" -
trunk/include/VBox/x86.mac
r10648 r13702 35 35 %define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13) 36 36 %define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14) 37 %define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21) 37 38 %define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23) 38 39 %define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0) … … 104 105 %define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12) 105 106 %define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13) 107 %define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0) 108 %define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1) 109 %define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2) 110 %define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3) 111 %define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4) 112 %define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5) 113 %define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6) 114 %define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7) 115 %define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8) 106 116 %define X86_CR0_PE RT_BIT(0) 107 117 %define X86_CR0_PROTECTION_ENABLE RT_BIT(0) … … 150 160 %define X86_DR6_BS RT_BIT(14) 151 161 %define X86_DR6_BT RT_BIT(15) 162 %define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0) 152 163 %define X86_DR7_L0 RT_BIT(0) 153 164 %define X86_DR7_G0 RT_BIT(1) … … 170 181 %define X86_DR7_LEN3_MASK (3 << 30) 171 182 %define X86_DR7_MB1_MASK (RT_BIT(10)) 172 %define X86_DR7_L(iBp) ( 1<< (iBp * 2) )173 %define X86_DR7_G(iBp) ( 1<< (iBp * 2 + 1) )183 %define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) ) 184 %define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) ) 174 185 %define X86_DR7_RW_EO 0 175 186 %define X86_DR7_RW_WO 1 … … 179 190 %define X86_DR7_LEN_BYTE 0 180 191 %define X86_DR7_LEN_WORD 1 181 %define X86_DR7_LEN_QWORD 2 ;/**< AMD64 long mode only. */192 %define X86_DR7_LEN_QWORD 2 182 193 %define X86_DR7_LEN_DWORD 3 183 194 %define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) ) 184 %define X86_DR7_ENABLED_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(6) | RT_BIT(7)) 195 %define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U) 196 %define X86_DR7_ENABLED_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7)) 197 %define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) | X86_DR7_RW(1, X86_DR7_RW_IO) | X86_DR7_RW(2, X86_DR7_RW_IO) | X86_DR7_RW(3, X86_DR7_RW_IO)) 198 %define X86_DR7_INIT_VAL 0x400 185 199 %define MSR_IA32_TSC 0x10 200 %define MSR_IA32_PLATFORM_ID 0x17 186 201 %define MSR_IA32_APICBASE 0x1b 187 202 %define MSR_IA32_FEATURE_CONTROL 0x3A 188 203 %define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0) 189 204 %define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2) 205 %define MSR_IA32_BIOS_UPDT_TRIG 0x79 206 %define MSR_IA32_BIOS_SIGN_ID 0x8B 190 207 %define MSR_IA32_MTRR_CAP 0xFE 191 208 %define MSR_IA32_SYSENTER_CS 0x174 … … 197 214 %define MSR_IA32_CR_PAT 0x277 198 215 %define MSR_IA32_MTRR_DEF_TYPE 0x2FF 216 %define MSR_IA32_MC0_CTL 0x400 217 %define MSR_IA32_MC0_STATUS 0x401 199 218 %define MSR_IA32_VMX_BASIC_INFO 0x480 200 219 %define MSR_IA32_VMX_PINBASED_CTLS 0x481 … … 208 227 %define MSR_IA32_VMX_CR4_FIXED1 0x489 209 228 %define MSR_IA32_VMX_VMCS_ENUM 0x48A 229 %define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B 230 %define MSR_IA32_VMX_EPT_CAPS 0x48C 231 %define MSR_IA32_APIC_START 0x800 232 %define MSR_IA32_APIC_END 0x900 210 233 %define MSR_K6_EFER 0xc0000080 211 234 %define MSR_K6_EFER_SCE RT_BIT(0) … … 262 285 %define X86_PAGE_4K_OFFSET_MASK 0xfff 263 286 %define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL 264 %define X86_PAGE_4K_BASE_MASK_32 0xfffff000 U287 %define X86_PAGE_4K_BASE_MASK_32 0xfffff000 265 288 %define X86_PAGE_2M_SIZE _2M 266 289 %define X86_PAGE_2M_SHIFT 21 267 290 %define X86_PAGE_2M_OFFSET_MASK 0x001fffff 268 291 %define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL 269 %define X86_PAGE_2M_BASE_MASK_32 0xffe00000 U292 %define X86_PAGE_2M_BASE_MASK_32 0xffe00000 270 293 %define X86_PAGE_4M_SIZE _4M 271 294 %define X86_PAGE_4M_SHIFT 22 272 295 %define X86_PAGE_4M_OFFSET_MASK 0x003fffff 273 296 %define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL 274 %define X86_PAGE_4M_BASE_MASK_32 0xffc00000 U297 %define X86_PAGE_4M_BASE_MASK_32 0xffc00000 275 298 %define X86_PTE_P RT_BIT(0) 276 299 %define X86_PTE_RW RT_BIT(1) … … 422 445 %define X86_TRAP_PF_RSVD RT_BIT(3) 423 446 %define X86_TRAP_PF_ID RT_BIT(4) 424
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