Index: trunk/include/VBox/err.h
===================================================================
--- trunk/include/VBox/err.h	(revision 13701)
+++ trunk/include/VBox/err.h	(revision 13702)
@@ -101,32 +101,35 @@
  * resolved there it will enter guru meditation. */
 #define VINF_EM_DBG_HYPER_ASSERTION         1103
+/** Hit a ring-0 assertion on EMT.
+ * EM will enter guru mediation state when. */
+#define VINF_EM_DBG_RING0_ASSERTION         1104
 /** Indicating that the VM should be suspended for debugging because
  * the developer wants to inspect the VM state. */
-#define VINF_EM_DBG_STOP                    1104
+#define VINF_EM_DBG_STOP                    1105
 /** Indicating success single stepping and that EM should report that
  * event to the debugger. */
-#define VINF_EM_DBG_STEPPED                 1105
+#define VINF_EM_DBG_STEPPED                 1106
 /** Indicating that a breakpoint was hit and that EM should notify the debugger
  * and in the event there is no debugger fail fatally. */
-#define VINF_EM_DBG_BREAKPOINT              1106
+#define VINF_EM_DBG_BREAKPOINT              1107
 /** Indicating that EM should single step an instruction.
  * The instruction is stepped in the current execution mode (RAW/REM). */
-#define VINF_EM_DBG_STEP                    1107
+#define VINF_EM_DBG_STEP                    1108
 /** Indicating that the VM is being turned off and that the EM should
  * exit to the VM awaiting the destruction request. */
-#define VINF_EM_OFF                         1108
+#define VINF_EM_OFF                         1109
 /** Indicating that the VM has been reset and that scheduling goes
  * back to startup defaults. */
-#define VINF_EM_RESET                       1109
+#define VINF_EM_RESET                       1110
 /** Indicating that the VM has been suspended and that the the thread
  * should wait for request telling it what to do next. */
-#define VINF_EM_SUSPEND                     1110
+#define VINF_EM_SUSPEND                     1111
 /** Indicating that the VM has executed a halt instruction and that
  * the emulation thread should wait for an interrupt before resuming
  * execution. */
-#define VINF_EM_HALT                        1111
+#define VINF_EM_HALT                        1112
 /** Indicating that the VM has been resumed and that the thread should
  * start executing. */
-#define VINF_EM_RESUME                      1112
+#define VINF_EM_RESUME                      1113
 /** Indicating that we've got an out-of-memory condition and that we need
  * to take the appropriate actions to deal with this.
@@ -136,80 +139,80 @@
  *          with an out-of-memory condition, and even if that should happen the condition
  *          will be rediscovered before executing any more code. */
-#define VINF_EM_NO_MEMORY                   1113
+#define VINF_EM_NO_MEMORY                   1114
 /** The fatal variant of VINF_EM_NO_MEMORY. */
-#define VERR_EM_NO_MEMORY                   (-1113)
+#define VERR_EM_NO_MEMORY                   (-1114)
 /** Indicating that a rescheduling to recompiled execution.
  * Typically caused by raw-mode executing code which is difficult/slow
  * to virtualize rawly.
  * @remarks Important to have a higher priority (lower number) than the other rescheduling status codes. */
-#define VINF_EM_RESCHEDULE_REM              1114
+#define VINF_EM_RESCHEDULE_REM              1115
 /** Indicating that a rescheduling to vmx-mode execution.
  * Typically caused by REM detecting that hardware-accelerated raw-mode execution is possible. */
-#define VINF_EM_RESCHEDULE_HWACC            1115
+#define VINF_EM_RESCHEDULE_HWACC            1116
 /** Indicating that a rescheduling to raw-mode execution.
  * Typically caused by REM detecting that raw-mode execution is possible.
  * @remarks Important to have a higher priority (lower number) than VINF_EM_RESCHEDULE. */
-#define VINF_EM_RESCHEDULE_RAW              1116
+#define VINF_EM_RESCHEDULE_RAW              1117
 /** Indicating that a rescheduling now is required. Typically caused by
  * interrupts having changed the EIP. */
-#define VINF_EM_RESCHEDULE                  1117
+#define VINF_EM_RESCHEDULE                  1118
 /** PARAV call */
-#define VINF_EM_RESCHEDULE_PARAV            1118
+#define VINF_EM_RESCHEDULE_PARAV            1119
 /** Last scheduling related status code. (inclusive) */
-#define VINF_EM_LAST                        1118
+#define VINF_EM_LAST                        1119
 
 /** Reason for leaving GC: Guest trap which couldn't be handled in GC.
  * The trap is generally forwared to the REM and executed there. */
-#define VINF_EM_RAW_GUEST_TRAP              1120
+#define VINF_EM_RAW_GUEST_TRAP              1121
 /** Reason for leaving GC: Interrupted by external interrupt.
  * The interrupt needed to be handled by the host OS. */
-#define VINF_EM_RAW_INTERRUPT               1121
+#define VINF_EM_RAW_INTERRUPT               1122
 /** Reason for leaving GC: Interrupted by external interrupt while in hypervisor code.
  * The interrupt needed to be handled by the host OS and hypervisor execution must be
  * resumed. VM state is not complete at this point. */
-#define VINF_EM_RAW_INTERRUPT_HYPER         1122
+#define VINF_EM_RAW_INTERRUPT_HYPER         1123
 /** Reason for leaving GC: A Ring switch was attempted.
  * Normal cause of action is to execute this in REM. */
-#define VINF_EM_RAW_RING_SWITCH             1123
+#define VINF_EM_RAW_RING_SWITCH             1124
 /** Reason for leaving GC: A Ring switch was attempted using software interrupt.
  * Normal cause of action is to execute this in REM. */
-#define VINF_EM_RAW_RING_SWITCH_INT         1124
+#define VINF_EM_RAW_RING_SWITCH_INT         1125
 /** Reason for leaving GC: A privileged instruction was attempted executed.
  * Normal cause of action is to execute this in REM. */
-#define VINF_EM_RAW_EXCEPTION_PRIVILEGED    1125
+#define VINF_EM_RAW_EXCEPTION_PRIVILEGED    1126
 
 /** Reason for leaving GC: Emulate instruction. */
-#define VINF_EM_RAW_EMULATE_INSTR           1126
+#define VINF_EM_RAW_EMULATE_INSTR           1127
 /** Reason for leaving GC: Unhandled TSS write.
  * Recompiler gets control. */
-#define VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT 1127
+#define VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT 1128
 /** Reason for leaving GC: Unhandled LDT write.
  * Recompiler gets control. */
-#define VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT 1128
+#define VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT 1129
 /** Reason for leaving GC: Unhandled IDT write.
  * Recompiler gets control. */
-#define VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT 1129
+#define VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT 1130
 /** Reason for leaving GC: Unhandled GDT write.
  * Recompiler gets control. */
-#define VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT 1130
+#define VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT 1131
 /** Reason for leaving GC: Unhandled Page Directory write.
  * Recompiler gets control. */
-#define VINF_EM_RAW_EMULATE_INSTR_PD_FAULT  1131
+#define VINF_EM_RAW_EMULATE_INSTR_PD_FAULT  1132
 /** Reason for leaving GC: jump inside generated patch jump.
  * Fatal error. */
-#define VERR_EM_RAW_PATCH_CONFLICT          (-1132)
+#define VERR_EM_RAW_PATCH_CONFLICT          (-1133)
 /** Reason for leaving GC: Hlt instruction.
  * Recompiler gets control. */
-#define VINF_EM_RAW_EMULATE_INSTR_HLT       1133
+#define VINF_EM_RAW_EMULATE_INSTR_HLT       1134
 /** Reason for leaving GC: Ring-3 operation pending. */
-#define VINF_EM_RAW_TO_R3                   1134
+#define VINF_EM_RAW_TO_R3                   1135
 /** Reason for leaving GC: Timer pending. */
-#define VINF_EM_RAW_TIMER_PENDING           1135
+#define VINF_EM_RAW_TIMER_PENDING           1136
 /** Reason for leaving GC: Interrupt pending (guest). */
-#define VINF_EM_RAW_INTERRUPT_PENDING       1136
+#define VINF_EM_RAW_INTERRUPT_PENDING       1137
 /** Reason for leaving GC: Encountered a stale selector. */
-#define VINF_EM_RAW_STALE_SELECTOR          1137
+#define VINF_EM_RAW_STALE_SELECTOR          1138
 /** Reason for leaving GC: The IRET resuming guest code trapped. */
-#define VINF_EM_RAW_IRET_TRAP               1138
+#define VINF_EM_RAW_IRET_TRAP               1139
 /** The interpreter was unable to deal with the instruction at hand. */
 #define VERR_EM_INTERPRETER                 (-1148)
Index: trunk/include/VBox/err.mac
===================================================================
--- trunk/include/VBox/err.mac	(revision 13701)
+++ trunk/include/VBox/err.mac	(revision 13702)
@@ -19,39 +19,41 @@
 %define VINF_EM_DBG_HYPER_BREAKPOINT    1102
 %define VINF_EM_DBG_HYPER_ASSERTION    1103
-%define VINF_EM_DBG_STOP    1104
-%define VINF_EM_DBG_STEPPED    1105
-%define VINF_EM_DBG_BREAKPOINT    1106
-%define VINF_EM_DBG_STEP    1107
-%define VINF_EM_OFF    1108
-%define VINF_EM_RESET    1109
-%define VINF_EM_SUSPEND    1110
-%define VINF_EM_HALT    1111
-%define VINF_EM_RESUME    1112
-%define VINF_EM_NO_MEMORY    1113
-%define VERR_EM_NO_MEMORY    (-1113)
-%define VINF_EM_RESCHEDULE_REM    1114
-%define VINF_EM_RESCHEDULE_HWACC    1115
-%define VINF_EM_RESCHEDULE_RAW    1116
-%define VINF_EM_RESCHEDULE    1117
-%define VINF_EM_LAST    1117
-%define VINF_EM_RAW_GUEST_TRAP    1120
-%define VINF_EM_RAW_INTERRUPT    1121
-%define VINF_EM_RAW_INTERRUPT_HYPER    1122
-%define VINF_EM_RAW_RING_SWITCH    1123
-%define VINF_EM_RAW_RING_SWITCH_INT    1124
-%define VINF_EM_RAW_EXCEPTION_PRIVILEGED    1125
-%define VINF_EM_RAW_EMULATE_INSTR    1126
-%define VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT    1127
-%define VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT    1128
-%define VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT    1129
-%define VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT    1130
-%define VINF_EM_RAW_EMULATE_INSTR_PD_FAULT    1131
-%define VERR_EM_RAW_PATCH_CONFLICT    (-1132)
-%define VINF_EM_RAW_EMULATE_INSTR_HLT    1133
-%define VINF_EM_RAW_TO_R3    1134
-%define VINF_EM_RAW_TIMER_PENDING    1135
-%define VINF_EM_RAW_INTERRUPT_PENDING    1136
-%define VINF_EM_RAW_STALE_SELECTOR    1137
-%define VINF_EM_RAW_IRET_TRAP    1138
+%define VINF_EM_DBG_RING0_ASSERTION    1104
+%define VINF_EM_DBG_STOP    1105
+%define VINF_EM_DBG_STEPPED    1106
+%define VINF_EM_DBG_BREAKPOINT    1107
+%define VINF_EM_DBG_STEP    1108
+%define VINF_EM_OFF    1109
+%define VINF_EM_RESET    1110
+%define VINF_EM_SUSPEND    1111
+%define VINF_EM_HALT    1112
+%define VINF_EM_RESUME    1113
+%define VINF_EM_NO_MEMORY    1114
+%define VERR_EM_NO_MEMORY    (-1114)
+%define VINF_EM_RESCHEDULE_REM    1115
+%define VINF_EM_RESCHEDULE_HWACC    1116
+%define VINF_EM_RESCHEDULE_RAW    1117
+%define VINF_EM_RESCHEDULE    1118
+%define VINF_EM_RESCHEDULE_PARAV    1119
+%define VINF_EM_LAST    1119
+%define VINF_EM_RAW_GUEST_TRAP    1121
+%define VINF_EM_RAW_INTERRUPT    1122
+%define VINF_EM_RAW_INTERRUPT_HYPER    1123
+%define VINF_EM_RAW_RING_SWITCH    1124
+%define VINF_EM_RAW_RING_SWITCH_INT    1125
+%define VINF_EM_RAW_EXCEPTION_PRIVILEGED    1126
+%define VINF_EM_RAW_EMULATE_INSTR    1127
+%define VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT    1128
+%define VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT    1129
+%define VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT    1130
+%define VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT    1131
+%define VINF_EM_RAW_EMULATE_INSTR_PD_FAULT    1132
+%define VERR_EM_RAW_PATCH_CONFLICT    (-1133)
+%define VINF_EM_RAW_EMULATE_INSTR_HLT    1134
+%define VINF_EM_RAW_TO_R3    1135
+%define VINF_EM_RAW_TIMER_PENDING    1136
+%define VINF_EM_RAW_INTERRUPT_PENDING    1137
+%define VINF_EM_RAW_STALE_SELECTOR    1138
+%define VINF_EM_RAW_IRET_TRAP    1139
 %define VERR_EM_INTERPRETER    (-1148)
 %define VERR_EM_INTERNAL_ERROR    (-1149)
@@ -343,4 +345,7 @@
 %define VERR_VDI_BLOCK_FREE    (-3215)
 %define VERR_VDI_VALUE_NOT_FOUND    (-3216)
+%define VERR_VDI_UNKNOWN_CFG_VALUES    (-3217)
+%define VINF_VDI_ASYNC_IO_FINISHED    3218
+%define VERR_VDI_ASYNC_IO_IN_PROGRESS    (-3219)
 %define VERR_VBGL_NOT_INITIALIZED    (-3300)
 %define VERR_VBGL_INVALID_ADDR    (-3301)
@@ -358,4 +363,6 @@
 %define VERR_INTNET_FLT_IF_BUSY    (-3601)
 %define VERR_INTNET_FLT_IF_FAILED    (-3602)
+%define VERR_INTNET_INCOMPATIBLE_TRUNK    (-3603)
+%define VERR_INTNET_INCOMPATIBLE_FLAGS    (-3604)
 %define VERR_SUPDRV_COMPONENT_NOT_FOUND    (-3700)
 %define VERR_SUPDRV_INTERFACE_NOT_SUPPORTED    (-3701)
@@ -392,4 +399,8 @@
 %define VERR_VMX_X86_CR4_VMXE_CLEARED    (-4012)
 %define VERR_VMX_MSR_LOCKED_OR_DISABLED    (-4013)
+%define VERR_VMX_INVALID_GUEST_STATE    (-4014)
+%define VERR_VMX_UNEXPECTED_EXIT_CODE    (-4015)
+%define VERR_VMX_UNEXPECTED_EXCEPTION    (-4016)
+%define VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE    (-4017)
 %define VERR_SVM_UNABLE_TO_START_VM    (-4050)
 %define VERR_SVM_ILLEGAL_EFER_MSR    (-4051)
@@ -398,4 +409,5 @@
 %define VERR_HWACCM_UNKNOWN_CPU    (-4100)
 %define VERR_HWACCM_NO_CPUID    (-4101)
+%define VERR_HWACCM_SUSPEND_PENDING    (-4102)
 %define VERR_DIS_INVALID_OPCODE    (-4200)
 %define VERR_DIS_GEN_FAILURE    (-4201)
@@ -405,3 +417,4 @@
 %define VERR_WEB_INVALID_OBJECT_ID    (-4303)
 %define VERR_WEB_UNSUPPORTED_INTERFACE    (-4304)
+%define VINF_PARAV_SWITCH_TO_HOST    4400
 %include "iprt/err.mac"
Index: trunk/include/VBox/x86.mac
===================================================================
--- trunk/include/VBox/x86.mac	(revision 13701)
+++ trunk/include/VBox/x86.mac	(revision 13702)
@@ -35,4 +35,5 @@
 %define X86_CPUID_FEATURE_ECX_CX16      RT_BIT(13)
 %define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
+%define X86_CPUID_FEATURE_ECX_X2APIC    RT_BIT(21)
 %define X86_CPUID_FEATURE_ECX_POPCOUNT  RT_BIT(23)
 %define X86_CPUID_FEATURE_EDX_FPU       RT_BIT(0)
@@ -104,4 +105,13 @@
 %define X86_CPUID_AMD_FEATURE_ECX_SKINIT    RT_BIT(12)
 %define X86_CPUID_AMD_FEATURE_ECX_WDT       RT_BIT(13)
+%define X86_CPUID_AMD_ADVPOWER_EDX_TS        RT_BIT(0)
+%define X86_CPUID_AMD_ADVPOWER_EDX_FID       RT_BIT(1)
+%define X86_CPUID_AMD_ADVPOWER_EDX_VID       RT_BIT(2)
+%define X86_CPUID_AMD_ADVPOWER_EDX_TTP       RT_BIT(3)
+%define X86_CPUID_AMD_ADVPOWER_EDX_TM        RT_BIT(4)
+%define X86_CPUID_AMD_ADVPOWER_EDX_STC       RT_BIT(5)
+%define X86_CPUID_AMD_ADVPOWER_EDX_MC        RT_BIT(6)
+%define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE  RT_BIT(7)
+%define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR  RT_BIT(8)
 %define X86_CR0_PE                          RT_BIT(0)
 %define X86_CR0_PROTECTION_ENABLE           RT_BIT(0)
@@ -150,4 +160,5 @@
 %define X86_DR6_BS                          RT_BIT(14)
 %define X86_DR6_BT                          RT_BIT(15)
+%define X86_DR6_INIT_VAL                    UINT64_C(0xFFFF0FF0)
 %define X86_DR7_L0                          RT_BIT(0)
 %define X86_DR7_G0                          RT_BIT(1)
@@ -170,6 +181,6 @@
 %define X86_DR7_LEN3_MASK                   (3 << 30)
 %define X86_DR7_MB1_MASK                    (RT_BIT(10))
-%define X86_DR7_L(iBp)                      ( 1 << (iBp * 2) )
-%define X86_DR7_G(iBp)                      ( 1 << (iBp * 2 + 1) )
+%define X86_DR7_L(iBp)                      ( UINT32_C(1) << (iBp * 2) )
+%define X86_DR7_G(iBp)                      ( UINT32_C(1) << (iBp * 2 + 1) )
 %define X86_DR7_RW_EO                       0
 %define X86_DR7_RW_WO                       1
@@ -179,13 +190,19 @@
 %define X86_DR7_LEN_BYTE                    0
 %define X86_DR7_LEN_WORD                    1
-%define X86_DR7_LEN_QWORD                   2 ;/**< AMD64 long mode only. */
+%define X86_DR7_LEN_QWORD                   2
 %define X86_DR7_LEN_DWORD                   3
 %define X86_DR7_LEN(iBp, cb)                ( (cb) << ((iBp) * 4 + 18) )
-%define X86_DR7_ENABLED_MASK                (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(6) | RT_BIT(7))
+%define X86_DR7_GET_LEN(uDR7, iBp)          ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
+%define X86_DR7_ENABLED_MASK                (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7))
+%define X86_DR7_IO_ENABLED_MASK             (X86_DR7_RW(0, X86_DR7_RW_IO) | X86_DR7_RW(1, X86_DR7_RW_IO) | X86_DR7_RW(2, X86_DR7_RW_IO) | X86_DR7_RW(3, X86_DR7_RW_IO))
+%define X86_DR7_INIT_VAL                    0x400
 %define MSR_IA32_TSC                        0x10
+%define MSR_IA32_PLATFORM_ID                0x17
 %define MSR_IA32_APICBASE                   0x1b
 %define MSR_IA32_FEATURE_CONTROL            0x3A
 %define MSR_IA32_FEATURE_CONTROL_LOCK       RT_BIT(0)
 %define MSR_IA32_FEATURE_CONTROL_VMXON      RT_BIT(2)
+%define MSR_IA32_BIOS_UPDT_TRIG             0x79
+%define MSR_IA32_BIOS_SIGN_ID               0x8B
 %define MSR_IA32_MTRR_CAP                   0xFE
 %define MSR_IA32_SYSENTER_CS                0x174
@@ -197,4 +214,6 @@
 %define MSR_IA32_CR_PAT                     0x277
 %define MSR_IA32_MTRR_DEF_TYPE              0x2FF
+%define MSR_IA32_MC0_CTL                    0x400
+%define MSR_IA32_MC0_STATUS                 0x401
 %define MSR_IA32_VMX_BASIC_INFO             0x480
 %define MSR_IA32_VMX_PINBASED_CTLS          0x481
@@ -208,4 +227,8 @@
 %define MSR_IA32_VMX_CR4_FIXED1             0x489
 %define MSR_IA32_VMX_VMCS_ENUM              0x48A
+%define MSR_IA32_VMX_PROCBASED_CTLS2        0x48B
+%define MSR_IA32_VMX_EPT_CAPS               0x48C
+%define MSR_IA32_APIC_START                 0x800
+%define MSR_IA32_APIC_END                   0x900
 %define MSR_K6_EFER                         0xc0000080
 %define  MSR_K6_EFER_SCE                     RT_BIT(0)
@@ -262,15 +285,15 @@
 %define X86_PAGE_4K_OFFSET_MASK             0xfff
 %define X86_PAGE_4K_BASE_MASK               0xfffffffffffff000ULL
-%define X86_PAGE_4K_BASE_MASK_32            0xfffff000U
+%define X86_PAGE_4K_BASE_MASK_32            0xfffff000
 %define X86_PAGE_2M_SIZE                    _2M
 %define X86_PAGE_2M_SHIFT                   21
 %define X86_PAGE_2M_OFFSET_MASK             0x001fffff
 %define X86_PAGE_2M_BASE_MASK               0xffffffffffe00000ULL
-%define X86_PAGE_2M_BASE_MASK_32            0xffe00000U
+%define X86_PAGE_2M_BASE_MASK_32            0xffe00000
 %define X86_PAGE_4M_SIZE                    _4M
 %define X86_PAGE_4M_SHIFT                   22
 %define X86_PAGE_4M_OFFSET_MASK             0x003fffff
 %define X86_PAGE_4M_BASE_MASK               0xffffffffffc00000ULL
-%define X86_PAGE_4M_BASE_MASK_32            0xffc00000U
+%define X86_PAGE_4M_BASE_MASK_32            0xffc00000
 %define X86_PTE_P                           RT_BIT(0)
 %define X86_PTE_RW                          RT_BIT(1)
@@ -422,3 +445,2 @@
 %define X86_TRAP_PF_RSVD            RT_BIT(3)
 %define X86_TRAP_PF_ID              RT_BIT(4)
-
Index: trunk/include/iprt/err.mac
===================================================================
--- trunk/include/iprt/err.mac	(revision 13701)
+++ trunk/include/iprt/err.mac	(revision 13702)
@@ -85,4 +85,6 @@
 %define VERR_OUT_OF_RESOURCES    (-80)
 %define VWRN_OUT_OF_RESOURCES    80
+%define VERR_NO_MORE_HANDLES    (-81)
+%define VERR_PREEMPT_DISABLED    (-82)
 %define VERR_FILE_IO_ERROR    (-100)
 %define VERR_OPEN_FAILED    (-101)
@@ -258,2 +260,4 @@
 %define VERR_GETOPT_REQUIRED_ARGUMENT_MISSING    (-826)
 %define VERR_GETOPT_INVALID_ARGUMENT_FORMAT    (-827)
+%define VERR_CACHE_FULL    (-850)
+%define VERR_CACHE_EMPTY    (-851)
