Changeset 13823 in vbox for trunk/src/VBox/VMM/VMMAll
- Timestamp:
- Nov 5, 2008 1:10:20 AM (16 years ago)
- svn:sync-xref-src-repo-rev:
- 38814
- Location:
- trunk/src/VBox/VMM/VMMAll
- Files:
-
- 11 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/EMAll.cpp
r13822 r13823 103 103 # ifdef IN_RING0 104 104 int rc = PGMPhysSimpleReadGCPtr(pVM, pDest, pSrc, cb); 105 AssertMsgRC(rc, ("PGMPhysSimpleReadGCPtr failed for pSrc=% VGv cb=%x\n", pSrc, cb));105 AssertMsgRC(rc, ("PGMPhysSimpleReadGCPtr failed for pSrc=%RGv cb=%x\n", pSrc, cb)); 106 106 # else /* IN_RING3 */ 107 107 if (!PATMIsPatchGCAddr(pVM, pSrc)) … … 154 154 if (RT_FAILURE(rc)) 155 155 { 156 Log(("EMInterpretDisasOne: Failed to convert %RTsel:% VGv (cpl=%d) - rc=%Rrc !!\n",156 Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n", 157 157 pCtxCore->cs, (RTGCPTR)pCtxCore->rip, pCtxCore->ss & X86_SEL_RPL, rc)); 158 158 return rc; … … 184 184 if (RT_SUCCESS(rc)) 185 185 return VINF_SUCCESS; 186 AssertMsgFailed(("DISCoreOne failed to GCPtrInstr=% VGv rc=%Rrc\n", GCPtrInstr, rc));186 AssertMsgFailed(("DISCoreOne failed to GCPtrInstr=%RGv rc=%Rrc\n", GCPtrInstr, rc)); 187 187 return VERR_INTERNAL_ERROR; 188 188 } … … 211 211 RTGCPTR pbCode; 212 212 213 LogFlow(("EMInterpretInstruction %RGv fault % VGv\n", (RTGCPTR)pRegFrame->rip, pvFault));213 LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault)); 214 214 int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode); 215 215 if (RT_SUCCESS(rc)) … … 457 457 if (RT_FAILURE(rc)) 458 458 { 459 AssertMsgFailed(("MMGCRamRead % VGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));459 AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc)); 460 460 return VERR_EM_INTERPRETER; 461 461 } … … 476 476 if (RT_FAILURE(rc)) 477 477 { 478 AssertMsgFailed(("MMGCRamRead % VGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));478 AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc)); 479 479 } 480 480 break; … … 510 510 if (RT_FAILURE(rc)) 511 511 { 512 AssertMsgFailed(("emRamWrite % VGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));512 AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc)); 513 513 return VERR_EM_INTERPRETER; 514 514 } … … 536 536 if (RT_FAILURE(rc)) 537 537 { 538 AssertMsgFailed(("emRamWrite % VGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));538 AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc)); 539 539 return VERR_EM_INTERPRETER; 540 540 } … … 583 583 if (RT_FAILURE(rc)) 584 584 { 585 AssertMsgFailed(("emRamRead % VGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));585 AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc)); 586 586 return VERR_EM_INTERPRETER; 587 587 } … … 601 601 if (RT_FAILURE(rc)) 602 602 { 603 AssertMsgFailed(("emRamWrite % VGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));603 AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc)); 604 604 return VERR_EM_INTERPRETER; 605 605 } … … 653 653 if (RT_FAILURE(rc)) 654 654 { 655 AssertMsgFailed(("emRamRead % VGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));655 AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc)); 656 656 return VERR_EM_INTERPRETER; 657 657 } … … 674 674 if (RT_FAILURE(rc)) 675 675 { 676 AssertMsgFailed(("emRamWrite % VGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));676 AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc)); 677 677 return VERR_EM_INTERPRETER; 678 678 } … … 745 745 if (RT_FAILURE(rc)) 746 746 { 747 AssertMsgFailed(("emRamRead % VGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));747 AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc)); 748 748 return VERR_EM_INTERPRETER; 749 749 } … … 767 767 } 768 768 769 LogFlow(("emInterpretOrXorAnd %s % VGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pCpu), pParam1, valpar1, valpar2, param2.size, param1.size));769 LogFlow(("emInterpretOrXorAnd %s %RGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pCpu), pParam1, valpar1, valpar2, param2.size, param1.size)); 770 770 771 771 /* Data read, emulate instruction. */ … … 850 850 851 851 /* Try emulate it with a one-shot #PF handler in place. */ 852 Log2(("%s % VGv imm%d=%RX64\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));852 Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2)); 853 853 854 854 RTGCUINTREG32 eflags = 0; … … 862 862 if (RT_FAILURE(rc)) 863 863 { 864 Log(("%s % VGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));864 Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2)); 865 865 return VERR_EM_INTERPRETER; 866 866 } … … 920 920 if (RT_FAILURE(rc)) 921 921 { 922 AssertMsgFailed(("emRamRead % VGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));922 AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc)); 923 923 return VERR_EM_INTERPRETER; 924 924 } … … 1023 1023 } 1024 1024 1025 Log2(("emInterpret%s: pvFault=% VGv pParam1=%VGv val2=%x\n", emGetMnemonic(pCpu), pvFault, pParam1, valpar2));1025 Log2(("emInterpret%s: pvFault=%RGv pParam1=%RGv val2=%x\n", emGetMnemonic(pCpu), pvFault, pParam1, valpar2)); 1026 1026 pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8); 1027 1027 EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, VERR_EM_INTERPRETER); … … 1029 1029 if (RT_FAILURE(rc)) 1030 1030 { 1031 AssertMsgFailed(("emRamRead % VGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));1031 AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc)); 1032 1032 return VERR_EM_INTERPRETER; 1033 1033 } … … 1102 1102 #endif 1103 1103 1104 Log2(("emInterpretLockBitTest %s: pvFault=% VGv GCPtrPar1=%VGv imm=%RX64\n", emGetMnemonic(pCpu), pvFault, GCPtrPar1, ValPar2));1104 Log2(("emInterpretLockBitTest %s: pvFault=%RGv GCPtrPar1=%RGv imm=%RX64\n", emGetMnemonic(pCpu), pvFault, GCPtrPar1, ValPar2)); 1105 1105 1106 1106 #ifdef IN_GC … … 1120 1120 if (RT_FAILURE(rc)) 1121 1121 { 1122 Log(("emInterpretLockBitTest %s: % VGv imm%d=%RX64 -> emulation failed due to page fault!\n",1122 Log(("emInterpretLockBitTest %s: %RGv imm%d=%RX64 -> emulation failed due to page fault!\n", 1123 1123 emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2)); 1124 1124 return VERR_EM_INTERPRETER; 1125 1125 } 1126 1126 1127 Log2(("emInterpretLockBitTest %s: GCPtrPar1=% VGv imm=%VX64 CF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));1127 Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%VX64 CF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF))); 1128 1128 1129 1129 /* Update guest's eflags and finish. */ … … 1192 1192 #ifdef LOG_ENABLED 1193 1193 if (pCpu->mode == CPUMODE_64BIT) 1194 LogFlow(("EMInterpretInstruction at %RGv: OP_MOV % VGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64));1194 LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64)); 1195 1195 else 1196 LogFlow(("EMInterpretInstruction at %08RX64: OP_MOV % VGv <- %08X (%d) &val64=%RHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));1196 LogFlow(("EMInterpretInstruction at %08RX64: OP_MOV %RGv <- %08X (%d) &val64=%RHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64)); 1197 1197 #endif 1198 1198 … … 1255 1255 #ifdef LOG_ENABLED 1256 1256 if (pCpu->mode == CPUMODE_64BIT) 1257 LogFlow(("EMInterpretInstruction: OP_MOV % VGv -> %RX64 (%d)\n", pSrc, val64, param1.size));1257 LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size)); 1258 1258 else 1259 LogFlow(("EMInterpretInstruction: OP_MOV % VGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));1259 LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size)); 1260 1260 #endif 1261 1261 } … … 1324 1324 if (!(pCpu->prefix & PREFIX_REP)) 1325 1325 { 1326 LogFlow(("emInterpretStosWD dest=%04X:% VGv (%VGv) cbSize=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize));1326 LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize)); 1327 1327 1328 1328 rc = PGMPhysWriteGCPtr(pVM, GCDest, &pRegFrame->rax, cbSize); … … 1354 1354 return VINF_SUCCESS; 1355 1355 1356 LogFlow(("emInterpretStosWD dest=%04X:% VGv (%VGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));1356 LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF)); 1357 1357 1358 1358 /* Access verification first; we currently can't recover properly from traps inside this instruction */ … … 1457 1457 } 1458 1458 1459 LogFlow(("%s % VGv rax=%RX64 %RX64\n", emGetMnemonic(pCpu), GCPtrPar1, pRegFrame->rax, valpar));1459 LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pCpu), GCPtrPar1, pRegFrame->rax, valpar)); 1460 1460 1461 1461 if (pCpu->prefix & PREFIX_LOCK) … … 1464 1464 eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pCpu->param2.size); 1465 1465 1466 LogFlow(("%s % VGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));1466 LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF))); 1467 1467 1468 1468 /* Update guest's eflags and finish. */ … … 1511 1511 } 1512 1512 1513 LogFlow(("%s % VGv=%08x eax=%08x\n", emGetMnemonic(pCpu), pvParam1, pRegFrame->eax));1513 LogFlow(("%s %RGv=%08x eax=%08x\n", emGetMnemonic(pCpu), pvParam1, pRegFrame->eax)); 1514 1514 1515 1515 if (pCpu->prefix & PREFIX_LOCK) … … 1518 1518 eflags = EMEmulateCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx); 1519 1519 1520 LogFlow(("%s % VGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pCpu), pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));1520 LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pCpu), pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF))); 1521 1521 1522 1522 /* Update guest's eflags and finish; note that *only* ZF is affected. */ … … 1588 1588 if (RT_FAILURE(rc)) 1589 1589 { 1590 Log(("%s % VGv eax=%08x %08x -> emulation failed due to page fault!\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, valpar));1590 Log(("%s %RGv eax=%08x %08x -> emulation failed due to page fault!\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, valpar)); 1591 1591 return VERR_EM_INTERPRETER; 1592 1592 } … … 1650 1650 if (RT_FAILURE(rc)) 1651 1651 { 1652 Log(("%s % VGv=%08x eax=%08x -> emulation failed due to page fault!\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax));1652 Log(("%s %RGv=%08x eax=%08x -> emulation failed due to page fault!\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax)); 1653 1653 return VERR_EM_INTERPRETER; 1654 1654 } 1655 1655 1656 LogFlow(("%s % VGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));1656 LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF))); 1657 1657 1658 1658 /* Update guest's eflags and finish; note that *only* ZF is affected. */ … … 1721 1721 if (RT_FAILURE(rc)) 1722 1722 { 1723 Log(("XAdd % VGv reg=%08x -> emulation failed due to page fault!\n", pParam1, *pParamReg2));1723 Log(("XAdd %RGv reg=%08x -> emulation failed due to page fault!\n", pParam1, *pParamReg2)); 1724 1724 return VERR_EM_INTERPRETER; 1725 1725 } 1726 1726 1727 LogFlow(("XAdd % VGv reg=%08x ZF=%d\n", pParam1, *pParamReg2, !!(eflags & X86_EFL_ZF)));1727 LogFlow(("XAdd %RGv reg=%08x ZF=%d\n", pParam1, *pParamReg2, !!(eflags & X86_EFL_ZF))); 1728 1728 1729 1729 /* Update guest's eflags and finish. */ -
trunk/src/VBox/VMM/VMMAll/IOMAll.cpp
r13818 r13823 750 750 if (rc != VINF_SUCCESS) 751 751 { 752 Log(("iomInterpretCheckPortIOAccess: Port=%RTiop cb=%d GCPtrTss=% VGv %Rrc\n",752 Log(("iomInterpretCheckPortIOAccess: Port=%RTiop cb=%d GCPtrTss=%RGv %Rrc\n", 753 753 Port, cb, GCPtrTss, rc)); 754 754 return rc; … … 769 769 if (rc != VINF_SUCCESS) 770 770 { 771 Log(("iomInterpretCheckPortIOAccess: Port=%RTiop cb=%d GCPtrTss=% VGv offTss=%#x -> %Rrc\n",771 Log(("iomInterpretCheckPortIOAccess: Port=%RTiop cb=%d GCPtrTss=%RGv offTss=%#x -> %Rrc\n", 772 772 Port, cb, GCPtrTss, offTss, rc)); 773 773 return rc; -
trunk/src/VBox/VMM/VMMAll/IOMAllMMIO.cpp
r13820 r13823 1018 1018 { 1019 1019 STAM_PROFILE_START(&pVM->iom.s.StatRZMMIOHandler, a); 1020 Log(("IOMMMIOHandler: GCPhys=%RGp uErr=%#x pvFault=% VGv rip=%RGv\n",1020 Log(("IOMMMIOHandler: GCPhys=%RGp uErr=%#x pvFault=%RGv rip=%RGv\n", 1021 1021 GCPhysFault, (uint32_t)uErrorCode, pvFault, (RTGCPTR)pCtxCore->rip)); 1022 1022 -
trunk/src/VBox/VMM/VMMAll/PGMAll.cpp
r13821 r13823 360 360 VMMDECL(int) PGMTrap0eHandler(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault) 361 361 { 362 LogFlow(("PGMTrap0eHandler: uErr=%RGu pvFault=% VGv eip=%VGv\n", uErr, pvFault, (RTGCPTR)pRegFrame->rip));362 LogFlow(("PGMTrap0eHandler: uErr=%RGu pvFault=%RGv eip=%RGv\n", uErr, pvFault, (RTGCPTR)pRegFrame->rip)); 363 363 STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0e, a); 364 364 STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } ); … … 493 493 if (RT_FAILURE(rc)) 494 494 { 495 Log(("PGMIsValidAccess: access violation for % VGv rc=%d\n", Addr, rc));495 Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc)); 496 496 return VINF_EM_RAW_GUEST_TRAP; 497 497 } … … 509 509 || (fUser && !(fPage & X86_PTE_US)) ) 510 510 { 511 Log(("PGMIsValidAccess: access violation for % VGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));511 Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser)); 512 512 return VINF_EM_RAW_GUEST_TRAP; 513 513 } … … 541 541 if (RT_FAILURE(rc)) 542 542 { 543 Log(("PGMVerifyAccess: access violation for % VGv rc=%d\n", Addr, rc));543 Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc)); 544 544 return VINF_EM_RAW_GUEST_TRAP; 545 545 } … … 557 557 || (fUser && !(fPageGst & X86_PTE_US)) ) 558 558 { 559 Log(("PGMVerifyAccess: access violation for % VGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));559 Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser)); 560 560 return VINF_EM_RAW_GUEST_TRAP; 561 561 } … … 581 581 } 582 582 else 583 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage % VGv failed with %Rrc\n", Addr, rc));583 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc)); 584 584 } 585 585 … … 595 595 || (fUser && !(fPageShw & X86_PTE_US)) ) 596 596 { 597 AssertMsgFailed(("Unexpected access violation for % VGv! rc=%Rrc write=%d user=%d\n",597 AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n", 598 598 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US))); 599 599 return VINF_EM_RAW_GUEST_TRAP; … … 643 643 { 644 644 int rc; 645 Log3(("PGMInvalidatePage: GCPtrPage=% VGv\n", GCPtrPage));645 Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage)); 646 646 647 647 #ifndef IN_RING3 … … 727 727 rc = VINF_EM_RAW_EMULATE_INSTR; 728 728 if (rc != VINF_SUCCESS) 729 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=% VGv)\n", rc, pvFault));729 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", rc, pvFault)); 730 730 return rc; 731 731 } … … 1201 1201 Assert(cb); 1202 1202 1203 LogFlow(("PGMGstModifyPage % VGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));1203 LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask)); 1204 1204 1205 1205 /* … … 2010 2010 if (rc != VERR_PAGE_TABLE_NOT_PRESENT) 2011 2011 { 2012 AssertMsgFailed(("Conflict at % VGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));2012 AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc))); 2013 2013 cErrors++; 2014 2014 break; -
trunk/src/VBox/VMM/VMMAll/PGMAllBth.h
r13820 r13823 281 281 { 282 282 STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eConflicts); 283 Log(("Trap0e: Detected Conflict % VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));283 Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast)); 284 284 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */ 285 285 STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a); … … 471 471 || !(uErr & X86_TRAP_PF_P) 472 472 || (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))), 473 ("Unexpected trap for virtual handler: % VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));473 ("Unexpected trap for virtual handler: %RGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType)); 474 474 475 475 if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key < pCur->cb … … 637 637 uint64_t fPageGst; 638 638 PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys); 639 Log(("Page out of sync: % VGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n",639 Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n", 640 640 pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip))); 641 641 # endif /* LOG_ENABLED */ … … 712 712 */ 713 713 /** @todo not correct for pages that contain both code and data!! */ 714 Log2(("CSAMMarkPage % VGv; scanned=%d\n", pvFault, true));714 Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true)); 715 715 CSAMMarkPage(pVM, (RTRCPTR)pvFault, true); 716 716 } … … 755 755 rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys); 756 756 Assert(RT_SUCCESS(rc) && fPageGst & X86_PTE_RW); 757 LogFlow(("Obsolete physical monitor page out of sync % VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));757 LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst)); 758 758 759 759 uint64_t fPageShw; … … 808 808 */ 809 809 AssertMsg((fPageShw & ~(X86_PTE_A | X86_PTE_D | X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A | X86_PTE_D | X86_PTE_AVL_MASK)), 810 ("Page flags mismatch! pvFault=% VGv GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));810 ("Page flags mismatch! pvFault=%RGv GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst)); 811 811 } 812 812 else … … 886 886 int rc; 887 887 888 LogFlow(("InvalidatePage % VGv\n", GCPtrPage));888 LogFlow(("InvalidatePage %RGv\n", GCPtrPage)); 889 889 /* 890 890 * Get the shadow PD entry and skip out if this PD isn't present. … … 1019 1019 || pShwPdpt->GCPhys != GCPhysPdpt) 1020 1020 { 1021 LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at % VGv GCPhys=%VGp vs %VGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",1021 LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %RGv GCPhys=%VGp vs %VGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n", 1022 1022 GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u)); 1023 1023 pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e); … … 1033 1033 * Mark not present so we can resync the PML4E when it's used. 1034 1034 */ 1035 LogFlow(("InvalidatePage: Out-of-sync PML4E at % VGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",1035 LogFlow(("InvalidatePage: Out-of-sync PML4E at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n", 1036 1036 GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u)); 1037 1037 pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e); … … 1045 1045 * Mark not present so we can set the accessed bit. 1046 1046 */ 1047 LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at % VGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",1047 LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n", 1048 1048 GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u)); 1049 1049 pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e); … … 1059 1059 || pShwPde->GCPhys != GCPhysPd) 1060 1060 { 1061 LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at % VGv GCPhys=%VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",1061 LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %RGv GCPhys=%VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n", 1062 1062 GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u)); 1063 1063 pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte); … … 1073 1073 * Mark not present so we can resync the PDPTE when it's used. 1074 1074 */ 1075 LogFlow(("InvalidatePage: Out-of-sync PDPE at % VGv PdpeSrc=%RX64 PdpeDst=%RX64\n",1075 LogFlow(("InvalidatePage: Out-of-sync PDPE at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n", 1076 1076 GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u)); 1077 1077 pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte); … … 1085 1085 * Mark not present so we can set the accessed bit. 1086 1086 */ 1087 LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at % VGv PdpeSrc=%RX64 PdpeDst=%RX64\n",1087 LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n", 1088 1088 GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u)); 1089 1089 pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte); … … 1242 1242 || (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))) 1243 1243 { 1244 LogFlow(("Skipping flush for big page containing % VGv (PD=%X .u=%VX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));1244 LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%VX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u)); 1245 1245 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip)); 1246 1246 return VINF_SUCCESS; … … 1561 1561 PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr) 1562 1562 { 1563 LogFlow(("SyncPage: GCPtrPage=% VGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));1563 LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr)); 1564 1564 1565 1565 #if ( PGM_GST_TYPE == PGM_TYPE_32BIT \ … … 1708 1708 #endif /* else: CSAM not active */ 1709 1709 PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst); 1710 Log2(("SyncPage: 4K+ % VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",1710 Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n", 1711 1711 GCPtrCurPage, PteSrc.n.u1Present, 1712 1712 PteSrc.n.u1Write & PdeSrc.n.u1Write, … … 1725 1725 const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK; 1726 1726 PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst); 1727 Log2(("SyncPage: 4K % VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",1727 Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n", 1728 1728 GCPtrPage, PteSrc.n.u1Present, 1729 1729 PteSrc.n.u1Write & PdeSrc.n.u1Write, … … 1803 1803 pPDDst->a[iPDDst] = PdeDst; 1804 1804 # endif 1805 Log2(("SyncPage: BIG % VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",1805 Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n", 1806 1806 GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys, 1807 1807 PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : "")); … … 1919 1919 PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst); 1920 1920 1921 Log2(("SyncPage: 4K+ % VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",1921 Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n", 1922 1922 GCPtrCurPage, PteSrc.n.u1Present, 1923 1923 PteSrc.n.u1Write & PdeSrc.n.u1Write, … … 1928 1928 } 1929 1929 else 1930 Log4(("% VGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) | (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));1930 Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) | (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u)); 1931 1931 } 1932 1932 } … … 1947 1947 PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst); 1948 1948 1949 Log2(("SyncPage: 4K % VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",1949 Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n", 1950 1950 GCPtrPage, PteSrc.n.u1Present, 1951 1951 PteSrc.n.u1Write & PdeSrc.n.u1Write, … … 1993 1993 1994 1994 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a); 1995 LogFlow(("CheckPageFault: GCPtrPage=% VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));1995 LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u)); 1996 1996 1997 1997 # if PGM_GST_TYPE == PGM_TYPE_PAE \ … … 2118 2118 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF)); 2119 2119 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a); 2120 LogFlow(("CheckPageFault: real page fault at % VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));2120 LogFlow(("CheckPageFault: real page fault at %RGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u)); 2121 2121 2122 2122 /* Check the present bit as the shadow tables can cause different error codes by being out of sync. … … 2129 2129 return VINF_EM_RAW_GUEST_TRAP; 2130 2130 } 2131 LogFlow(("CheckPageFault: page fault at % VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));2131 LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u)); 2132 2132 2133 2133 /* … … 2164 2164 if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage)) 2165 2165 { 2166 LogRel(("CheckPageFault: write to hypervisor region % VGv\n", GCPtrPage));2166 LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage)); 2167 2167 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a); 2168 2168 return VINF_SUCCESS; … … 2180 2180 && (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY)) 2181 2181 { 2182 LogFlow(("DIRTY page trap addr=% VGv\n", GCPtrPage));2182 LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage)); 2183 2183 # ifdef VBOX_STRICT 2184 2184 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK); 2185 2185 if (pPage) 2186 2186 AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage), 2187 ("Unexpected dirty bit tracking on monitored page % VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));2187 ("Unexpected dirty bit tracking on monitored page %RGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK)); 2188 2188 # endif 2189 2189 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap)); … … 2219 2219 if ( pPteDst->n.u1Present 2220 2220 && pPteDst->n.u1Write) 2221 LogFlow(("Writable present page % VGv not marked for dirty bit tracking!!!\n", GCPtrPage));2221 LogFlow(("Writable present page %RGv not marked for dirty bit tracking!!!\n", GCPtrPage)); 2222 2222 } 2223 2223 # endif /* VBOX_STRICT */ … … 2237 2237 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF)); 2238 2238 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a); 2239 Log(("CheckPageFault: real page fault at % VGv (%d)\n", GCPtrPage, uPageFaultLevel));2239 Log(("CheckPageFault: real page fault at %RGv (%d)\n", GCPtrPage, uPageFaultLevel)); 2240 2240 2241 2241 if ( … … 2292 2292 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a); 2293 2293 STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPtPD[iPDSrc]); 2294 LogFlow(("SyncPT: GCPtrPage=% VGv\n", GCPtrPage));2294 LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage)); 2295 2295 2296 2296 #if ( PGM_GST_TYPE == PGM_TYPE_32BIT \ … … 2305 2305 * Validate input a little bit. 2306 2306 */ 2307 AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=% VGv\n", iPDSrc, GCPtrPage));2307 AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage)); 2308 2308 # if PGM_SHW_TYPE == PGM_TYPE_32BIT 2309 2309 const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; … … 2343 2343 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s)); 2344 2344 # ifndef IN_RING3 2345 Log(("SyncPT: Conflict at % VGv\n", GCPtrPage));2345 Log(("SyncPT: Conflict at %RGv\n", GCPtrPage)); 2346 2346 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a); 2347 2347 return VERR_ADDRESS_CONFLICT; … … 2458 2458 * Sync all or just a few entries depending on PGM_SYNC_N_PAGES. 2459 2459 */ 2460 Log2(("SyncPT: 4K % VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",2460 Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n", 2461 2461 GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u)); 2462 2462 PGSTPT pPTSrc; … … 2524 2524 # endif 2525 2525 PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst); 2526 Log2(("SyncPT: 4K+ % VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",2526 Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n", 2527 2527 (RTGCPTR)((iPDSrc << GST_PD_SHIFT) | (iPTSrc << PAGE_SHIFT)), 2528 2528 PteSrc.n.u1Present, … … 2583 2583 /* Loop thru the entries in the shadow PT. */ 2584 2584 const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr); 2585 Log2(("SyncPT: BIG % VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",2585 Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%VGp %s\n", 2586 2586 GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr, 2587 2587 GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : "")); … … 2645 2645 /* commit it */ 2646 2646 pPTDst->a[iPTDst] = PteDst; 2647 Log4(("SyncPT: BIG % VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",2647 Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n", 2648 2648 (RTGCPTR)(GCPtr | (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u, 2649 2649 PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "")); … … 2905 2905 PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr) 2906 2906 { 2907 LogFlow(("VerifyAccessSyncPage: GCPtrPage=% VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));2907 LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr)); 2908 2908 2909 2909 Assert(!HWACCMIsNestedPagingActive(pVM)); … … 2918 2918 */ 2919 2919 /** @todo not correct for pages that contain both code and data!! */ 2920 Log(("CSAMMarkPage % VGv; scanned=%d\n", GCPtrPage, true));2920 Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true)); 2921 2921 CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true); 2922 2922 } … … 2936 2936 if (pPDSrc) 2937 2937 { 2938 Log(("PGMVerifyAccess: access violation for % VGv due to non-present PDPTR\n", GCPtrPage));2938 Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage)); 2939 2939 return VINF_EM_RAW_GUEST_TRAP; 2940 2940 } … … 2946 2946 if (!pPDSrc) 2947 2947 { 2948 Log(("PGMVerifyAccess: access violation for % VGv due to non-present PDPTR\n", GCPtrPage));2948 Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage)); 2949 2949 return VINF_EM_RAW_GUEST_TRAP; 2950 2950 } … … 3029 3029 else 3030 3030 { 3031 Log(("PGMVerifyAccess: access violation for % VGv rc=%d\n", GCPtrPage, rc));3031 Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", GCPtrPage, rc)); 3032 3032 return VINF_EM_RAW_GUEST_TRAP; 3033 3033 } … … 3869 3869 if (!pPoolPage) 3870 3870 { 3871 AssertMsgFailed(("Invalid page table address %VHp at % VGv! PdeDst=%#RX64\n",3871 AssertMsgFailed(("Invalid page table address %VHp at %RGv! PdeDst=%#RX64\n", 3872 3872 HCPhysShw, GCPtr, (uint64_t)PdeDst.u)); 3873 3873 cErrors++; … … 3878 3878 if (PdeDst.u & (X86_PDE4M_PWT | X86_PDE4M_PCD)) 3879 3879 { 3880 AssertMsgFailed(("PDE flags PWT and/or PCD is set at % VGv! These flags are not virtualized! PdeDst=%#RX64\n",3880 AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n", 3881 3881 GCPtr, (uint64_t)PdeDst.u)); 3882 3882 cErrors++; … … 3885 3885 if (PdeDst.u & (X86_PDE4M_G | X86_PDE4M_D)) 3886 3886 { 3887 AssertMsgFailed(("4K PDE reserved flags at % VGv! PdeDst=%#RX64\n",3887 AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n", 3888 3888 GCPtr, (uint64_t)PdeDst.u)); 3889 3889 cErrors++; … … 3893 3893 if (!PdeSrc.n.u1Present) 3894 3894 { 3895 AssertMsgFailed(("Guest PDE at % VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",3895 AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n", 3896 3896 GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u)); 3897 3897 cErrors++; … … 3912 3912 if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK) 3913 3913 { 3914 AssertMsgFailed(("Guest PDE at % VGv is using PSE36 or similar! PdeSrc=%#RX64\n",3914 AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n", 3915 3915 GCPtr, (uint64_t)PdeSrc.u)); 3916 3916 cErrors++; … … 3927 3927 != (!PdeSrc.b.u1Size || !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG)) 3928 3928 { 3929 AssertMsgFailed(("Invalid shadow page table kind %d at % VGv! PdeSrc=%#RX64\n",3929 AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n", 3930 3930 pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u)); 3931 3931 cErrors++; … … 3935 3935 if (!pPhysPage) 3936 3936 { 3937 AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at % VGv! PdeSrc=%#RX64\n",3937 AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %RGv! PdeSrc=%#RX64\n", 3938 3938 GCPhysGst, GCPtr, (uint64_t)PdeSrc.u)); 3939 3939 cErrors++; … … 3943 3943 if (GCPhysGst != pPoolPage->GCPhys) 3944 3944 { 3945 AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at % VGv\n",3945 AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %RGv\n", 3946 3946 GCPhysGst, pPoolPage->GCPhys, GCPtr)); 3947 3947 cErrors++; … … 3959 3959 if (RT_FAILURE(rc)) 3960 3960 { 3961 AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at % VGv! PdeSrc=%#RX64\n",3961 AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %RGv! PdeSrc=%#RX64\n", 3962 3962 GCPhysGst, GCPtr, (uint64_t)PdeSrc.u)); 3963 3963 cErrors++; … … 3969 3969 /// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here! 3970 3970 // (This problem will go away when/if we shadow multiple CR3s.) 3971 AssertMsgFailed(("4K PDE flags mismatch at % VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",3971 AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n", 3972 3972 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u)); 3973 3973 cErrors++; … … 3976 3976 if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY) 3977 3977 { 3978 AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=% VGv PdeDst=%#RX64\n",3978 AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n", 3979 3979 GCPtr, (uint64_t)PdeDst.u)); 3980 3980 cErrors++; … … 4007 4007 PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK)); 4008 4008 # endif 4009 AssertMsgFailed(("Out of sync (!P) PTE at % VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",4009 AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n", 4010 4010 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0], 4011 4011 (PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc))); … … 4029 4029 if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) 4030 4030 { 4031 AssertMsgFailed(("Cannot find guest physical address %VGp at % VGv! PteSrc=%#RX64 PteDst=%#RX64\n",4031 AssertMsgFailed(("Cannot find guest physical address %VGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n", 4032 4032 GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u)); 4033 4033 cErrors++; … … 4037 4037 else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK)) 4038 4038 { 4039 AssertMsgFailed(("Out of sync (phys) at % VGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",4039 AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n", 4040 4040 GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u)); 4041 4041 cErrors++; … … 4050 4050 if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) 4051 4051 { 4052 AssertMsgFailed(("Cannot find guest physical address %VGp at % VGv! PteSrc=%#RX64 PteDst=%#RX64\n",4052 AssertMsgFailed(("Cannot find guest physical address %VGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n", 4053 4053 GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u)); 4054 4054 cErrors++; … … 4058 4058 if (PteDst.n.u1Write) 4059 4059 { 4060 AssertMsgFailed(("Invalid guest page at % VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",4060 AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n", 4061 4061 GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u)); 4062 4062 cErrors++; … … 4066 4066 else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK)) 4067 4067 { 4068 AssertMsgFailed(("Out of sync (phys) at % VGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",4068 AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n", 4069 4069 GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u)); 4070 4070 cErrors++; … … 4079 4079 if (PteDst.n.u1Write) 4080 4080 { 4081 AssertMsgFailed(("WRITE access flagged at % VGv but the page is writable! HCPhys=%RHp PteSrc=%#RX64 PteDst=%#RX64\n",4081 AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! HCPhys=%RHp PteSrc=%#RX64 PteDst=%#RX64\n", 4082 4082 GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u)); 4083 4083 cErrors++; … … 4090 4090 if (PteDst.n.u1Present) 4091 4091 { 4092 AssertMsgFailed(("ALL access flagged at % VGv but the page is present! HCPhys=%RHp PteSrc=%#RX64 PteDst=%#RX64\n",4092 AssertMsgFailed(("ALL access flagged at %RGv but the page is present! HCPhys=%RHp PteSrc=%#RX64 PteDst=%#RX64\n", 4093 4093 GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u)); 4094 4094 cErrors++; … … 4104 4104 if (PteDst.n.u1Write) 4105 4105 { 4106 AssertMsgFailed(("!DIRTY page at % VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",4106 AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n", 4107 4107 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u)); 4108 4108 cErrors++; … … 4111 4111 if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)) 4112 4112 { 4113 AssertMsgFailed(("!DIRTY page at % VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",4113 AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n", 4114 4114 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u)); 4115 4115 cErrors++; … … 4118 4118 if (PteDst.n.u1Dirty) 4119 4119 { 4120 AssertMsgFailed(("!DIRTY page at % VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",4120 AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n", 4121 4121 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u)); 4122 4122 cErrors++; … … 4125 4125 if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed) 4126 4126 { 4127 AssertMsgFailed(("!DIRTY page at % VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",4127 AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n", 4128 4128 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u)); 4129 4129 cErrors++; … … 4139 4139 if (PteSrc.n.u1Accessed || PteDst.n.u1Present) 4140 4140 { 4141 AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at % VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",4141 AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n", 4142 4142 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u)); 4143 4143 cErrors++; … … 4146 4146 if (!PteDst.n.u1Accessed) 4147 4147 { 4148 AssertMsgFailed(("!ACCESSED page at % VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",4148 AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n", 4149 4149 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u)); 4150 4150 cErrors++; … … 4161 4161 ) 4162 4162 { 4163 AssertMsgFailed(("Flags mismatch at % VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",4163 AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n", 4164 4164 GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags, 4165 4165 fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u)); … … 4179 4179 if (PdeDst.n.u1Write) 4180 4180 { 4181 AssertMsgFailed(("!DIRTY page at % VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",4181 AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n", 4182 4182 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u)); 4183 4183 cErrors++; … … 4186 4186 if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)) 4187 4187 { 4188 AssertMsgFailed(("!DIRTY page at % VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",4188 AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n", 4189 4189 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u)); 4190 4190 cErrors++; … … 4194 4194 if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed) 4195 4195 { 4196 AssertMsgFailed(("!DIRTY page at % VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",4196 AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n", 4197 4197 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u)); 4198 4198 cErrors++; … … 4208 4208 if (PdeSrc.b.u1Accessed || PdeDst.n.u1Present) 4209 4209 { 4210 AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at % VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",4210 AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n", 4211 4211 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u)); 4212 4212 cErrors++; … … 4215 4215 if (!PdeDst.n.u1Accessed) 4216 4216 { 4217 AssertMsgFailed(("!ACCESSED page at % VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",4217 AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n", 4218 4218 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u)); 4219 4219 cErrors++; … … 4224 4224 if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags)) 4225 4225 { 4226 AssertMsgFailed(("Flags mismatch (B) at % VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",4226 AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n", 4227 4227 GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags, 4228 4228 fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u)); … … 4239 4239 if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY) 4240 4240 { 4241 AssertMsgFailed(("The PTE at % VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",4241 AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n", 4242 4242 GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u)); 4243 4243 cErrors++; … … 4259 4259 if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) 4260 4260 { 4261 AssertMsgFailed(("Cannot find guest physical address %VGp at % VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",4261 AssertMsgFailed(("Cannot find guest physical address %VGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n", 4262 4262 GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u)); 4263 4263 cErrors++; … … 4266 4266 else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK)) 4267 4267 { 4268 AssertMsgFailed(("Out of sync (phys) at % VGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",4268 AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n", 4269 4269 GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u)); 4270 4270 cErrors++; … … 4278 4278 if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) 4279 4279 { 4280 AssertMsgFailed(("Cannot find guest physical address %VGp at % VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",4280 AssertMsgFailed(("Cannot find guest physical address %VGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n", 4281 4281 GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u)); 4282 4282 cErrors++; … … 4286 4286 if (PteDst.n.u1Write) 4287 4287 { 4288 AssertMsgFailed(("Invalid guest page at % VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",4288 AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n", 4289 4289 GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u)); 4290 4290 cErrors++; … … 4294 4294 else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK)) 4295 4295 { 4296 AssertMsgFailed(("Out of sync (phys) at % VGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",4296 AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n", 4297 4297 GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u)); 4298 4298 cErrors++; … … 4309 4309 if (PteDst.n.u1Write) 4310 4310 { 4311 AssertMsgFailed(("WRITE access flagged at % VGv but the page is writable! HCPhys=%RHp PdeSrc=%#RX64 PteDst=%#RX64\n",4311 AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! HCPhys=%RHp PdeSrc=%#RX64 PteDst=%#RX64\n", 4312 4312 GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u)); 4313 4313 cErrors++; … … 4321 4321 if (PteDst.n.u1Present) 4322 4322 { 4323 AssertMsgFailed(("ALL access flagged at % VGv but the page is present! HCPhys=%RHp PdeSrc=%#RX64 PteDst=%#RX64\n",4323 AssertMsgFailed(("ALL access flagged at %RGv but the page is present! HCPhys=%RHp PdeSrc=%#RX64 PteDst=%#RX64\n", 4324 4324 GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u)); 4325 4325 cErrors++; … … 4334 4334 ) 4335 4335 { 4336 AssertMsgFailed(("Flags mismatch (BT) at % VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",4336 AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n", 4337 4337 GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags, 4338 4338 fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u)); -
trunk/src/VBox/VMM/VMMAll/PGMAllGst.h
r13820 r13823 455 455 pVM->pgm.s.pGstPaePDPTHC = (R3R0PTRTYPE(PX86PDPT)) HCPtrGuestCR3; 456 456 pVM->pgm.s.pGstPaePDPTGC = (RCPTRTYPE(PX86PDPT)) ((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + offset); 457 Log(("Cached mapping % VGv\n", pVM->pgm.s.pGstPaePDPTGC));457 Log(("Cached mapping %RGv\n", pVM->pgm.s.pGstPaePDPTGC)); 458 458 459 459 /* -
trunk/src/VBox/VMM/VMMAll/PGMAllHandler.cpp
r13819 r13823 1360 1360 if (pVirt->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS) 1361 1361 { 1362 AssertMsgFailed(("virt handler phys out of sync. %VGp GCPhysNew=~0 iPage=%#x % VGv %s\n",1362 AssertMsgFailed(("virt handler phys out of sync. %VGp GCPhysNew=~0 iPage=%#x %RGv %s\n", 1363 1363 pVirt->aPhysToVirt[iPage].Core.Key, iPage, GCPtr, R3STRING(pVirt->pszDesc))); 1364 1364 pState->cErrors++; … … 1370 1370 if ((pVirt->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) != GCPhysGst) 1371 1371 { 1372 AssertMsgFailed(("virt handler phys out of sync. %VGp GCPhysGst=%VGp iPage=%#x % VGv %s\n",1372 AssertMsgFailed(("virt handler phys out of sync. %VGp GCPhysGst=%VGp iPage=%#x %RGv %s\n", 1373 1373 pVirt->aPhysToVirt[iPage].Core.Key, GCPhysGst, iPage, GCPtr, R3STRING(pVirt->pszDesc))); 1374 1374 pState->cErrors++; … … 1379 1379 if (!pPage) 1380 1380 { 1381 AssertMsgFailed(("virt handler getting ram flags. GCPhysGst=%VGp iPage=%#x % VGv %s\n",1381 AssertMsgFailed(("virt handler getting ram flags. GCPhysGst=%VGp iPage=%#x %RGv %s\n", 1382 1382 GCPhysGst, iPage, GCPtr, R3STRING(pVirt->pszDesc))); 1383 1383 pState->cErrors++; … … 1387 1387 if (PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < uState) 1388 1388 { 1389 AssertMsgFailed(("virt handler state mismatch. HCPhys=%RHp GCPhysGst=%VGp iPage=%#x % VGv state=%d expected>=%d %s\n",1389 AssertMsgFailed(("virt handler state mismatch. HCPhys=%RHp GCPhysGst=%VGp iPage=%#x %RGv state=%d expected>=%d %s\n", 1390 1390 pPage->HCPhys, GCPhysGst, iPage, GCPtr, PGM_PAGE_GET_HNDL_VIRT_STATE(pPage), uState, R3STRING(pVirt->pszDesc))); 1391 1391 pState->cErrors++; -
trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp
r13820 r13823 2114 2114 return VINF_SUCCESS; 2115 2115 2116 LogFlow(("PGMPhysReadGCPtr: % VGv %zu\n", GCPtrSrc, cb));2116 LogFlow(("PGMPhysReadGCPtr: %RGv %zu\n", GCPtrSrc, cb)); 2117 2117 2118 2118 /* … … 2186 2186 return VINF_SUCCESS; 2187 2187 2188 LogFlow(("PGMPhysWriteGCPtr: % VGv %zu\n", GCPtrDst, cb));2188 LogFlow(("PGMPhysWriteGCPtr: %RGv %zu\n", GCPtrDst, cb)); 2189 2189 2190 2190 /* … … 2328 2328 { 2329 2329 /** @todo we should check reserved bits ... */ 2330 AssertMsgFailed(("cb=%d cb1=%d cb2=%d GCPtrSrc=% VGv\n", cb, cb1, cb2, GCPtrSrc));2330 AssertMsgFailed(("cb=%d cb1=%d cb2=%d GCPtrSrc=%RGv\n", cb, cb1, cb2, GCPtrSrc)); 2331 2331 void *pvSrc1; 2332 2332 rc = PGM_GCPHYS_2_PTR(pVM, GCPhys1, &pvSrc1); … … 2390 2390 2391 2391 default: 2392 AssertMsgFailed(("rc=%Rrc GCPtrSrc=% VGv cb=%#x\n", rc, GCPtrSrc, cb));2392 AssertMsgFailed(("rc=%Rrc GCPtrSrc=%RGv cb=%#x\n", rc, GCPtrSrc, cb)); 2393 2393 return rc; 2394 2394 } 2395 Log(("PGMPhysInterpretedRead: GCPtrSrc=% VGv cb=%#x -> #PF(%#x)\n", GCPtrSrc, cb, uErr));2395 Log(("PGMPhysInterpretedRead: GCPtrSrc=%RGv cb=%#x -> #PF(%#x)\n", GCPtrSrc, cb, uErr)); 2396 2396 return TRPMRaiseXcptErrCR2(pVM, pCtxCore, X86_XCPT_PF, uErr, GCPtrSrc); 2397 2397 } -
trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp
r13820 r13823 292 292 const unsigned cbWrite = (pCpu) ? pgmPoolDisasWriteSize(pCpu) : 0; 293 293 294 LogFlow(("pgmPoolMonitorChainChanging: % VGv phys=%VGp kind=%d cbWrite=%d\n", pvAddress, GCPhysFault, pPage->enmKind, cbWrite));294 LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%VGp kind=%d cbWrite=%d\n", pvAddress, GCPhysFault, pPage->enmKind, cbWrite)); 295 295 296 296 for (;;) … … 752 752 { 753 753 /* Fault caused by stack writes while trying to inject an interrupt event. */ 754 Log(("pgmPoolMonitorIsReused: reused % VGv for interrupt stack (rsp=%VGv).\n", pvFault, pRegFrame->rsp));754 Log(("pgmPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp)); 755 755 return true; 756 756 } … … 997 997 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); 998 998 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser; 999 LogFlow(("pgmPoolAccessHandler: pvFault=% VGv pPage=%p:{.idx=%d} GCPhysFault=%VGp\n", pvFault, pPage, pPage->idx, GCPhysFault));999 LogFlow(("pgmPoolAccessHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%VGp\n", pvFault, pPage, pPage->idx, GCPhysFault)); 1000 1000 1001 1001 /* … … 1055 1055 /* REP prefix, don't bother. */ 1056 1056 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix)); 1057 Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=% VGv opcode=%d prefix=%#x\n",1057 Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n", 1058 1058 pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, Cpu.pCurInstr->opcode, Cpu.prefix)); 1059 1059 } -
trunk/src/VBox/VMM/VMMAll/PGMAllShw.h
r13816 r13823 226 226 227 227 PPGMMAPPING pMap = pgmGetMapping(pVM, (RTGCPTR)GCPtr); 228 AssertMsgReturn(pMap, ("GCPtr=% VGv\n", GCPtr), VERR_INTERNAL_ERROR);228 AssertMsgReturn(pMap, ("GCPtr=%RGv\n", GCPtr), VERR_INTERNAL_ERROR); 229 229 # if PGM_SHW_TYPE == PGM_TYPE_32BIT 230 230 pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(pPT); -
trunk/src/VBox/VMM/VMMAll/TRPMAll.cpp
r13822 r13823 208 208 VMMDECL(void) TRPMSetErrorCode(PVM pVM, RTGCUINT uErrorCode) 209 209 { 210 Log2(("TRPMSetErrorCode: uErrorCode=% VGv\n", uErrorCode)); /** @todo RTGCUINT mess! */210 Log2(("TRPMSetErrorCode: uErrorCode=%RGv\n", uErrorCode)); /** @todo RTGCUINT mess! */ 211 211 AssertMsg(pVM->trpm.s.uActiveVector != ~0U, ("No active trap!\n")); 212 212 pVM->trpm.s.uActiveErrorCode = uErrorCode; … … 240 240 VMMDECL(void) TRPMSetFaultAddress(PVM pVM, RTGCUINTPTR uCR2) 241 241 { 242 Log2(("TRPMSetFaultAddress: uCR2=% VGv\n", uCR2));242 Log2(("TRPMSetFaultAddress: uCR2=%RGv\n", uCR2)); 243 243 AssertMsg(pVM->trpm.s.uActiveVector != ~0U, ("No active trap!\n")); 244 244 AssertMsg(pVM->trpm.s.uActiveVector == 0xe, ("Not trap 0e!\n")); … … 386 386 # endif 387 387 if (RT_SUCCESS(rc)) 388 Log(("TRPMForwardTrap: caller=% VGv\n", pCallerGC));388 Log(("TRPMForwardTrap: caller=%RGv\n", pCallerGC)); 389 389 } 390 390 /* no break */ … … 455 455 { 456 456 /* The page might be out of sync. */ /** @todo might cross a page boundary) */ 457 Log(("Page % VGv out of sync -> prefetch and try again\n", pIDTEntry));457 Log(("Page %RGv out of sync -> prefetch and try again\n", pIDTEntry)); 458 458 rc = PGMPrefetchPage(pVM, pIDTEntry); /** @todo r=bird: rainy day: this isn't entirely safe because of access bit virtualiziation and CSAM. */ 459 459 if (rc != VINF_SUCCESS) … … 515 515 { 516 516 /* The page might be out of sync. */ /** @todo might cross a page boundary) */ 517 Log(("Page % VGv out of sync -> prefetch and try again\n", pGdtEntry));517 Log(("Page %RGv out of sync -> prefetch and try again\n", pGdtEntry)); 518 518 rc = PGMPrefetchPage(pVM, pGdtEntry); /** @todo r=bird: rainy day: this isn't entirely safe because of access bit virtualiziation and CSAM. */ 519 519 if (rc != VINF_SUCCESS) … … 606 606 if (eflags.Bits.u1VM) 607 607 { 608 Log(("TRAP%02X: (VM) Handler %04X:% VGv Stack %04X:%08X RPL=%d CR2=%08X\n", iGate, GuestIdte.Gen.u16SegSel, pHandler, ss_r0, esp_r0, (pRegFrame->ss & X86_SEL_RPL), pVM->trpm.s.uActiveCR2));608 Log(("TRAP%02X: (VM) Handler %04X:%RGv Stack %04X:%08X RPL=%d CR2=%08X\n", iGate, GuestIdte.Gen.u16SegSel, pHandler, ss_r0, esp_r0, (pRegFrame->ss & X86_SEL_RPL), pVM->trpm.s.uActiveCR2)); 609 609 pTrapStack[--idx] = pRegFrame->gs; 610 610 pTrapStack[--idx] = pRegFrame->fs; … … 616 616 } 617 617 else 618 Log(("TRAP%02X: Handler %04X:% VGv Stack %04X:%08X RPL=%d CR2=%08X\n", iGate, GuestIdte.Gen.u16SegSel, pHandler, ss_r0, esp_r0, (pRegFrame->ss & X86_SEL_RPL), pVM->trpm.s.uActiveCR2));618 Log(("TRAP%02X: Handler %04X:%RGv Stack %04X:%08X RPL=%d CR2=%08X\n", iGate, GuestIdte.Gen.u16SegSel, pHandler, ss_r0, esp_r0, (pRegFrame->ss & X86_SEL_RPL), pVM->trpm.s.uActiveCR2)); 619 619 620 620 if (!fConforming && dpl < cpl) … … 712 712 } 713 713 else 714 Log(("TRAP%02X: PGMVerifyAccess % VGv failed with %Rrc -> forward to REM\n", iGate, pTrapStackGC, rc));714 Log(("TRAP%02X: PGMVerifyAccess %RGv failed with %Rrc -> forward to REM\n", iGate, pTrapStackGC, rc)); 715 715 } 716 716 else … … 718 718 } 719 719 else 720 Log(("MMRamRead % VGv size %d failed with %Rrc\n", (RTGCUINTPTR)GCPtrIDT + sizeof(VBOXIDTE) * iGate, sizeof(GuestIdte), rc));720 Log(("MMRamRead %RGv size %d failed with %Rrc\n", (RTGCUINTPTR)GCPtrIDT + sizeof(VBOXIDTE) * iGate, sizeof(GuestIdte), rc)); 721 721 } 722 722 else
Note:
See TracChangeset
for help on using the changeset viewer.