Changeset 13837 in vbox for trunk/src/recompiler
- Timestamp:
- Nov 5, 2008 2:54:02 AM (16 years ago)
- svn:sync-xref-src-repo-rev:
- 38828
- Location:
- trunk/src/recompiler
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/recompiler/VBoxREMWrapper.cpp
r13835 r13837 1844 1844 RTUINTPTR Value; 1845 1845 rc = RTLdrGetSymbolEx(g_ModREM2, g_pvREM2, (RTUINTPTR)g_pvREM2, g_aExports[i].pszName, &Value); 1846 AssertMsgRC(rc, ("%s rc=% Vrc\n", g_aExports[i].pszName, rc));1846 AssertMsgRC(rc, ("%s rc=%Rrc\n", g_aExports[i].pszName, rc)); 1847 1847 if (RT_FAILURE(rc)) 1848 1848 break; … … 1859 1859 g_ModREM2 = NIL_RTLDRMOD; 1860 1860 } 1861 LogRel(("REM: failed loading '%s', rc=% Vrc\n", szPath, rc));1861 LogRel(("REM: failed loading '%s', rc=%Rrc\n", szPath, rc)); 1862 1862 return rc; 1863 1863 } -
trunk/src/recompiler/VBoxRecompiler.c
r13836 r13837 801 801 break; 802 802 } 803 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG rc=% Vrc iBP=%d GCPtrPC=%VGv\n", rc, iBP, GCPtrPC));803 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_DEBUG rc=%Rrc iBP=%d GCPtrPC=%VGv\n", rc, iBP, GCPtrPC)); 804 804 break; 805 805 } … … 942 942 */ 943 943 case EXCP_RC: 944 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_RC rc=% Vrc\n", pVM->rem.s.rc));944 Log2(("REMR3EmulateInstruction: cpu_exec -> EXCP_RC rc=%Rrc\n", pVM->rem.s.rc)); 945 945 rc = pVM->rem.s.rc; 946 946 pVM->rem.s.rc = VERR_INTERNAL_ERROR; … … 967 967 } 968 968 969 Log2(("REMR3EmulateInstruction: returns % Vrc (cs:eip=%04x:%VGv)\n",969 Log2(("REMR3EmulateInstruction: returns %Rrc (cs:eip=%04x:%VGv)\n", 970 970 rc, pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip)); 971 971 return rc; … … 1055 1055 break; 1056 1056 } 1057 Log2(("REMR3Run: cpu_exec -> EXCP_DEBUG rc=% Vrc iBP=%d GCPtrPC=%VGv\n", rc, iBP, GCPtrPC));1057 Log2(("REMR3Run: cpu_exec -> EXCP_DEBUG rc=%Rrc iBP=%d GCPtrPC=%VGv\n", rc, iBP, GCPtrPC)); 1058 1058 #endif 1059 1059 break; … … 1090 1090 */ 1091 1091 case EXCP_RC: 1092 Log2(("REMR3Run: cpu_exec -> EXCP_RC rc=% Vrc\n", pVM->rem.s.rc));1092 Log2(("REMR3Run: cpu_exec -> EXCP_RC rc=%Rrc\n", pVM->rem.s.rc)); 1093 1093 rc = pVM->rem.s.rc; 1094 1094 pVM->rem.s.rc = VERR_INTERNAL_ERROR; … … 1105 1105 } 1106 1106 1107 Log2(("REMR3Run: returns % Vrc (cs:eip=%04x:%VGv)\n", rc, pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip));1107 Log2(("REMR3Run: returns %Rrc (cs:eip=%04x:%VGv)\n", rc, pVM->rem.s.Env.segs[R_CS].selector, pVM->rem.s.Env.eip)); 1108 1108 return rc; 1109 1109 } … … 1509 1509 rc = PGMChangeMode(pVM, env->cr[0], env->cr[4], env->efer); 1510 1510 if (rc != VINF_SUCCESS) 1511 cpu_abort(env, "PGMChangeMode(, %RX64, %RX64, %RX64) -> % Vrc\n", env->cr[0], env->cr[4], env->efer, rc);1511 cpu_abort(env, "PGMChangeMode(, %RX64, %RX64, %RX64) -> %Rrc\n", env->cr[0], env->cr[4], env->efer, rc); 1512 1512 #else 1513 1513 rc = PGMChangeMode(pVM, env->cr[0], env->cr[4], 0); 1514 1514 if (rc != VINF_SUCCESS) 1515 cpu_abort(env, "PGMChangeMode(, %RX64, %RX64, %RX64) -> % Vrc\n", env->cr[0], env->cr[4], 0LL, rc);1515 cpu_abort(env, "PGMChangeMode(, %RX64, %RX64, %RX64) -> %Rrc\n", env->cr[0], env->cr[4], 0LL, rc); 1516 1516 #endif 1517 1517 } … … 3271 3271 uint32_t u32 = 0; 3272 3272 int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 1); 3273 AssertMsg(rc == VINF_SUCCESS, ("rc=% Vrc\n", rc)); NOREF(rc);3273 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc); 3274 3274 Log2(("remR3MMIOReadU8: GCPhys=%VGp -> %02x\n", GCPhys, u32)); 3275 3275 return u32; … … 3281 3281 uint32_t u32 = 0; 3282 3282 int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 2); 3283 AssertMsg(rc == VINF_SUCCESS, ("rc=% Vrc\n", rc)); NOREF(rc);3283 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc); 3284 3284 Log2(("remR3MMIOReadU16: GCPhys=%VGp -> %04x\n", GCPhys, u32)); 3285 3285 return u32; … … 3291 3291 uint32_t u32 = 0; 3292 3292 int rc = IOMMMIORead((PVM)pvVM, GCPhys, &u32, 4); 3293 AssertMsg(rc == VINF_SUCCESS, ("rc=% Vrc\n", rc)); NOREF(rc);3293 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc); 3294 3294 Log2(("remR3MMIOReadU32: GCPhys=%VGp -> %08x\n", GCPhys, u32)); 3295 3295 return u32; … … 3301 3301 Log2(("remR3MMIOWriteU8: GCPhys=%VGp u32=%#x\n", GCPhys, u32)); 3302 3302 int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 1); 3303 AssertMsg(rc == VINF_SUCCESS, ("rc=% Vrc\n", rc)); NOREF(rc);3303 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc); 3304 3304 } 3305 3305 … … 3309 3309 Log2(("remR3MMIOWriteU16: GCPhys=%VGp u32=%#x\n", GCPhys, u32)); 3310 3310 int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 2); 3311 AssertMsg(rc == VINF_SUCCESS, ("rc=% Vrc\n", rc)); NOREF(rc);3311 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc); 3312 3312 } 3313 3313 … … 3317 3317 Log2(("remR3MMIOWriteU32: GCPhys=%VGp u32=%#x\n", GCPhys, u32)); 3318 3318 int rc = IOMMMIOWrite((PVM)pvVM, GCPhys, u32, 4); 3319 AssertMsg(rc == VINF_SUCCESS, ("rc=% Vrc\n", rc)); NOREF(rc);3319 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc)); NOREF(rc); 3320 3320 } 3321 3321 … … 4013 4013 void remR3RaiseRC(PVM pVM, int rc) 4014 4014 { 4015 Log(("remR3RaiseRC: rc=% Vrc\n", rc));4015 Log(("remR3RaiseRC: rc=%Rrc\n", rc)); 4016 4016 Assert(pVM->rem.s.fInREM); 4017 4017 VM_ASSERT_EMT(pVM); … … 4061 4061 rc = PDMGetInterrupt(env->pVM, &u8Interrupt); 4062 4062 4063 LogFlow(("cpu_get_pic_interrupt: u8Interrupt=%d rc=% Vrc\n", u8Interrupt, rc));4063 LogFlow(("cpu_get_pic_interrupt: u8Interrupt=%d rc=%Rrc\n", u8Interrupt, rc)); 4064 4064 if (RT_SUCCESS(rc)) 4065 4065 { … … 4077 4077 { 4078 4078 int rc = PDMApicSetBase(env->pVM, val); 4079 LogFlow(("cpu_set_apic_base: val=%#llx rc=% Vrc\n", val, rc)); NOREF(rc);4079 LogFlow(("cpu_set_apic_base: val=%#llx rc=%Rrc\n", val, rc)); NOREF(rc); 4080 4080 } 4081 4081 … … 4089 4089 return u64; 4090 4090 } 4091 LogFlow(("cpu_get_apic_base: returns 0 (rc=% Vrc)\n", rc));4091 LogFlow(("cpu_get_apic_base: returns 0 (rc=%Rrc)\n", rc)); 4092 4092 return 0; 4093 4093 } … … 4096 4096 { 4097 4097 int rc = PDMApicSetTPR(env->pVM, val); 4098 LogFlow(("cpu_set_apic_tpr: val=%#x rc=% Vrc\n", val, rc)); NOREF(rc);4098 LogFlow(("cpu_set_apic_tpr: val=%#x rc=%Rrc\n", val, rc)); NOREF(rc); 4099 4099 } 4100 4100 … … 4108 4108 return u8; 4109 4109 } 4110 LogFlow(("cpu_get_apic_tpr: returns 0 (rc=% Vrc)\n", rc));4110 LogFlow(("cpu_get_apic_tpr: returns 0 (rc=%Rrc)\n", rc)); 4111 4111 return 0; 4112 4112 } … … 4123 4123 } 4124 4124 /** @todo: exception ? */ 4125 LogFlow(("cpu_apic_rdms returns 0 (rc=% Vrc)\n", rc));4125 LogFlow(("cpu_apic_rdms returns 0 (rc=%Rrc)\n", rc)); 4126 4126 return value; 4127 4127 } … … 4131 4131 int rc = PDMApicWriteMSR(env->pVM, 0 /* cpu */, reg, value); 4132 4132 /** @todo: exception if error ? */ 4133 LogFlow(("cpu_apic_wrmsr: rc=% Vrc\n", rc)); NOREF(rc);4133 LogFlow(("cpu_apic_wrmsr: rc=%Rrc\n", rc)); NOREF(rc); 4134 4134 } 4135 4135 /* -+- I/O Ports -+- */ … … 4148 4148 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST) 4149 4149 { 4150 Log(("cpu_outb: addr=%#06x val=%#x -> % Vrc\n", addr, val, rc));4150 Log(("cpu_outb: addr=%#06x val=%#x -> %Rrc\n", addr, val, rc)); 4151 4151 remR3RaiseRC(env->pVM, rc); 4152 4152 return; … … 4163 4163 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST) 4164 4164 { 4165 Log(("cpu_outw: addr=%#06x val=%#x -> % Vrc\n", addr, val, rc));4165 Log(("cpu_outw: addr=%#06x val=%#x -> %Rrc\n", addr, val, rc)); 4166 4166 remR3RaiseRC(env->pVM, rc); 4167 4167 return; … … 4178 4178 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST) 4179 4179 { 4180 Log(("cpu_outl: addr=%#06x val=%#x -> % Vrc\n", addr, val, rc));4180 Log(("cpu_outl: addr=%#06x val=%#x -> %Rrc\n", addr, val, rc)); 4181 4181 remR3RaiseRC(env->pVM, rc); 4182 4182 return; … … 4197 4197 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST) 4198 4198 { 4199 Log(("cpu_inb: addr=%#06x -> %#x rc=% Vrc\n", addr, u32, rc));4199 Log(("cpu_inb: addr=%#06x -> %#x rc=%Rrc\n", addr, u32, rc)); 4200 4200 remR3RaiseRC(env->pVM, rc); 4201 4201 return (int)u32; … … 4216 4216 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST) 4217 4217 { 4218 Log(("cpu_inw: addr=%#06x -> %#x rc=% Vrc\n", addr, u32, rc));4218 Log(("cpu_inw: addr=%#06x -> %#x rc=%Rrc\n", addr, u32, rc)); 4219 4219 remR3RaiseRC(env->pVM, rc); 4220 4220 return (int)u32; … … 4237 4237 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST) 4238 4238 { 4239 Log(("cpu_inl: addr=%#06x -> %#x rc=% Vrc\n", addr, u32, rc));4239 Log(("cpu_inl: addr=%#06x -> %#x rc=%Rrc\n", addr, u32, rc)); 4240 4240 remR3RaiseRC(env->pVM, rc); 4241 4241 return (int)u32; … … 4341 4341 * Bitch about it. 4342 4342 */ 4343 RTLogPrintf("internal REM fatal error: rc=% Vrc %s\n", rc, pszTip);4344 AssertReleaseMsgFailed(("internal REM fatal error: rc=% Vrc %s\n", rc, pszTip));4343 RTLogPrintf("internal REM fatal error: rc=%Rrc %s\n", rc, pszTip); 4344 AssertReleaseMsgFailed(("internal REM fatal error: rc=%Rrc %s\n", rc, pszTip)); 4345 4345 4346 4346 /*
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