VirtualBox

Changeset 13935 in vbox


Ignore:
Timestamp:
Nov 6, 2008 8:23:28 PM (16 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
38959
Message:

PGM: One more CTXSUFF (guest AMD64 root).

Location:
trunk/src/VBox/VMM
Files:
4 edited

Legend:

Unmodified
Added
Removed

  • TabularUnified trunk/src/VBox/VMM/PGMInternal.h

    r13933 r13935  
    20322032    /** @name AMD64 Guest Paging.
    20332033     * @{ */
    2034     /** The guest's page directory pointer table, HC pointer. */
    2035 #if 0///@todo def VBOX_WITH_2X_4GB_ADDR_SPACE
    2036     R3R0PTRTYPE(PX86PML4)           pGstPaePML4HC;
    2037 #else
    2038     R3R0PTRTYPE(PX86PML4)           pGstPaePML4HC;
     2034    /** The guest's page directory pointer table, R3 pointer. */
     2035    R3PTRTYPE(PX86PML4)             pGstAmd64PML4R3;
     2036#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
     2037    /** The guest's page directory pointer table, R0 pointer. */
     2038    R0PTRTYPE(PX86PML4)             pGstAmd64PML4R0;
    20392039#endif
    20402040    /** @} */
    … …  
    35583558
    35593559/**
     3560 * Gets the page map level-4 pointer for the guest.
     3561 *
     3562 * @returns Pointer to the PML4 page.
     3563 * @param   pPGM        Pointer to the PGM instance data.
     3564 */
     3565DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGM pPGM)
     3566{
     3567#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
     3568    PX86PML4 pGuestPml4;
     3569    int rc = PGMDynMapGCPage(PGM2VM(pPGM), pPGM->GCPhysCR3, (void **)pGuestPml4);
     3570    AssertRCReturn(rc, NULL);
     3571    return pGuestPml4;
     3572#else
     3573    Assert(pPGM->CTX_SUFF(pGstAmd64PML4));
     3574    return pPGM->CTX_SUFF(pGstAmd64PML4);
     3575#endif
     3576}
     3577
     3578
     3579/**
     3580 * Gets the pointer to a page map level-4 entry.
     3581 *
     3582 * @returns Pointer to the PML4 entry.
     3583 * @param   pPGM        Pointer to the PGM instance data.
     3584 * @param   iPml4e      The index.
     3585 */
     3586DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4e)
     3587{
     3588#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
     3589    PX86PML4 pGuestPml4;
     3590    int rc = PGMDynMapGCPage(PGM2VM(pPGM), pPGM->GCPhysCR3, (void **)pGuestPml4);
     3591    AssertRCReturn(rc, NULL);
     3592    return &pGuestPml4->a[iPml4e];
     3593#else
     3594    Assert(pPGM->CTX_SUFF(pGstAmd64PML4));
     3595    return &pPGM->CTX_SUFF(pGstAmd64PML4)->a[iPml4e];
     3596#endif
     3597}
     3598
     3599
     3600/**
     3601 * Gets a page map level-4 entry.
     3602 *
     3603 * @returns The PML4 entry.
     3604 * @param   pPGM        Pointer to the PGM instance data.
     3605 * @param   iPml4e      The index.
     3606 */
     3607DECLINLINE(X86PGPAEUINT) pgmGstGetLongModePML4E(PPGM pPGM, unsigned int iPml4e)
     3608{
     3609#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
     3610    PX86PML4 pGuestPml4;
     3611    int rc = PGMDynMapGCPage(PGM2VM(pPGM), pPGM->GCPhysCR3, (void **)pGuestPml4);
     3612    AssertRCReturn(rc, 0);
     3613    return pGuestPml4->a[iPml4e].u;
     3614#else
     3615    Assert(pPGM->CTX_SUFF(pGstAmd64PML4));
     3616    return pPGM->CTX_SUFF(pGstAmd64PML4)->a[iPml4e].u;
     3617#endif
     3618}
     3619
     3620
     3621/**
    35603622 * Gets the page directory pointer entry for the specified address.
    35613623 *
    … …  
    35683630DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e)
    35693631{
    3570     const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
    3571 
    3572     Assert(pPGM->pGstPaePML4HC);
    3573     *ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
    3574     if ((*ppPml4e)->n.u1Present)
     3632    PX86PML4        pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
     3633    const unsigned  iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
     3634    PCX86PML4E      pPml4e = *ppPml4e = &pGuestPml4->a[iPml4e];
     3635    if (pPml4e->n.u1Present)
    35753636    {
    35763637        PX86PDPT pPdpt;
    3577         int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdpt);
    3578         if (RT_FAILURE(rc))
    3579         {
    3580             AssertFailed();
    3581             return NULL;
    3582         }
    3583         const unsigned iPdPt  = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
     3638        int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
     3639        AssertRCReturn(rc, NULL);
     3640
     3641        const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
    35843642        return &pPdpt->a[iPdPt];
    35853643    }
    … …  
    36003658DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
    36013659{
    3602     const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
    3603 
    3604     Assert(pPGM->pGstPaePML4HC);
    3605     *ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
    3606     if ((*ppPml4e)->n.u1Present)
     3660    PX86PML4        pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
     3661    const unsigned  iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
     3662    PCX86PML4E      pPml4e = *ppPml4e = &pGuestPml4->a[iPml4e];
     3663    if (pPml4e->n.u1Present)
    36073664    {
    3608         PX86PDPT pPdptTemp;
    3609         int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdptTemp);
    3610         if (RT_FAILURE(rc))
     3665        PCX86PDPT   pPdptTemp;
     3666        int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
     3667        AssertRCReturn(rc, 0);
     3668
     3669        const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
     3670        *pPdpe = pPdptTemp->a[iPdPt];
     3671        if (pPdptTemp->a[iPdPt].n.u1Present)
    36113672        {
    3612             AssertFailed();
    3613             return 0;
    3614         }
    3615 
    3616         const unsigned iPdPt  = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
    3617         *pPdpe = pPdptTemp->a[iPdPt];
    3618         if (pPdpe->n.u1Present)
    3619         {
    3620             PX86PDPAE pPD;
    3621 
    3622             rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
    3623             if (RT_FAILURE(rc))
    3624             {
    3625                 AssertFailed();
    3626                 return 0;
    3627             }
     3673            PCX86PDPAE pPD;
     3674            rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
     3675            AssertRCReturn(rc, 0);
     3676
    36283677            const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
    36293678            return pPD->a[iPD].u;
    … …  
    36443693DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr)
    36453694{
    3646     const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
    3647 
    3648     Assert(pPGM->pGstPaePML4HC);
    3649     if (pPGM->pGstPaePML4HC->a[iPml4e].n.u1Present)
     3695    PCX86PML4       pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
     3696    const unsigned  iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
     3697    if (pGuestPml4->a[iPml4e].n.u1Present)
    36503698    {
    3651         PX86PDPT pPdptTemp;
    3652         int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPGM->pGstPaePML4HC->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
    3653         if (RT_FAILURE(rc))
    3654         {
    3655             AssertFailed();
    3656             return 0;
    3657         }
    3658 
    3659         const unsigned iPdPt  = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
     3699        PCX86PDPT   pPdptTemp;
     3700        int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPml4->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
     3701        AssertRCReturn(rc, 0);
     3702
     3703        const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
    36603704        if (pPdptTemp->a[iPdPt].n.u1Present)
    36613705        {
    3662             PX86PDPAE pPD;
    3663 
     3706            PCX86PDPAE pPD;
    36643707            rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
    3665             if (RT_FAILURE(rc))
    3666             {
    3667                 AssertFailed();
    3668                 return 0;
    3669             }
     3708            AssertRCReturn(rc, 0);
     3709
    36703710            const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
    36713711            return pPD->a[iPD].u;
    … …  
    36863726DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr)
    36873727{
    3688     const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
    3689 
    3690     Assert(pPGM->pGstPaePML4HC);
    3691     if (pPGM->pGstPaePML4HC->a[iPml4e].n.u1Present)
     3728    PCX86PML4       pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
     3729    const unsigned  iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
     3730    if (pGuestPml4->a[iPml4e].n.u1Present)
    36923731    {
    3693         PX86PDPT pPdptTemp;
    3694         int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPGM->pGstPaePML4HC->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
    3695         if (RT_FAILURE(rc))
    3696         {
    3697             AssertFailed();
    3698             return NULL;
    3699         }
    3700 
    3701         const unsigned iPdPt  = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
     3732        PCX86PDPT   pPdptTemp;
     3733        int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPml4->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
     3734        AssertRCReturn(rc, NULL);
     3735
     3736        const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
    37023737        if (pPdptTemp->a[iPdPt].n.u1Present)
    37033738        {
    37043739            PX86PDPAE pPD;
    3705 
    37063740            rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
    3707             if (RT_FAILURE(rc))
    3708             {
    3709                 AssertFailed();
    3710                 return NULL;
    3711             }
     3741            AssertRCReturn(rc, NULL);
     3742
    37123743            const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
    37133744            return &pPD->a[iPD];
    … …  
    37313762DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe, unsigned *piPD)
    37323763{
    3733     const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
    3734 
    3735     Assert(pPGM->pGstPaePML4HC);
    3736     *ppPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
    3737     if ((*ppPml4e)->n.u1Present)
     3764    PX86PML4        pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
     3765    const unsigned  iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
     3766    PCX86PML4E      pPml4e = *ppPml4e = &pGuestPml4->a[iPml4e];
     3767    if (pPml4e->n.u1Present)
    37383768    {
    3739         PX86PDPT pPdptTemp;
    3740         int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdptTemp);
    3741         if (RT_FAILURE(rc))
    3742         {
    3743             AssertFailed();
    3744             return 0;
    3745         }
    3746 
    3747         const unsigned iPdPt  = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
     3769        PCX86PDPT   pPdptTemp;
     3770        int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
     3771        AssertRCReturn(rc, NULL);
     3772
     3773        const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
    37483774        *pPdpe = pPdptTemp->a[iPdPt];
    3749         if (pPdpe->n.u1Present)
     3775        if (pPdptTemp->a[iPdPt].n.u1Present)
    37503776        {
    37513777            PX86PDPAE pPD;
    3752 
    3753             rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
    3754             if (RT_FAILURE(rc))
    3755             {
    3756                 AssertFailed();
    3757                 return 0;
    3758             }
     3778            rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
     3779            AssertRCReturn(rc, NULL);
     3780
    37593781            *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
    37603782            return pPD;
    … …  
    37763798DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCUINTPTR64 GCPtr, unsigned *piPD)
    37773799{
    3778     PX86PML4E pPml4e;
    3779     PX86PDPE pPdpe;
    3780     const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
    3781 
    3782     Assert(pPGM->pGstPaePML4HC);
    3783     pPml4e = &pPGM->pGstPaePML4HC->a[iPml4e];
    3784     if (pPml4e->n.u1Present)
     3800    PCX86PML4       pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
     3801    const unsigned  iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
     3802    if (pGuestPml4->a[iPml4e].n.u1Present)
    37853803    {
    3786         PX86PDPT pPdptTemp;
    3787         int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
    3788         if (RT_FAILURE(rc))
    3789         {
    3790             AssertFailed();
    3791             return 0;
    3792         }
    3793 
    3794         const unsigned iPdPt  = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
    3795         pPdpe = &pPdptTemp->a[iPdPt];
    3796         if (pPdpe->n.u1Present)
     3804        PCX86PDPT   pPdptTemp;
     3805        int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPml4->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
     3806        AssertRCReturn(rc, NULL);
     3807
     3808        const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
     3809        if (pPdptTemp->a[iPdPt].n.u1Present)
    37973810        {
    37983811            PX86PDPAE pPD;
    3799 
    3800             rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
    3801             if (RT_FAILURE(rc))
    3802             {
    3803                 AssertFailed();
    3804                 return 0;
    3805             }
     3812            rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
     3813            AssertRCReturn(rc, NULL);
     3814
    38063815            *piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
    38073816            return pPD;
    38083817        }
    38093818    }
    3810     return 0;
     3819    return NULL;
    38113820}
    38123821

  • TabularUnified trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

    r13933 r13935  
    888888
    889889/**
    890  * Syncs the SHADOW page directory pointer for the specified address. Allocates
    891  * backing pages in case the PDPT or PML4 entry is missing.
     890 * Syncs the SHADOW page directory pointer for the specified address.
     891 *
     892 * Allocates backing pages in case the PDPT or PML4 entry is missing.
     893 *
     894 * The caller is responsible for making sure the guest has a valid PD before
     895 * calling this function.
    892896 *
    893897 * @returns VBox status.
    … …  
    905909    PX86PML4E      pPml4e;
    906910    PPGMPOOLPAGE   pShwPage;
     911    X86PML4E       Pml4eGst;
    907912    int            rc;
    908913    bool           fNestedPaging = HWACCMIsNestedPagingActive(pVM);
    … …  
    919924        if (!fNestedPaging)
    920925        {
     926            /** @todo why are we looking up the guest PML4E here?  Isn't pGstPml4e
     927             *        trustworthy? (Remove pgmGstGetLongModePML4E if pGstPml4e and pGstPdpe
     928             *        are fine.) */
    921929            Assert(pVM->pgm.s.pHCShwAmd64CR3);
    922             Assert(pPGM->pGstPaePML4HC);
    923 
    924             PX86PML4E pPml4eGst = &pPGM->pGstPaePML4HC->a[iPml4e];
    925 
    926             rc = pgmPoolAlloc(pVM, pPml4eGst->u & X86_PML4E_PG_MASK,
     930            Pml4eGst.u = pgmGstGetLongModePML4E(&pVM->pgm.s, iPml4e);
     931
     932            rc = pgmPoolAlloc(pVM, Pml4eGst.u & X86_PML4E_PG_MASK,
    927933                              PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e, &pShwPage);
    928934        }
    … …  
    946952    }
    947953    /* The PDPT was cached or created; hook it up now. */
    948     pPml4e->u |=   pShwPage->Core.Key
    949                 | (pGstPml4e->u & ~(X86_PML4E_PG_MASK | X86_PML4E_AVL_MASK | X86_PML4E_PCD | X86_PML4E_PWT));
     954    pPml4e->u |= pShwPage->Core.Key
     955              | (pGstPml4e->u & ~(X86_PML4E_PG_MASK | X86_PML4E_AVL_MASK | X86_PML4E_PCD | X86_PML4E_PWT));
    950956
    951957    const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
    … …  
    959965        if (!fNestedPaging)
    960966        {
    961             Assert(pPGM->pGstPaePML4HC);
    962 
    963             PX86PML4E pPml4eGst = &pPGM->pGstPaePML4HC->a[iPml4e];
    964             PX86PDPT  pPdptGst;
    965             rc = PGM_GCPHYS_2_PTR(pVM, pPml4eGst->u & X86_PML4E_PG_MASK, &pPdptGst);
     967            /** @todo why are we looking up the guest PDPTE here?  Isn't pGstPdpe
     968             *        trustworthy? */
     969            Pml4eGst.u = pgmGstGetLongModePML4E(&pVM->pgm.s, iPml4e);
     970            PX86PDPT pPdptGst;
     971            rc = PGM_GCPHYS_2_PTR(pVM, Pml4eGst.u & X86_PML4E_PG_MASK, &pPdptGst);
    966972            AssertRCReturn(rc, rc);
    967973
    … …  
    988994    }
    989995    /* The PD was cached or created; hook it up now. */
    990     pPdpe->u |=    pShwPage->Core.Key
    991                 | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
     996    pPdpe->u |= pShwPage->Core.Key
     997             | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
    992998
    993999    *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);

  • TabularUnified trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

    r13933 r13935  
    37093709        RTGCPHYS        GCPhysPdptSrc;
    37103710
    3711         pPml4eSrc     = &pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPml4e];
     3711        pPml4eSrc     = pgmGstGetLongModePML4EPtr(&pVM->pgm.s, iPml4e);
    37123712        pPml4eDst     = &pVM->pgm.s.CTXMID(p,PaePML4)->a[iPml4e];
    37133713

  • TabularUnified trunk/src/VBox/VMM/VMMAll/PGMAllGst.h

    r13933 r13935  
    505505                PGM_INVL_PG(GCPtr); /** @todo this shouldn't be necessary? */
    506506            }
     507
    507508# elif PGM_GST_TYPE == PGM_TYPE_AMD64
    508             PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
    509 
    510             pVM->pgm.s.pGstPaePML4HC = (R3R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
    511 
     509            pVM->pgm.s.pGstAmd64PML4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
     510#  ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
     511            pVM->pgm.s.pGstAmd64PML4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
     512#  endif
    512513            if (!HWACCMIsNestedPagingActive(pVM))
    513514            {
     515                PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
    514516                if (pVM->pgm.s.pHCShwAmd64CR3)
    515517                {
    … …  
    587589
    588590#elif PGM_GST_TYPE == PGM_TYPE_AMD64
    589     pVM->pgm.s.pGstPaePML4HC = 0;
     591    pVM->pgm.s.pGstAmd64PML4R3 = 0;
     592# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
     593    pVM->pgm.s.pGstAmd64PML4R0 = 0;
     594# endif
    590595    if (!HWACCMIsNestedPagingActive(pVM))
    591596    {
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