Changeset 13960 in vbox for trunk/src/VBox/VMM/VMMSwitcher
- Timestamp:
- Nov 7, 2008 1:04:45 PM (17 years ago)
- svn:sync-xref-src-repo-rev:
- 38992
- Location:
- trunk/src/VBox/VMM/VMMSwitcher
- Files:
-
- 2 edited
-
AMD64ToPAE.asm (modified) (21 diffs)
-
PAEand32Bit.mac (modified) (19 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMSwitcher/AMD64ToPAE.asm
r12602 r13960 198 198 ; 199 199 ; USES/DESTROYS: 200 ; - eax, ecx, edx 200 ; - eax, ecx, edx, r8 201 201 ; 202 202 ; ASSUMPTION: … … 206 206 ALIGNCODE(16) 207 207 BEGINPROC vmmR0HostToGuestAsm 208 ;; Store the offset from CPUM to CPUMCPU in r8 209 mov r8, [rdx + CPUM.ulOffCPUMCPU] 210 208 211 ;; 209 212 ;; Save CPU host context … … 211 214 ;; 212 215 ; general registers. 213 ; mov [rdx + CPUM.Host.rax], rax - scratch214 mov [rdx + CPUM.Host.rbx], rbx215 ; mov [rdx + CPUM.Host.rcx], rcx - scratch216 ; mov [rdx + CPUM.Host.rdx], rdx - scratch217 mov [rdx + CPUM.Host.rdi], rdi218 mov [rdx + CPUM.Host.rsi], rsi219 mov [rdx + CPUM.Host.rsp], rsp220 mov [rdx + CPUM.Host.rbp], rbp221 ; mov [rdx + CPUM.Host.r8 ], r8 - scratch222 ; mov [rdx + CPUM.Host.r9 ], r9 - scratch223 mov [rdx + CPUM.Host.r10], r10224 mov [rdx + CPUM.Host.r11], r11225 mov [rdx + CPUM.Host.r12], r12226 mov [rdx + CPUM.Host.r13], r13227 mov [rdx + CPUM.Host.r14], r14228 mov [rdx + CPUM.Host.r15], r15216 ; mov [rdx + r8 + CPUMCPU.Host.rax], rax - scratch 217 mov [rdx + r8 + CPUMCPU.Host.rbx], rbx 218 ; mov [rdx + r8 + CPUMCPU.Host.rcx], rcx - scratch 219 ; mov [rdx + r8 + CPUMCPU.Host.rdx], rdx - scratch 220 mov [rdx + r8 + CPUMCPU.Host.rdi], rdi 221 mov [rdx + r8 + CPUMCPU.Host.rsi], rsi 222 mov [rdx + r8 + CPUMCPU.Host.rsp], rsp 223 mov [rdx + r8 + CPUMCPU.Host.rbp], rbp 224 ; mov [rdx + r8 + CPUMCPU.Host.r8 ], r8 - scratch 225 ; mov [rdx + r8 + CPUMCPU.Host.r9 ], r9 - scratch 226 mov [rdx + r8 + CPUMCPU.Host.r10], r10 227 mov [rdx + r8 + CPUMCPU.Host.r11], r11 228 mov [rdx + r8 + CPUMCPU.Host.r12], r12 229 mov [rdx + r8 + CPUMCPU.Host.r13], r13 230 mov [rdx + r8 + CPUMCPU.Host.r14], r14 231 mov [rdx + r8 + CPUMCPU.Host.r15], r15 229 232 ; selectors. 230 mov [rdx + CPUM.Host.ds], ds231 mov [rdx + CPUM.Host.es], es232 mov [rdx + CPUM.Host.fs], fs233 mov [rdx + CPUM.Host.gs], gs234 mov [rdx + CPUM.Host.ss], ss233 mov [rdx + r8 + CPUMCPU.Host.ds], ds 234 mov [rdx + r8 + CPUMCPU.Host.es], es 235 mov [rdx + r8 + CPUMCPU.Host.fs], fs 236 mov [rdx + r8 + CPUMCPU.Host.gs], gs 237 mov [rdx + r8 + CPUMCPU.Host.ss], ss 235 238 ; MSRs 236 239 mov rbx, rdx 237 240 mov ecx, MSR_K8_FS_BASE 238 241 rdmsr 239 mov [rbx + CPUM.Host.FSbase], eax240 mov [rbx + CPUM.Host.FSbase + 4], edx242 mov [rbx + r8 + CPUMCPU.Host.FSbase], eax 243 mov [rbx + r8 + CPUMCPU.Host.FSbase + 4], edx 241 244 mov ecx, MSR_K8_GS_BASE 242 245 rdmsr 243 mov [rbx + CPUM.Host.GSbase], eax244 mov [rbx + CPUM.Host.GSbase + 4], edx246 mov [rbx + r8 + CPUMCPU.Host.GSbase], eax 247 mov [rbx + r8 + CPUMCPU.Host.GSbase + 4], edx 245 248 mov ecx, MSR_K6_EFER 246 249 rdmsr 247 mov [rbx + CPUM.Host.efer], eax248 mov [rbx + CPUM.Host.efer + 4], edx250 mov [rbx + r8 + CPUMCPU.Host.efer], eax 251 mov [rbx + r8 + CPUMCPU.Host.efer + 4], edx 249 252 mov ecx, MSR_K6_EFER 250 253 mov rdx, rbx 251 254 ; special registers. 252 sldt [rdx + CPUM.Host.ldtr]253 sidt [rdx + CPUM.Host.idtr]254 sgdt [rdx + CPUM.Host.gdtr]255 str [rdx + CPUM.Host.tr] ; yasm BUG, generates sldt. YASMCHECK!255 sldt [rdx + r8 + CPUMCPU.Host.ldtr] 256 sidt [rdx + r8 + CPUMCPU.Host.idtr] 257 sgdt [rdx + r8 + CPUMCPU.Host.gdtr] 258 str [rdx + r8 + CPUMCPU.Host.tr] ; yasm BUG, generates sldt. YASMCHECK! 256 259 ; flags 257 260 pushf 258 pop qword [rdx + CPUM.Host.rflags]261 pop qword [rdx + r8 + CPUMCPU.Host.rflags] 259 262 260 263 FIXUP FIX_NO_SYSENTER_JMP, 0, htg_no_sysenter - NAME(Start) ; this will insert a jmp htg_no_sysenter if host doesn't use sysenter. … … 263 266 mov rbx, rdx ; save edx 264 267 rdmsr ; edx:eax <- MSR[ecx] 265 mov [rbx + CPUM.Host.SysEnter.cs], rax266 mov [rbx + CPUM.Host.SysEnter.cs + 4], rdx268 mov [rbx + r8 + CPUMCPU.Host.SysEnter.cs], rax 269 mov [rbx + r8 + CPUMCPU.Host.SysEnter.cs + 4], rdx 267 270 xor rax, rax ; load 0:0 to cause #GP upon sysenter 268 271 xor rdx, rdx … … 275 278 276 279 ;; handle use flags. 277 mov esi, [rdx + CPUM.fUseFlags] ; esi == use flags.280 mov esi, [rdx + r8 + CPUMCPU.fUseFlags] ; esi == use flags. 278 281 and esi, ~CPUM_USED_FPU ; Clear CPUM_USED_* flags. ;;@todo FPU check can be optimized to use cr0 flags! 279 mov [rdx + CPUM.fUseFlags], esi282 mov [rdx + r8 + CPUMCPU.fUseFlags], esi 280 283 281 284 ; debug registers. … … 288 291 ; control registers. 289 292 mov rax, cr0 290 mov [rdx + CPUM.Host.cr0], rax291 ;mov rax, cr2 ; assume host os don't s uff things in cr2. (safe)292 ;mov [rdx + CPUM.Host.cr2], rax293 mov [rdx + r8 + CPUMCPU.Host.cr0], rax 294 ;mov rax, cr2 ; assume host os don't stuff things in cr2. (safe) 295 ;mov [rdx + r8 + CPUMCPU.Host.cr2], rax 293 296 mov rax, cr3 294 mov [rdx + CPUM.Host.cr3], rax297 mov [rdx + r8 + CPUMCPU.Host.cr3], rax 295 298 mov rax, cr4 296 mov [rdx + CPUM.Host.cr4], rax299 mov [rdx + r8 + CPUMCPU.Host.cr4], rax 297 300 298 301 ;; … … 306 309 ; 307 310 and rax, X86_CR4_MCE | X86_CR4_PSE | X86_CR4_PAE 308 mov ecx, [rdx + CPUM.Guest.cr4]311 mov ecx, [rdx + r8 + CPUMCPU.Guest.cr4] 309 312 DEBUG_CHAR('b') ; trashes esi 310 ;; @todo Switcher cleanup: Determin base CR4 during CPUMR0Init / VMMR3SelectSwitcher putting it313 ;; @todo Switcher cleanup: Determine base CR4 during CPUMR0Init / VMMR3SelectSwitcher putting it 311 314 ; in CPUM.Hyper.cr4 (which isn't currently being used). That should 312 315 ; simplify this operation a bit (and improve locality of the data). … … 322 325 DEBUG_CHAR('c') ; trashes esi 323 326 324 mov eax, [rdx + CPUM.Guest.cr0]327 mov eax, [rdx + r8 + CPUMCPU.Guest.cr0] 325 328 and eax, X86_CR0_EM 326 329 or eax, X86_CR0_PE | X86_CR0_PG | X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP … … 360 363 DEBUG_S_CHAR('s'); 361 364 mov rax, dr7 ; not sure, but if I read the docs right this will trap if GD is set. FIXME!!! 362 mov [rdx + CPUM.Host.dr7], rax365 mov [rdx + r8 + CPUMCPU.Host.dr7], rax 363 366 xor eax, eax ; clear everything. (bit 12? is read as 1...) 364 367 mov dr7, rax 365 368 mov rax, dr6 ; just in case we save the state register too. 366 mov [rdx + CPUM.Host.dr6], rax369 mov [rdx + r8 + CPUMCPU.Host.dr6], rax 367 370 ; save host DR0-3? 368 371 test esi, CPUM_USE_DEBUG_REGS … … 370 373 DEBUG_S_CHAR('S'); 371 374 mov rax, dr0 372 mov [rdx + CPUM.Host.dr0], rax375 mov [rdx + r8 + CPUMCPU.Host.dr0], rax 373 376 mov rbx, dr1 374 mov [rdx + CPUM.Host.dr1], rbx377 mov [rdx + r8 + CPUMCPU.Host.dr1], rbx 375 378 mov rcx, dr2 376 mov [rdx + CPUM.Host.dr2], rcx379 mov [rdx + r8 + CPUMCPU.Host.dr2], rcx 377 380 mov rax, dr3 378 mov [rdx + CPUM.Host.dr3], rax381 mov [rdx + r8 + CPUMCPU.Host.dr3], rax 379 382 jmp htg_debug_regs_no 380 383 … … 472 475 473 476 ;; use flags. 474 mov esi, [edx + CPUM.fUseFlags] 477 mov esi, [edx + CPUM.ulOffCPUMCPU] 478 mov esi, [edx + esi + CPUMCPU.fUseFlags] 475 479 476 480 ; debug registers … … 632 636 FIXUP FIX_GC_CPUM_OFF, 1, 0 633 637 mov edx, 0ffffffffh 634 638 ; Convert to CPUMCPU pointer 639 add edx, [edx + CPUM.ulOffCPUMCPU] 640 635 641 ; Skip return address (assumes called!) 636 642 lea esp, [esp + 4] … … 642 648 push eax ; save return code. 643 649 mov eax, [esp + 4 + CPUMCTXCORE.edi] 644 mov [edx + CPUM .Guest.edi], eax650 mov [edx + CPUMCPU.Guest.edi], eax 645 651 mov eax, [esp + 4 + CPUMCTXCORE.esi] 646 mov [edx + CPUM .Guest.esi], eax652 mov [edx + CPUMCPU.Guest.esi], eax 647 653 mov eax, [esp + 4 + CPUMCTXCORE.ebp] 648 mov [edx + CPUM .Guest.ebp], eax654 mov [edx + CPUMCPU.Guest.ebp], eax 649 655 mov eax, [esp + 4 + CPUMCTXCORE.eax] 650 mov [edx + CPUM .Guest.eax], eax656 mov [edx + CPUMCPU.Guest.eax], eax 651 657 mov eax, [esp + 4 + CPUMCTXCORE.ebx] 652 mov [edx + CPUM .Guest.ebx], eax658 mov [edx + CPUMCPU.Guest.ebx], eax 653 659 mov eax, [esp + 4 + CPUMCTXCORE.edx] 654 mov [edx + CPUM .Guest.edx], eax660 mov [edx + CPUMCPU.Guest.edx], eax 655 661 mov eax, [esp + 4 + CPUMCTXCORE.ecx] 656 mov [edx + CPUM .Guest.ecx], eax662 mov [edx + CPUMCPU.Guest.ecx], eax 657 663 mov eax, [esp + 4 + CPUMCTXCORE.esp] 658 mov [edx + CPUM .Guest.esp], eax664 mov [edx + CPUMCPU.Guest.esp], eax 659 665 ; selectors 660 666 mov eax, [esp + 4 + CPUMCTXCORE.ss] 661 mov [edx + CPUM .Guest.ss], eax667 mov [edx + CPUMCPU.Guest.ss], eax 662 668 mov eax, [esp + 4 + CPUMCTXCORE.gs] 663 mov [edx + CPUM .Guest.gs], eax669 mov [edx + CPUMCPU.Guest.gs], eax 664 670 mov eax, [esp + 4 + CPUMCTXCORE.fs] 665 mov [edx + CPUM .Guest.fs], eax671 mov [edx + CPUMCPU.Guest.fs], eax 666 672 mov eax, [esp + 4 + CPUMCTXCORE.es] 667 mov [edx + CPUM .Guest.es], eax673 mov [edx + CPUMCPU.Guest.es], eax 668 674 mov eax, [esp + 4 + CPUMCTXCORE.ds] 669 mov [edx + CPUM .Guest.ds], eax675 mov [edx + CPUMCPU.Guest.ds], eax 670 676 mov eax, [esp + 4 + CPUMCTXCORE.cs] 671 mov [edx + CPUM .Guest.cs], eax677 mov [edx + CPUMCPU.Guest.cs], eax 672 678 ; flags 673 679 mov eax, [esp + 4 + CPUMCTXCORE.eflags] 674 mov [edx + CPUM .Guest.eflags], eax680 mov [edx + CPUMCPU.Guest.eflags], eax 675 681 ; eip 676 682 mov eax, [esp + 4 + CPUMCTXCORE.eip] 677 mov [edx + CPUM .Guest.eip], eax683 mov [edx + CPUMCPU.Guest.eip], eax 678 684 ; jump to common worker code. 679 685 pop eax ; restore return code. 686 ; Load CPUM into edx again 687 sub edx, [edx + CPUMCPU.ulOffCPUM] 680 688 681 689 add esp, CPUMCTXCORE_size ; skip CPUMCTXCORE structure … … 913 921 914 922 ; load final cr3 915 mov rsi, [rdx + CPUM.Host.cr3]923 mov rsi, [rdx + r8 + CPUMCPU.Host.cr3] 916 924 mov cr3, rsi 917 925 DEBUG_CHAR('@') … … 922 930 ; Load CPUM pointer into edx 923 931 mov rdx, [NAME(pCpumHC) wrt rip] 932 ; Load the CPUMCPU offset. 933 mov r8, [rdx + CPUM.ulOffCPUMCPU] 934 924 935 ; activate host gdt and idt 925 lgdt [rdx + CPUM.Host.gdtr]936 lgdt [rdx + r8 + CPUMCPU.Host.gdtr] 926 937 DEBUG_CHAR('0') 927 lidt [rdx + CPUM.Host.idtr]938 lidt [rdx + r8 + CPUMCPU.Host.idtr] 928 939 DEBUG_CHAR('1') 929 940 ; Restore TSS selector; must mark it as not busy before using ltr (!) 930 941 %if 1 ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p) 931 movzx eax, word [rdx + CPUM.Host.tr] ; eax <- TR942 movzx eax, word [rdx + r8 + CPUMCPU.Host.tr] ; eax <- TR 932 943 and al, 0F8h ; mask away TI and RPL bits, get descriptor offset. 933 add rax, [rdx + CPUM.Host.gdtr + 2] ; eax <- GDTR.address + descriptor offset.944 add rax, [rdx + r8 + CPUMCPU.Host.gdtr + 2] ; eax <- GDTR.address + descriptor offset. 934 945 and dword [rax + 4], ~0200h ; clear busy flag (2nd type2 bit) 935 ltr word [rdx + CPUM.Host.tr]946 ltr word [rdx + r8 + CPUMCPU.Host.tr] 936 947 %else 937 movzx eax, word [rdx + CPUM.Host.tr] ; eax <- TR948 movzx eax, word [rdx + r8 + CPUMCPU.Host.tr] ; eax <- TR 938 949 and al, 0F8h ; mask away TI and RPL bits, get descriptor offset. 939 add rax, [rdx + CPUM.Host.gdtr + 2] ; eax <- GDTR.address + descriptor offset.950 add rax, [rdx + r8 + CPUMCPU.Host.gdtr + 2] ; eax <- GDTR.address + descriptor offset. 940 951 mov ecx, [rax + 4] ; ecx <- 2nd descriptor dword 941 952 mov ebx, ecx ; save orginal value 942 953 and ecx, ~0200h ; clear busy flag (2nd type2 bit) 943 954 mov [rax + 4], ccx ; not using xchg here is paranoia.. 944 ltr word [rdx + CPUM.Host.tr]955 ltr word [rdx + r8 + CPUMCPU.Host.tr] 945 956 xchg [rax + 4], ebx ; using xchg is paranoia too... 946 957 %endif 947 958 ; activate ldt 948 959 DEBUG_CHAR('2') 949 lldt [rdx + CPUM.Host.ldtr]960 lldt [rdx + r8 + CPUMCPU.Host.ldtr] 950 961 ; Restore segment registers 951 mov eax, [rdx + CPUM.Host.ds]962 mov eax, [rdx + r8 + CPUMCPU.Host.ds] 952 963 mov ds, eax 953 mov eax, [rdx + CPUM.Host.es]964 mov eax, [rdx + r8 + CPUMCPU.Host.es] 954 965 mov es, eax 955 mov eax, [rdx + CPUM.Host.fs]966 mov eax, [rdx + r8 + CPUMCPU.Host.fs] 956 967 mov fs, eax 957 mov eax, [rdx + CPUM.Host.gs]968 mov eax, [rdx + r8 + CPUMCPU.Host.gs] 958 969 mov gs, eax 959 970 ; restore stack 960 mov eax, [rdx + CPUM.Host.ss]971 mov eax, [rdx + r8 + CPUMCPU.Host.ss] 961 972 mov ss, eax 962 mov rsp, [rdx + CPUM.Host.rsp]973 mov rsp, [rdx + r8 + CPUMCPU.Host.rsp] 963 974 964 975 FIXUP FIX_NO_SYSENTER_JMP, 0, gth_sysenter_no - NAME(Start) ; this will insert a jmp gth_sysenter_no if host doesn't use sysenter. 965 976 ; restore MSR_IA32_SYSENTER_CS register. 966 977 mov ecx, MSR_IA32_SYSENTER_CS 967 mov eax, [rdx + CPUM.Host.SysEnter.cs]968 mov ebx, [rdx + CPUM.Host.SysEnter.cs + 4]978 mov eax, [rdx + r8 + CPUMCPU.Host.SysEnter.cs] 979 mov ebx, [rdx + r8 + CPUMCPU.Host.SysEnter.cs + 4] 969 980 mov rbx, rdx ; save/load edx 970 981 wrmsr ; MSR[ecx] <- edx:eax … … 979 990 ; Restore FPU if guest has used it. 980 991 ; Using fxrstor should ensure that we're not causing unwanted exception on the host. 981 mov esi, [rdx + CPUM.fUseFlags] ; esi == use flags.992 mov esi, [rdx + r8 + CPUMCPU.fUseFlags] ; esi == use flags. 982 993 test esi, CPUM_USED_FPU 983 994 jz short gth_fpu_no … … 986 997 mov cr0, rcx 987 998 988 fxsave [rdx + CPUM.Guest.fpu]989 fxrstor [rdx + CPUM.Host.fpu]999 fxsave [rdx + r8 + CPUMCPU.Guest.fpu] 1000 fxrstor [rdx + r8 + CPUMCPU.Host.fpu] 990 1001 jmp short gth_fpu_no 991 1002 … … 996 1007 ; Would've liked to have these highere up in case of crashes, but 997 1008 ; the fpu stuff must be done before we restore cr0. 998 mov rcx, [rdx + CPUM.Host.cr4]1009 mov rcx, [rdx + r8 + CPUMCPU.Host.cr4] 999 1010 mov cr4, rcx 1000 mov rcx, [rdx + CPUM.Host.cr0]1011 mov rcx, [rdx + r8 + CPUMCPU.Host.cr0] 1001 1012 mov cr0, rcx 1002 ;mov rcx, [rdx + CPUM.Host.cr2] ; assumes this is waste of time.1013 ;mov rcx, [rdx + r8 + CPUMCPU.Host.cr2] ; assumes this is waste of time. 1003 1014 ;mov cr2, rcx 1004 1015 … … 1013 1024 mov rbx, rdx 1014 1025 mov ecx, MSR_K8_FS_BASE 1015 mov eax, [rbx + CPUM.Host.FSbase]1016 mov edx, [rbx + CPUM.Host.FSbase + 4]1026 mov eax, [rbx + r8 + CPUMCPU.Host.FSbase] 1027 mov edx, [rbx + r8 + CPUMCPU.Host.FSbase + 4] 1017 1028 wrmsr 1018 1029 mov ecx, MSR_K8_GS_BASE 1019 mov eax, [rbx + CPUM.Host.GSbase]1020 mov edx, [rbx + CPUM.Host.GSbase + 4]1030 mov eax, [rbx + r8 + CPUMCPU.Host.GSbase] 1031 mov edx, [rbx + r8 + CPUMCPU.Host.GSbase + 4] 1021 1032 wrmsr 1022 1033 mov ecx, MSR_K6_EFER 1023 mov eax, [rbx + CPUM.Host.efer]1024 mov edx, [rbx + CPUM.Host.efer + 4]1034 mov eax, [rbx + r8 + CPUMCPU.Host.efer] 1035 mov edx, [rbx + r8 + CPUMCPU.Host.efer + 4] 1025 1036 wrmsr 1026 1037 mov rdx, rbx … … 1029 1040 ; restore general registers. 1030 1041 mov eax, edi ; restore return code. eax = return code !! 1031 ; mov rax, [rdx + CPUM.Host.rax] - scratch + return code1032 mov rbx, [rdx + CPUM.Host.rbx]1033 ; mov rcx, [rdx + CPUM.Host.rcx] - scratch1034 ; mov rdx, [rdx + CPUM.Host.rdx] - scratch1035 mov rdi, [rdx + CPUM.Host.rdi]1036 mov rsi, [rdx + CPUM.Host.rsi]1037 mov rsp, [rdx + CPUM.Host.rsp]1038 mov rbp, [rdx + CPUM.Host.rbp]1039 ; mov r8, [rdx + CPUM.Host.r8 ] - scratch1040 ; mov r9, [rdx + CPUM.Host.r9 ] - scratch1041 mov r10, [rdx + CPUM.Host.r10]1042 mov r11, [rdx + CPUM.Host.r11]1043 mov r12, [rdx + CPUM.Host.r12]1044 mov r13, [rdx + CPUM.Host.r13]1045 mov r14, [rdx + CPUM.Host.r14]1046 mov r15, [rdx + CPUM.Host.r15]1042 ; mov rax, [rdx + r8 + CPUMCPU.Host.rax] - scratch + return code 1043 mov rbx, [rdx + r8 + CPUMCPU.Host.rbx] 1044 ; mov rcx, [rdx + r8 + CPUMCPU.Host.rcx] - scratch 1045 ; mov rdx, [rdx + r8 + CPUMCPU.Host.rdx] - scratch 1046 mov rdi, [rdx + r8 + CPUMCPU.Host.rdi] 1047 mov rsi, [rdx + r8 + CPUMCPU.Host.rsi] 1048 mov rsp, [rdx + r8 + CPUMCPU.Host.rsp] 1049 mov rbp, [rdx + r8 + CPUMCPU.Host.rbp] 1050 ; mov r8, [rdx + r8 + CPUMCPU.Host.r8 ] - scratch 1051 ; mov r9, [rdx + r8 + CPUMCPU.Host.r9 ] - scratch 1052 mov r10, [rdx + r8 + CPUMCPU.Host.r10] 1053 mov r11, [rdx + r8 + CPUMCPU.Host.r11] 1054 mov r12, [rdx + r8 + CPUMCPU.Host.r12] 1055 mov r13, [rdx + r8 + CPUMCPU.Host.r13] 1056 mov r14, [rdx + r8 + CPUMCPU.Host.r14] 1057 mov r15, [rdx + r8 + CPUMCPU.Host.r15] 1047 1058 1048 1059 ; finally restore flags. (probably not required) 1049 push qword [rdx + CPUM.Host.rflags]1060 push qword [rdx + r8 + CPUMCPU.Host.rflags] 1050 1061 popf 1051 1062 … … 1067 1078 jz short gth_debug_regs_dr7 1068 1079 DEBUG_S_CHAR('r') 1069 mov rax, [rdx + CPUM.Host.dr0]1080 mov rax, [rdx + r8 + CPUMCPU.Host.dr0] 1070 1081 mov dr0, rax 1071 mov rbx, [rdx + CPUM.Host.dr1]1082 mov rbx, [rdx + r8 + CPUMCPU.Host.dr1] 1072 1083 mov dr1, rbx 1073 mov rcx, [rdx + CPUM.Host.dr2]1084 mov rcx, [rdx + r8 + CPUMCPU.Host.dr2] 1074 1085 mov dr2, rcx 1075 mov rax, [rdx + CPUM.Host.dr3]1086 mov rax, [rdx + r8 + CPUMCPU.Host.dr3] 1076 1087 mov dr3, rax 1077 1088 gth_debug_regs_dr7: 1078 mov rbx, [rdx + CPUM.Host.dr6]1089 mov rbx, [rdx + r8 + CPUMCPU.Host.dr6] 1079 1090 mov dr6, rbx 1080 mov rcx, [rdx + CPUM.Host.dr7]1091 mov rcx, [rdx + r8 + CPUMCPU.Host.dr7] 1081 1092 mov dr7, rcx 1082 1093 jmp gth_debug_regs_no -
trunk/src/VBox/VMM/VMMSwitcher/PAEand32Bit.mac
r12602 r13960 119 119 ;; Skip eax, edx and ecx as these are not preserved over calls. 120 120 ;; 121 CPUMCPU_FROM_CPUM(edx) 121 122 ; general registers. 122 mov [edx + CPUM .Host.ebx], ebx123 mov [edx + CPUM .Host.edi], edi124 mov [edx + CPUM .Host.esi], esi125 mov [edx + CPUM .Host.esp], esp126 mov [edx + CPUM .Host.ebp], ebp123 mov [edx + CPUMCPU.Host.ebx], ebx 124 mov [edx + CPUMCPU.Host.edi], edi 125 mov [edx + CPUMCPU.Host.esi], esi 126 mov [edx + CPUMCPU.Host.esp], esp 127 mov [edx + CPUMCPU.Host.ebp], ebp 127 128 ; selectors. 128 mov [edx + CPUM .Host.ds], ds129 mov [edx + CPUM .Host.es], es130 mov [edx + CPUM .Host.fs], fs131 mov [edx + CPUM .Host.gs], gs132 mov [edx + CPUM .Host.ss], ss129 mov [edx + CPUMCPU.Host.ds], ds 130 mov [edx + CPUMCPU.Host.es], es 131 mov [edx + CPUMCPU.Host.fs], fs 132 mov [edx + CPUMCPU.Host.gs], gs 133 mov [edx + CPUMCPU.Host.ss], ss 133 134 ; special registers. 134 sldt [edx + CPUM .Host.ldtr]135 sidt [edx + CPUM .Host.idtr]136 sgdt [edx + CPUM .Host.gdtr]137 str [edx + CPUM .Host.tr]135 sldt [edx + CPUMCPU.Host.ldtr] 136 sidt [edx + CPUMCPU.Host.idtr] 137 sgdt [edx + CPUMCPU.Host.gdtr] 138 str [edx + CPUMCPU.Host.tr] 138 139 ; flags 139 140 pushfd 140 pop dword [edx + CPUM .Host.eflags]141 pop dword [edx + CPUMCPU.Host.eflags] 141 142 142 143 FIXUP FIX_NO_SYSENTER_JMP, 0, htg_no_sysenter - NAME(Start) ; this will insert a jmp htg_no_sysenter if host doesn't use sysenter. … … 145 146 mov ebx, edx ; save edx 146 147 rdmsr ; edx:eax <- MSR[ecx] 147 mov [ebx + CPUM .Host.SysEnter.cs], eax148 mov [ebx + CPUM .Host.SysEnter.cs + 4], edx148 mov [ebx + CPUMCPU.Host.SysEnter.cs], eax 149 mov [ebx + CPUMCPU.Host.SysEnter.cs + 4], edx 149 150 xor eax, eax ; load 0:0 to cause #GP upon sysenter 150 151 xor edx, edx … … 157 158 158 159 ;; handle use flags. 159 mov esi, [edx + CPUM .fUseFlags] ; esi == use flags.160 mov esi, [edx + CPUMCPU.fUseFlags] ; esi == use flags. 160 161 and esi, ~CPUM_USED_FPU ; Clear CPUM_USED_* flags. ;;@todo FPU check can be optimized to use cr0 flags! 161 mov [edx + CPUM .fUseFlags], esi162 mov [edx + CPUMCPU.fUseFlags], esi 162 163 163 164 ; debug registers. … … 169 170 ; control registers. 170 171 mov eax, cr0 171 mov [edx + CPUM .Host.cr0], eax172 mov [edx + CPUMCPU.Host.cr0], eax 172 173 ;mov eax, cr2 ; assume host os don't suff things in cr2. (safe) 173 ;mov [edx + CPUM .Host.cr2], eax174 ;mov [edx + CPUMCPU.Host.cr2], eax 174 175 mov eax, cr3 175 mov [edx + CPUM .Host.cr3], eax176 mov [edx + CPUMCPU.Host.cr3], eax 176 177 mov eax, cr4 177 mov [edx + CPUM .Host.cr4], eax178 mov [edx + CPUMCPU.Host.cr4], eax 178 179 179 180 ;; … … 188 189 ; 189 190 and eax, X86_CR4_MCE | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_VMXE 190 mov ecx, [edx + CPUM .Guest.cr4]191 mov ecx, [edx + CPUMCPU.Guest.cr4] 191 192 ;; @todo Switcher cleanup: Determin base CR4 during CPUMR0Init / VMMR3SelectSwitcher putting it 192 193 ; in CPUM.Hyper.cr4 (which isn't currently being used). That should … … 197 198 ; FXSAVE support on the host CPU 198 199 ; 200 CPUM_FROM_CPUMCPU(edx) 199 201 and ecx, [edx + CPUM.CR4.AndMask] 200 202 or eax, ecx … … 202 204 mov cr4, eax 203 205 204 mov eax, [edx + CPUM.Guest.cr0] 206 CPUMCPU_FROM_CPUM(edx) 207 mov eax, [edx + CPUMCPU.Guest.cr0] 205 208 and eax, X86_CR0_EM 206 209 or eax, X86_CR0_PE | X86_CR0_PG | X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP 207 210 mov cr0, eax 208 211 212 CPUM_FROM_CPUMCPU(edx) 209 213 ; Load new gdt so we can do far jump to guest code after cr3 reload. 210 214 lgdt [edx + CPUM.Hyper.gdtr] … … 307 311 DEBUG_CHAR('7') 308 312 313 CPUMCPU_FROM_CPUM(edx) 309 314 ;; use flags. 310 mov esi, [edx + CPUM.fUseFlags] 315 mov esi, [edx + CPUMCPU.fUseFlags] 316 CPUM_FROM_CPUMCPU(edx) 311 317 312 318 ; debug registers … … 389 395 htg_debug_regs_save_dr7and6: 390 396 DEBUG_S_CHAR('s'); 397 CPUMCPU_FROM_CPUM(edx) 391 398 mov eax, dr7 ; not sure, but if I read the docs right this will trap if GD is set. FIXME!!! 392 mov [edx + CPUM .Host.dr7], eax399 mov [edx + CPUMCPU.Host.dr7], eax 393 400 xor eax, eax ; clear everything. (bit 12? is read as 1...) 394 401 mov dr7, eax 395 402 mov eax, dr6 ; just in case we save the state register too. 396 mov [edx + CPUM.Host.dr6], eax 403 mov [edx + CPUMCPU.Host.dr6], eax 404 CPUM_FROM_CPUMCPU(edx) 397 405 jmp htg_debug_regs_no 398 406 … … 404 412 DEBUG_S_CHAR('R') 405 413 DEBUG_S_CHAR('x') 414 CPUMCPU_FROM_CPUM(edx) 406 415 ; save host DR0-3. 407 416 mov eax, dr0 408 mov [edx + CPUM .Host.dr0], eax417 mov [edx + CPUMCPU.Host.dr0], eax 409 418 mov ebx, dr1 410 mov [edx + CPUM .Host.dr1], ebx419 mov [edx + CPUMCPU.Host.dr1], ebx 411 420 mov ecx, dr2 412 mov [edx + CPUM .Host.dr2], ecx421 mov [edx + CPUMCPU.Host.dr2], ecx 413 422 mov eax, dr3 414 mov [edx + CPUM.Host.dr3], eax 423 mov [edx + CPUMCPU.Host.dr3], eax 424 CPUM_FROM_CPUMCPU(edx) 425 415 426 ; load hyper DR0-7 416 427 mov ebx, [edx + CPUM.Hyper.dr] … … 538 549 push eax 539 550 551 CPUMCPU_FROM_CPUM(edx) 540 552 mov eax, [esp + 4 + CPUMCTXCORE.eax] 541 mov [edx + CPUM .Guest.eax], eax553 mov [edx + CPUMCPU.Guest.eax], eax 542 554 mov eax, [esp + 4 + CPUMCTXCORE.ecx] 543 mov [edx + CPUM .Guest.ecx], eax555 mov [edx + CPUMCPU.Guest.ecx], eax 544 556 mov eax, [esp + 4 + CPUMCTXCORE.edx] 545 mov [edx + CPUM .Guest.edx], eax557 mov [edx + CPUMCPU.Guest.edx], eax 546 558 mov eax, [esp + 4 + CPUMCTXCORE.ebx] 547 mov [edx + CPUM .Guest.ebx], eax559 mov [edx + CPUMCPU.Guest.ebx], eax 548 560 mov eax, [esp + 4 + CPUMCTXCORE.esp] 549 mov [edx + CPUM .Guest.esp], eax561 mov [edx + CPUMCPU.Guest.esp], eax 550 562 mov eax, [esp + 4 + CPUMCTXCORE.ebp] 551 mov [edx + CPUM .Guest.ebp], eax563 mov [edx + CPUMCPU.Guest.ebp], eax 552 564 mov eax, [esp + 4 + CPUMCTXCORE.esi] 553 mov [edx + CPUM .Guest.esi], eax565 mov [edx + CPUMCPU.Guest.esi], eax 554 566 mov eax, [esp + 4 + CPUMCTXCORE.edi] 555 mov [edx + CPUM .Guest.edi], eax567 mov [edx + CPUMCPU.Guest.edi], eax 556 568 mov eax, dword [esp + 4 + CPUMCTXCORE.es] 557 mov dword [edx + CPUM .Guest.es], eax569 mov dword [edx + CPUMCPU.Guest.es], eax 558 570 mov eax, dword [esp + 4 + CPUMCTXCORE.cs] 559 mov dword [edx + CPUM .Guest.cs], eax571 mov dword [edx + CPUMCPU.Guest.cs], eax 560 572 mov eax, dword [esp + 4 + CPUMCTXCORE.ss] 561 mov dword [edx + CPUM .Guest.ss], eax573 mov dword [edx + CPUMCPU.Guest.ss], eax 562 574 mov eax, dword [esp + 4 + CPUMCTXCORE.ds] 563 mov dword [edx + CPUM .Guest.ds], eax575 mov dword [edx + CPUMCPU.Guest.ds], eax 564 576 mov eax, dword [esp + 4 + CPUMCTXCORE.fs] 565 mov dword [edx + CPUM .Guest.fs], eax577 mov dword [edx + CPUMCPU.Guest.fs], eax 566 578 mov eax, dword [esp + 4 + CPUMCTXCORE.gs] 567 mov dword [edx + CPUM .Guest.gs], eax579 mov dword [edx + CPUMCPU.Guest.gs], eax 568 580 mov eax, [esp + 4 + CPUMCTXCORE.eflags] 569 mov dword [edx + CPUM .Guest.eflags], eax581 mov dword [edx + CPUMCPU.Guest.eflags], eax 570 582 mov eax, [esp + 4 + CPUMCTXCORE.eip] 571 mov dword [edx + CPUM .Guest.eip], eax583 mov dword [edx + CPUMCPU.Guest.eip], eax 572 584 pop eax 585 CPUM_FROM_CPUMCPU(edx) 573 586 574 587 add esp, CPUMCTXCORE_size ; skip CPUMCTXCORE structure … … 734 747 ;; 735 748 mov edi, eax ; save return code in EDI (careful with COM_DWORD_REG from here on!) 736 mov ecx, [edx + CPUM.Host.cr3] 749 CPUMCPU_FROM_CPUM(edx) 750 mov ecx, [edx + CPUMCPU.Host.cr3] 751 CPUM_FROM_CPUMCPU(edx) 737 752 FIXUP SWITCHER_FIX_INTER_CR3_GC, 1 738 753 mov eax, 0ffffffffh … … 803 818 FIXUP FIX_HC_CPUM_OFF, 1, 0 804 819 mov edx, 0ffffffffh 820 CPUMCPU_FROM_CPUM(edx) 805 821 ; activate host gdt and idt 806 lgdt [edx + CPUM .Host.gdtr]822 lgdt [edx + CPUMCPU.Host.gdtr] 807 823 DEBUG_CHAR('0') 808 lidt [edx + CPUM .Host.idtr]824 lidt [edx + CPUMCPU.Host.idtr] 809 825 DEBUG_CHAR('1') 810 826 ; Restore TSS selector; must mark it as not busy before using ltr (!) 811 827 %if 1 ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p) 812 movzx eax, word [edx + CPUM .Host.tr] ; eax <- TR828 movzx eax, word [edx + CPUMCPU.Host.tr] ; eax <- TR 813 829 and al, 0F8h ; mask away TI and RPL bits, get descriptor offset. 814 add eax, [edx + CPUM .Host.gdtr + 2] ; eax <- GDTR.address + descriptor offset.830 add eax, [edx + CPUMCPU.Host.gdtr + 2] ; eax <- GDTR.address + descriptor offset. 815 831 and dword [eax + 4], ~0200h ; clear busy flag (2nd type2 bit) 816 ltr word [edx + CPUM .Host.tr]832 ltr word [edx + CPUMCPU.Host.tr] 817 833 %else 818 movzx eax, word [edx + CPUM .Host.tr] ; eax <- TR834 movzx eax, word [edx + CPUMCPU.Host.tr] ; eax <- TR 819 835 and al, 0F8h ; mask away TI and RPL bits, get descriptor offset. 820 add eax, [edx + CPUM .Host.gdtr + 2] ; eax <- GDTR.address + descriptor offset.836 add eax, [edx + CPUMCPU.Host.gdtr + 2] ; eax <- GDTR.address + descriptor offset. 821 837 mov ecx, [eax + 4] ; ecx <- 2nd descriptor dword 822 838 mov ebx, ecx ; save orginal value 823 839 and ecx, ~0200h ; clear busy flag (2nd type2 bit) 824 840 mov [eax + 4], ecx ; not using xchg here is paranoia.. 825 ltr word [edx + CPUM .Host.tr]841 ltr word [edx + CPUMCPU.Host.tr] 826 842 xchg [eax + 4], ebx ; using xchg is paranoia too... 827 843 %endif 828 844 ; activate ldt 829 845 DEBUG_CHAR('2') 830 lldt [edx + CPUM .Host.ldtr]846 lldt [edx + CPUMCPU.Host.ldtr] 831 847 ; Restore segment registers 832 mov eax, [edx + CPUM .Host.ds]848 mov eax, [edx + CPUMCPU.Host.ds] 833 849 mov ds, eax 834 mov eax, [edx + CPUM .Host.es]850 mov eax, [edx + CPUMCPU.Host.es] 835 851 mov es, eax 836 mov eax, [edx + CPUM .Host.fs]852 mov eax, [edx + CPUMCPU.Host.fs] 837 853 mov fs, eax 838 mov eax, [edx + CPUM .Host.gs]854 mov eax, [edx + CPUMCPU.Host.gs] 839 855 mov gs, eax 840 856 ; restore stack 841 lss esp, [edx + CPUM .Host.esp]857 lss esp, [edx + CPUMCPU.Host.esp] 842 858 843 859 … … 845 861 ; restore MSR_IA32_SYSENTER_CS register. 846 862 mov ecx, MSR_IA32_SYSENTER_CS 847 mov eax, [edx + CPUM .Host.SysEnter.cs]848 mov ebx, [edx + CPUM .Host.SysEnter.cs + 4]863 mov eax, [edx + CPUMCPU.Host.SysEnter.cs] 864 mov ebx, [edx + CPUMCPU.Host.SysEnter.cs + 4] 849 865 xchg edx, ebx ; save/load edx 850 866 wrmsr ; MSR[ecx] <- edx:eax … … 859 875 ; Restore FPU if guest has used it. 860 876 ; Using fxrstor should ensure that we're not causing unwanted exception on the host. 861 mov esi, [edx + CPUM .fUseFlags] ; esi == use flags.877 mov esi, [edx + CPUMCPU.fUseFlags] ; esi == use flags. 862 878 test esi, CPUM_USED_FPU 863 879 jz near gth_fpu_no … … 867 883 868 884 FIXUP FIX_NO_FXSAVE_JMP, 0, gth_no_fxsave - NAME(Start) ; this will insert a jmp gth_no_fxsave if fxsave isn't supported. 869 fxsave [edx + CPUM .Guest.fpu]870 fxrstor [edx + CPUM .Host.fpu]885 fxsave [edx + CPUMCPU.Guest.fpu] 886 fxrstor [edx + CPUMCPU.Host.fpu] 871 887 jmp near gth_fpu_no 872 888 873 889 gth_no_fxsave: 874 fnsave [edx + CPUM .Guest.fpu]875 mov eax, [edx + CPUM .Host.fpu] ; control word890 fnsave [edx + CPUMCPU.Guest.fpu] 891 mov eax, [edx + CPUMCPU.Host.fpu] ; control word 876 892 not eax ; 1 means exception ignored (6 LS bits) 877 893 and eax, byte 03Fh ; 6 LS bits only 878 test eax, [edx + CPUM .Host.fpu + 4] ; status word894 test eax, [edx + CPUMCPU.Host.fpu + 4] ; status word 879 895 jz gth_no_exceptions_pending 880 896 881 897 ; technically incorrect, but we certainly don't want any exceptions now!! 882 and dword [edx + CPUM .Host.fpu + 4], ~03Fh898 and dword [edx + CPUMCPU.Host.fpu + 4], ~03Fh 883 899 884 900 gth_no_exceptions_pending: 885 frstor [edx + CPUM .Host.fpu]901 frstor [edx + CPUMCPU.Host.fpu] 886 902 jmp short gth_fpu_no 887 903 … … 892 908 ; Would've liked to have these highere up in case of crashes, but 893 909 ; the fpu stuff must be done before we restore cr0. 894 mov ecx, [edx + CPUM .Host.cr4]910 mov ecx, [edx + CPUMCPU.Host.cr4] 895 911 mov cr4, ecx 896 mov ecx, [edx + CPUM .Host.cr0]912 mov ecx, [edx + CPUMCPU.Host.cr0] 897 913 mov cr0, ecx 898 ;mov ecx, [edx + CPUM .Host.cr2] ; assumes this is waste of time.914 ;mov ecx, [edx + CPUMCPU.Host.cr2] ; assumes this is waste of time. 899 915 ;mov cr2, ecx 900 916 … … 908 924 ; restore general registers. 909 925 mov eax, edi ; restore return code. eax = return code !! 910 mov edi, [edx + CPUM .Host.edi]911 mov esi, [edx + CPUM .Host.esi]912 mov ebx, [edx + CPUM .Host.ebx]913 mov ebp, [edx + CPUM .Host.ebp]914 push dword [edx + CPUM .Host.eflags]926 mov edi, [edx + CPUMCPU.Host.edi] 927 mov esi, [edx + CPUMCPU.Host.esi] 928 mov ebx, [edx + CPUMCPU.Host.ebx] 929 mov ebp, [edx + CPUMCPU.Host.ebp] 930 push dword [edx + CPUMCPU.Host.eflags] 915 931 popfd 916 932 … … 930 946 jz short gth_debug_regs_dr7 931 947 DEBUG_S_CHAR('r') 932 mov eax, [edx + CPUM .Host.dr0]948 mov eax, [edx + CPUMCPU.Host.dr0] 933 949 mov dr0, eax 934 mov ebx, [edx + CPUM .Host.dr1]950 mov ebx, [edx + CPUMCPU.Host.dr1] 935 951 mov dr1, ebx 936 mov ecx, [edx + CPUM .Host.dr2]952 mov ecx, [edx + CPUMCPU.Host.dr2] 937 953 mov dr2, ecx 938 mov eax, [edx + CPUM .Host.dr3]954 mov eax, [edx + CPUMCPU.Host.dr3] 939 955 mov dr3, eax 940 956 gth_debug_regs_dr7: 941 mov ebx, [edx + CPUM .Host.dr6]957 mov ebx, [edx + CPUMCPU.Host.dr6] 942 958 mov dr6, ebx 943 mov ecx, [edx + CPUM .Host.dr7]959 mov ecx, [edx + CPUMCPU.Host.dr7] 944 960 mov dr7, ecx 945 961 jmp gth_debug_regs_no
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