Index: /trunk/src/VBox/VMM/PGMInternal.h
===================================================================
--- /trunk/src/VBox/VMM/PGMInternal.h	(revision 14144)
+++ /trunk/src/VBox/VMM/PGMInternal.h	(revision 14145)
@@ -3481,5 +3481,5 @@
  * @param   GCPtr       The address.
  */
-DECLINLINE(uint64_t) pgmGstGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
+DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
 {
     AssertGCPtr32(GCPtr);
@@ -3487,25 +3487,28 @@
 #ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
     PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
-    AssertReturn(pGuestPDPT, 0);
+    if (LIKELY(pGuestPDPT))
 #else
     PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePDPT);
 #endif
-    const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
-    if (pGuestPDPT->a[iPdPt].n.u1Present)
     {
-        const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
+        const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
+        if (pGuestPDPT->a[iPdPt].n.u1Present)
+        {
+            const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
 #ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
-        if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
-            return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD].u;
-#endif
-
-        /* cache is out-of-sync. */
-        PX86PDPAE pPD;
-        int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
-        if (RT_SUCCESS(rc))
-            return pPD->a[iPD].u;
-        AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
+            if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
+                return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
+#endif
+
+            /* cache is out-of-sync. */
+            PX86PDPAE pPD;
+            int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
+            if (RT_SUCCESS(rc))
+                return pPD->a[iPD];
+            AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt]));
+        }
     }
-    return 0;
+    X86PDEPAE ZeroPde = {0};
+    return ZeroPde;
 }
 
@@ -3665,6 +3668,7 @@
  * @param   pPdpe       Page directory pointer table entry (out)
  */
-DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
-{
+DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
+{
+    X86PDEPAE       ZeroPde = {0};
     PX86PML4        pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
     const unsigned  iPml4  = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
@@ -3674,5 +3678,5 @@
         PCX86PDPT   pPdptTemp;
         int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
-        AssertRCReturn(rc, 0);
+        AssertRCReturn(rc, ZeroPde);
 
         const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
@@ -3682,11 +3686,12 @@
             PCX86PDPAE pPD;
             rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
-            AssertRCReturn(rc, 0);
+            AssertRCReturn(rc, ZeroPde);
 
             const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
-            return pPD->a[iPD].u;
+            return pPD->a[iPD];
         }
     }
-    return 0;
+
+    return ZeroPde;
 }
 
@@ -3700,6 +3705,7 @@
  * @param   GCPtr       The address.
  */
-DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCPTR64 GCPtr)
-{
+DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGM pPGM, RTGCPTR64 GCPtr)
+{
+    X86PDEPAE       ZeroPde = {0};
     PCX86PML4       pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
     const unsigned  iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
@@ -3708,5 +3714,5 @@
         PCX86PDPT   pPdptTemp;
         int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
-        AssertRCReturn(rc, 0);
+        AssertRCReturn(rc, ZeroPde);
 
         const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
@@ -3715,11 +3721,11 @@
             PCX86PDPAE pPD;
             rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
-            AssertRCReturn(rc, 0);
+            AssertRCReturn(rc, ZeroPde);
 
             const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
-            return pPD->a[iPD].u;
+            return pPD->a[iPD];
         }
     }
-    return 0;
+    return ZeroPde;
 }
 
Index: /trunk/src/VBox/VMM/PGMMap.cpp
===================================================================
--- /trunk/src/VBox/VMM/PGMMap.cpp	(revision 14144)
+++ /trunk/src/VBox/VMM/PGMMap.cpp	(revision 14145)
@@ -1103,5 +1103,4 @@
         for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
         {
-            X86PDEPAE Pde;
             RTGCPTR   GCPtr = pCur->GCPtr;
 
@@ -1109,5 +1108,5 @@
             while (iPT-- > 0)
             {
-                Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
+                X86PDEPAE Pde = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
 
                 if (   Pde.n.u1Present
Index: /trunk/src/VBox/VMM/VMMAll/PGMAllGst.h
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/PGMAllGst.h	(revision 14144)
+++ /trunk/src/VBox/VMM/VMMAll/PGMAllGst.h	(revision 14145)
@@ -182,19 +182,15 @@
 
 #elif PGM_GST_TYPE == PGM_TYPE_PAE
-    X86PDEPAE   Pde;
+    /* pgmGstGetPaePDE will return 0 if the PDPTE is marked as not present.
+     * All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx). */
+    X86PDEPAE   Pde = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
     bool        fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
-
-    /* pgmGstGetPaePDE will return 0 if the PDPTE is marked as not present
-     * All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
-     */
-    Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
 
 #elif PGM_GST_TYPE == PGM_TYPE_AMD64
     PX86PML4E   pPml4e;
     X86PDPE     Pdpe;
-    X86PDEPAE   Pde;
+    X86PDEPAE   Pde = pgmGstGetLongModePDEEx(&pVM->pgm.s, GCPtr, &pPml4e, &Pdpe);
     bool        fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
 
-    Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr, &pPml4e, &Pdpe);
     Assert(pPml4e);
     if (!(pPml4e->n.u1Present & Pdpe.n.u1Present))
@@ -402,9 +398,7 @@
     X86PDE    Pde = pgmGstGet32bitPDE(&pVM->pgm.s, GCPtr);
 # elif PGM_GST_TYPE == PGM_TYPE_PAE
-    X86PDEPAE Pde;
-    Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
+    X86PDEPAE Pde = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
 # elif PGM_GST_TYPE == PGM_TYPE_AMD64
-    X86PDEPAE Pde;
-    Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr);
+    X86PDEPAE Pde = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr);
 # endif
 
@@ -840,9 +834,7 @@
         X86PDE      Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
 #elif PGM_GST_TYPE == PGM_TYPE_PAE
-        X86PDEPAE   Pde;
-        Pde.u = pgmGstGetPaePDE(&pState->pVM->pgm.s, GCPtr);
+        X86PDEPAE   Pde = pgmGstGetPaePDE(&pState->pVM->pgm.s, GCPtr);
 #elif PGM_GST_TYPE == PGM_TYPE_AMD64
-        X86PDEPAE   Pde;
-        Pde.u = pgmGstGetLongModePDE(&pState->pVM->pgm.s, GCPtr);
+        X86PDEPAE   Pde = pgmGstGetLongModePDE(&pState->pVM->pgm.s, GCPtr);
 #endif
         if (Pde.n.u1Present)
