VirtualBox

Changeset 14301 in vbox


Ignore:
Timestamp:
Nov 18, 2008 1:31:42 PM (16 years ago)
Author:
vboxsync
Message:

Synced some (inactive) new paging code.

Location:
trunk
Files:
7 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/pgm.h

    r14115 r14301  
    535535VMMR3DECL(bool)     PGMR3MapHasConflicts(PVM pVM, uint64_t cr3, bool fRawR0);
    536536VMMR3DECL(int)      PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
     537VMMR3DECL(int)      PGMR3MapActivate(PVM pVM);
     538VMMR3DECL(int)      PGMR3MapDeactivate(PVM pVM);
     539
    537540VMMR3DECL(int)      PGMR3HandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
    538541                                                 PFNPGMR3PHYSHANDLER pfnHandlerR3, void *pvUserR3,

  • trunk/src/VBox/VMM/PGM.cpp

    r14260 r14301  
    14131413     * As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
    14141414     */
     1415#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    14151416    pVM->pgm.s.pShw32BitPdR3    = (PX86PD)MMR3PageAllocLow(pVM);
    1416 #ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
     1417# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
    14171418    pVM->pgm.s.pShw32BitPdR0    = (uintptr_t)pVM->pgm.s.pShw32BitPdR3;
    1418 #endif
     1419# endif
    14191420    pVM->pgm.s.apShwPaePDsR3[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
    14201421    pVM->pgm.s.apShwPaePDsR3[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
    … …  
    14241425    pVM->pgm.s.apShwPaePDsR3[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
    14251426    AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[3]);
    1426 #ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
     1427# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
    14271428    pVM->pgm.s.apShwPaePDsR0[0] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[0];
    14281429    pVM->pgm.s.apShwPaePDsR0[1] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[1];
    14291430    pVM->pgm.s.apShwPaePDsR0[2] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[2];
    14301431    pVM->pgm.s.apShwPaePDsR0[3] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[3];
    1431 #endif
     1432# endif
    14321433    pVM->pgm.s.pShwPaePdptR3 = (PX86PDPT)MMR3PageAllocLow(pVM);
    1433 #ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
     1434# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
    14341435    pVM->pgm.s.pShwPaePdptR0 = (uintptr_t)pVM->pgm.s.pShwPaePdptR3;
    1435 #endif
     1436# endif
     1437#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
    14361438    pVM->pgm.s.pShwNestedRootR3 = MMR3PageAllocLow(pVM);
    14371439#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
    … …  
    14391441#endif
    14401442
     1443#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     1444    if (!pVM->pgm.s.pShwNestedRootR3)
     1445#else
    14411446    if (    !pVM->pgm.s.pShw32BitPdR3
    14421447        ||  !pVM->pgm.s.apShwPaePDsR3[0]
    … …  
    14461451        ||  !pVM->pgm.s.pShwPaePdptR3
    14471452        ||  !pVM->pgm.s.pShwNestedRootR3)
     1453#endif
    14481454    {
    14491455        AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
    … …  
    14521458
    14531459    /* get physical addresses. */
     1460#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    14541461    pVM->pgm.s.HCPhysShw32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pShw32BitPdR3);
    14551462    Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhysShw32BitPD) == pVM->pgm.s.pShw32BitPdR3);
    … …  
    14591466    pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[3]);
    14601467    pVM->pgm.s.HCPhysShwPaePdpt = MMPage2Phys(pVM, pVM->pgm.s.pShwPaePdptR3);
     1468#endif
    14611469    pVM->pgm.s.HCPhysShwNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pShwNestedRootR3);
    14621470
    … …  
    14641472     * Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
    14651473     */
     1474#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    14661475    ASMMemZero32(pVM->pgm.s.pShw32BitPdR3, PAGE_SIZE);
    14671476    ASMMemZero32(pVM->pgm.s.pShwPaePdptR3, PAGE_SIZE);
     1477#endif
    14681478    ASMMemZero32(pVM->pgm.s.pShwNestedRootR3, PAGE_SIZE);
     1479#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    14691480    for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3); i++)
    14701481    {
    … …  
    14751486
    14761487    CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhysShw32BitPD);
     1488#endif
    14771489
    14781490    /*
    … …  
    15151527        LogFlow(("pgmR3InitPaging: returns successfully\n"));
    15161528#if HC_ARCH_BITS == 64
     1529# ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    15171530        LogRel(("Debug: HCPhysShw32BitPD=%RHp aHCPhysPaePDs={%RHp,%RHp,%RHp,%RHp} HCPhysShwPaePdpt=%RHp HCPhysShwPaePml4=%RHp\n",
    15181531                pVM->pgm.s.HCPhysShw32BitPD,
    … …  
    15201533                pVM->pgm.s.HCPhysShwPaePdpt,
    15211534                pVM->pgm.s.HCPhysShwPaePml4));
     1535# endif
    15221536        LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
    15231537                pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
    … …  
    17721786{
    17731787    RTGCPTR GCPtr;
     1788    int     rc;
     1789
     1790#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    17741791    /*
    17751792     * Reserve space for mapping the paging pages into guest context.
    17761793     */
    1777     int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3) + 1 + 2 + 2), "Paging", &GCPtr);
     1794    rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3) + 1 + 2 + 2), "Paging", &GCPtr);
    17781795    AssertRCReturn(rc, rc);
    17791796    pVM->pgm.s.pShw32BitPdRC = GCPtr;
    17801797    MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
     1798#endif
    17811799
    17821800    /*
    … …  
    18111829VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
    18121830{
     1831    int rc;
     1832
     1833#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    18131834    /*
    18141835     * Map the paging pages into the guest context.
    … …  
    18171838    AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
    18181839
    1819     int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysShw32BitPD, PAGE_SIZE, 0);
     1840    rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysShw32BitPD, PAGE_SIZE, 0);
    18201841    AssertRCReturn(rc, rc);
    18211842    pVM->pgm.s.pShw32BitPdRC = GCPtr;
    … …  
    18411862    GCPtr += PAGE_SIZE;
    18421863    GCPtr += PAGE_SIZE; /* reserved page */
    1843 
     1864#endif
    18441865
    18451866    /*
    … …  
    19051926    /** @todo move this into shadow and guest specific relocation functions. */
    19061927    AssertMsg(pVM->pgm.s.pShw32BitPdR3, ("Init order, no relocation before paging is initialized!\n"));
     1928#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    19071929    pVM->pgm.s.pShw32BitPdRC += offDelta;
     1930#endif
    19081931    pVM->pgm.s.pGst32BitPdRC += offDelta;
    19091932    AssertCompile(RT_ELEMENTS(pVM->pgm.s.apShwPaePDsRC) == RT_ELEMENTS(pVM->pgm.s.apGstPaePDsRC));
    19101933    for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsRC); i++)
    19111934    {
     1935#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    19121936        pVM->pgm.s.apShwPaePDsRC[i] += offDelta;
     1937#endif
    19131938        pVM->pgm.s.apGstPaePDsRC[i] += offDelta;
    19141939    }
    19151940    pVM->pgm.s.pGstPaePdptRC += offDelta;
     1941#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    19161942    pVM->pgm.s.pShwPaePdptRC += offDelta;
     1943#endif
    19171944
    19181945    pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
    … …  
    29652992    pVM->pgm.s.pfnR3GstModifyPage           = pModeData->pfnR3GstModifyPage;
    29662993    pVM->pgm.s.pfnR3GstGetPDE               = pModeData->pfnR3GstGetPDE;
     2994#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    29672995    pVM->pgm.s.pfnR3GstMonitorCR3           = pModeData->pfnR3GstMonitorCR3;
    29682996    pVM->pgm.s.pfnR3GstUnmonitorCR3         = pModeData->pfnR3GstUnmonitorCR3;
     2997#endif
    29692998    pVM->pgm.s.pfnR3GstMapCR3               = pModeData->pfnR3GstMapCR3;
    29702999    pVM->pgm.s.pfnR3GstUnmapCR3             = pModeData->pfnR3GstUnmapCR3;
     3000#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    29713001    pVM->pgm.s.pfnR3GstWriteHandlerCR3      = pModeData->pfnR3GstWriteHandlerCR3;
    29723002    pVM->pgm.s.pszR3GstWriteHandlerCR3      = pModeData->pszR3GstWriteHandlerCR3;
    29733003    pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3   = pModeData->pfnR3GstPAEWriteHandlerCR3;
    29743004    pVM->pgm.s.pszR3GstPAEWriteHandlerCR3   = pModeData->pszR3GstPAEWriteHandlerCR3;
    2975 
     3005#endif
    29763006    pVM->pgm.s.pfnRCGstGetPage              = pModeData->pfnRCGstGetPage;
    29773007    pVM->pgm.s.pfnRCGstModifyPage           = pModeData->pfnRCGstModifyPage;
    29783008    pVM->pgm.s.pfnRCGstGetPDE               = pModeData->pfnRCGstGetPDE;
     3009#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    29793010    pVM->pgm.s.pfnRCGstMonitorCR3           = pModeData->pfnRCGstMonitorCR3;
    29803011    pVM->pgm.s.pfnRCGstUnmonitorCR3         = pModeData->pfnRCGstUnmonitorCR3;
     3012#endif
    29813013    pVM->pgm.s.pfnRCGstMapCR3               = pModeData->pfnRCGstMapCR3;
    29823014    pVM->pgm.s.pfnRCGstUnmapCR3             = pModeData->pfnRCGstUnmapCR3;
     3015#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    29833016    pVM->pgm.s.pfnRCGstWriteHandlerCR3      = pModeData->pfnRCGstWriteHandlerCR3;
    29843017    pVM->pgm.s.pfnRCGstPAEWriteHandlerCR3   = pModeData->pfnRCGstPAEWriteHandlerCR3;
    2985 
     3018#endif
    29863019    pVM->pgm.s.pfnR0GstGetPage              = pModeData->pfnR0GstGetPage;
    29873020    pVM->pgm.s.pfnR0GstModifyPage           = pModeData->pfnR0GstModifyPage;
    29883021    pVM->pgm.s.pfnR0GstGetPDE               = pModeData->pfnR0GstGetPDE;
     3022#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    29893023    pVM->pgm.s.pfnR0GstMonitorCR3           = pModeData->pfnR0GstMonitorCR3;
    29903024    pVM->pgm.s.pfnR0GstUnmonitorCR3         = pModeData->pfnR0GstUnmonitorCR3;
     3025#endif
    29913026    pVM->pgm.s.pfnR0GstMapCR3               = pModeData->pfnR0GstMapCR3;
    29923027    pVM->pgm.s.pfnR0GstUnmapCR3             = pModeData->pfnR0GstUnmapCR3;
     3028#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    29933029    pVM->pgm.s.pfnR0GstWriteHandlerCR3      = pModeData->pfnR0GstWriteHandlerCR3;
    29943030    pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3   = pModeData->pfnR0GstPAEWriteHandlerCR3;
    2995 
     3031#endif
    29963032
    29973033    /* both */

  • trunk/src/VBox/VMM/PGMGst.h

    r14154 r14301  
    110110PGM_GST_DECL(int, Exit)(PVM pVM);
    111111
     112#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    112113static DECLCALLBACK(int) pgmR3Gst32BitWriteHandlerCR3(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
    113114static DECLCALLBACK(int) pgmR3GstPAEWriteHandlerCR3(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
    114 #if 0
    115115static DECLCALLBACK(int) pgmR3GstPAEWriteHandlerPD(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
    116116#endif
    … …  
    122122PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
    123123PGM_GST_DECL(int, UnmapCR3)(PVM pVM);
     124#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    124125PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
    125126PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM);
     127#endif
    126128__END_DECLS
    127129
    … …  
    148150    pModeData->pfnR3GstMapCR3             = PGM_GST_NAME(MapCR3);
    149151    pModeData->pfnR3GstUnmapCR3           = PGM_GST_NAME(UnmapCR3);
     152#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    150153    pModeData->pfnR3GstMonitorCR3         = PGM_GST_NAME(MonitorCR3);
    151154    pModeData->pfnR3GstUnmonitorCR3       = PGM_GST_NAME(UnmonitorCR3);
    152 
    153 #if PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE
     155#endif
     156
     157#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
     158# if PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE
    154159    pModeData->pfnR3GstWriteHandlerCR3    = PGM_GST_NAME(WriteHandlerCR3);
    155160    pModeData->pszR3GstWriteHandlerCR3    = "Guest CR3 Write access handler";
    156161    pModeData->pfnR3GstPAEWriteHandlerCR3 = PGM_GST_NAME(WriteHandlerCR3);
    157162    pModeData->pszR3GstPAEWriteHandlerCR3 = "Guest CR3 Write access handler (PAE)";
    158 #else
     163# else
    159164    pModeData->pfnR3GstWriteHandlerCR3    = NULL;
    160165    pModeData->pszR3GstWriteHandlerCR3    = NULL;
    161166    pModeData->pfnR3GstPAEWriteHandlerCR3 = NULL;
    162167    pModeData->pszR3GstPAEWriteHandlerCR3 = NULL;
     168# endif
    163169#endif
    164170
    … …  
    175181        rc = PDMR3LdrGetSymbolRC(pVM, NULL,       PGM_GST_NAME_RC_STR(GetPDE),           &pModeData->pfnRCGstGetPDE);
    176182        AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_RC_STR(GetPDE), rc), rc);
     183# ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    177184        rc = PDMR3LdrGetSymbolRC(pVM, NULL,       PGM_GST_NAME_RC_STR(MonitorCR3),       &pModeData->pfnRCGstMonitorCR3);
    178185        AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_RC_STR(MonitorCR3), rc), rc);
    179186        rc = PDMR3LdrGetSymbolRC(pVM, NULL,       PGM_GST_NAME_RC_STR(UnmonitorCR3),     &pModeData->pfnRCGstUnmonitorCR3);
    180187        AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_RC_STR(UnmonitorCR3), rc), rc);
     188# endif
    181189        rc = PDMR3LdrGetSymbolRC(pVM, NULL,       PGM_GST_NAME_RC_STR(MapCR3),           &pModeData->pfnRCGstMapCR3);
    182190        AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_RC_STR(MapCR3), rc), rc);
    183191        rc = PDMR3LdrGetSymbolRC(pVM, NULL,       PGM_GST_NAME_RC_STR(UnmapCR3),         &pModeData->pfnRCGstUnmapCR3);
    184192        AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_RC_STR(UnmapCR3), rc), rc);
    185 # if PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE
     193# ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
     194#  if PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE
    186195        rc = PDMR3LdrGetSymbolRC(pVM, NULL,       PGM_GST_NAME_RC_STR(WriteHandlerCR3),  &pModeData->pfnRCGstWriteHandlerCR3);
    187196        AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_RC_STR(WriteHandlerCR3), rc), rc);
    188197        rc = PDMR3LdrGetSymbolRC(pVM, NULL,       PGM_GST_NAME_RC_STR(WriteHandlerCR3),  &pModeData->pfnRCGstPAEWriteHandlerCR3);
    189198        AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_RC_STR(WriteHandlerCR3), rc), rc);
     199#  endif
    190200# endif
    191201#endif /* Not AMD64 shadow paging. */
    … …  
    198208        rc = PDMR3LdrGetSymbolR0(pVM, NULL,       PGM_GST_NAME_R0_STR(GetPDE),           &pModeData->pfnR0GstGetPDE);
    199209        AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_R0_STR(GetPDE), rc), rc);
     210#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    200211        rc = PDMR3LdrGetSymbolR0(pVM, NULL,       PGM_GST_NAME_R0_STR(MonitorCR3),       &pModeData->pfnR0GstMonitorCR3);
    201212        AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_R0_STR(MonitorCR3), rc), rc);
    202213        rc = PDMR3LdrGetSymbolR0(pVM, NULL,       PGM_GST_NAME_R0_STR(UnmonitorCR3),     &pModeData->pfnR0GstUnmonitorCR3);
    203214        AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_R0_STR(UnmonitorCR3), rc), rc);
     215#endif
    204216        rc = PDMR3LdrGetSymbolR0(pVM, NULL,       PGM_GST_NAME_R0_STR(MapCR3),           &pModeData->pfnR0GstMapCR3);
    205217        AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_R0_STR(MapCR3), rc), rc);
    206218        rc = PDMR3LdrGetSymbolR0(pVM, NULL,       PGM_GST_NAME_R0_STR(UnmapCR3),         &pModeData->pfnR0GstUnmapCR3);
    207219        AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_R0_STR(UnmapCR3), rc), rc);
    208 #if PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE
     220#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
     221# if PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE
    209222        rc = PDMR3LdrGetSymbolR0(pVM, NULL,       PGM_GST_NAME_R0_STR(WriteHandlerCR3),  &pModeData->pfnR0GstWriteHandlerCR3);
    210223        AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_R0_STR(WriteHandlerCR3), rc), rc);
    211224        rc = PDMR3LdrGetSymbolR0(pVM, NULL,       PGM_GST_NAME_R0_STR(WriteHandlerCR3),  &pModeData->pfnR0GstPAEWriteHandlerCR3);
    212225        AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_GST_NAME_R0_STR(WriteHandlerCR3), rc), rc);
     226# endif
    213227#endif
    214228    }
    … …  
    231245     */
    232246    int rc = PGM_GST_NAME(MapCR3)(pVM, GCPhysCR3);
     247#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    233248    if (RT_SUCCESS(rc) && !pVM->pgm.s.fMappingsFixed)
    234249        rc = PGM_GST_NAME(MonitorCR3)(pVM, GCPhysCR3);
     250#endif
    235251    return rc;
    236252}
    … …  
    259275PGM_GST_DECL(int, Exit)(PVM pVM)
    260276{
    261     int rc = PGM_GST_NAME(UnmonitorCR3)(pVM);
     277    int rc;
     278
     279#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
     280    rc = PGM_GST_NAME(UnmonitorCR3)(pVM);
    262281    if (RT_SUCCESS(rc))
     282#endif
    263283        rc = PGM_GST_NAME(UnmapCR3)(pVM);
    264284    return rc;

  • trunk/src/VBox/VMM/PGMInternal.h

    r14244 r14301  
    13421342/** Page directory (32-bit root). */
    13431343#define PGMPOOL_IDX_PD                  1
     1344#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     1345/** Page directory (32-bit root). */
     1346#define PGMPOOL_IDX_PD                  1
     1347/** Page Directory Pointer Table (PAE root). */
     1348#define PGMPOOL_IDX_PDPT                2
     1349/** AMD64 CR3 level index.*/
     1350#define PGMPOOL_IDX_AMD64_CR3           3
     1351/** Nested paging root.*/
     1352#define PGMPOOL_IDX_NESTED_ROOT         4
     1353/** The first normal index. */
     1354#define PGMPOOL_IDX_FIRST               5
     1355#else
    13441356/** The extended PAE page directory (2048 entries, works as root currently). */
    13451357#define PGMPOOL_IDX_PAE_PD              2
    … …  
    13601372/** The first normal index. */
    13611373#define PGMPOOL_IDX_FIRST               10
     1374#endif
    13621375/** The last valid index. (inclusive, 14 bits) */
    13631376#define PGMPOOL_IDX_LAST                0x3fff
    … …  
    14291442    PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
    14301443
     1444    /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
     1445    PGMPOOLKIND_32BIT_PD,
     1446    /** Shw: 32-bit page directory. Gst: real mode. */
     1447    PGMPOOLKIND_32BIT_PD_PHYS_REAL,
     1448    /** Shw: 32-bit page directory. Gst: protected mode without paging. */
     1449    PGMPOOLKIND_32BIT_PD_PHYS_PROT,
    14311450    /** Shw: PAE page directory;    Gst: 32-bit page directory. */
    14321451    PGMPOOLKIND_PAE_PD_FOR_32BIT_PD,
    14331452    /** Shw: PAE page directory;    Gst: PAE page directory. */
    14341453    PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
     1454    /** Shw: PAE page directory;    Gst: real mode. */
     1455    PGMPOOLKIND_PAE_PD_PHYS_REAL,
     1456    /** Shw: PAE page directory;    Gst: protected mode without paging. */
     1457    PGMPOOLKIND_PAE_PD_PHYS_PROT,
     1458
     1459    /** Shw: PAE page directory pointer table (legacy, 4 entries);  Gst 32 bits paging. */
     1460    PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
     1461    /** Shw: PAE page directory pointer table (legacy, 4 entries);  Gst PAE PDPT. */
     1462    PGMPOOLKIND_PAE_PDPT,
    14351463
    14361464    /** Shw: 64-bit page directory pointer table;   Gst: 64-bit page directory pointer table. */
    … …  
    14531481    PGMPOOLKIND_EPT_PT_FOR_PHYS,
    14541482
     1483#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    14551484    /** Shw: Root 32-bit page directory. */
    14561485    PGMPOOLKIND_ROOT_32BIT_PD,
    … …  
    14591488    /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
    14601489    PGMPOOLKIND_ROOT_PDPT,
     1490#endif
    14611491    /** Shw: Root Nested paging table. */
    14621492    PGMPOOLKIND_ROOT_NESTED,
    … …  
    17411771# define PGMPOOL_PAGE_2_PTR(pVM, pPage)    pgmPoolMapPage((pVM), (pPage))
    17421772#else
    1743 # define PGMPOOL_PAGE_2_PTR(pVM, pPage)    ((pPage)->pvPageR3)
     1773 inline R3R0PTRTYPE(void *) PGMPOOL_PAGE_2_PTR(PVM pVM, PPGMPOOLPAGE pPage)
     1774 {
     1775     Assert(pPage->pvPageR3);
     1776     return pPage->pvPageR3;
     1777 }
    17441778#endif
    17451779
    … …  
    19151949    DECLR3CALLBACKMEMBER(int,       pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
    19161950    DECLR3CALLBACKMEMBER(int,       pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
     1951#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    19171952    DECLR3CALLBACKMEMBER(int,       pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
    19181953    DECLR3CALLBACKMEMBER(int,       pfnR3GstUnmonitorCR3,(PVM pVM));
     1954#endif
    19191955    DECLR3CALLBACKMEMBER(int,       pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
    19201956    DECLR3CALLBACKMEMBER(int,       pfnR3GstUnmapCR3,(PVM pVM));
     1957#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    19211958    R3PTRTYPE(PFNPGMR3PHYSHANDLER)  pfnR3GstWriteHandlerCR3;
    19221959    R3PTRTYPE(const char *)         pszR3GstWriteHandlerCR3;
    19231960    R3PTRTYPE(PFNPGMR3PHYSHANDLER)  pfnR3GstPAEWriteHandlerCR3;
    19241961    R3PTRTYPE(const char *)         pszR3GstPAEWriteHandlerCR3;
    1925 
     1962#endif
    19261963    DECLRCCALLBACKMEMBER(int,       pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
    19271964    DECLRCCALLBACKMEMBER(int,       pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
    19281965    DECLRCCALLBACKMEMBER(int,       pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
     1966#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    19291967    DECLRCCALLBACKMEMBER(int,       pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
    19301968    DECLRCCALLBACKMEMBER(int,       pfnRCGstUnmonitorCR3,(PVM pVM));
     1969#endif
    19311970    DECLRCCALLBACKMEMBER(int,       pfnRCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
    19321971    DECLRCCALLBACKMEMBER(int,       pfnRCGstUnmapCR3,(PVM pVM));
     1972#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    19331973    RCPTRTYPE(PFNPGMRCPHYSHANDLER)  pfnRCGstWriteHandlerCR3;
    19341974    RCPTRTYPE(PFNPGMRCPHYSHANDLER)  pfnRCGstPAEWriteHandlerCR3;
    1935 
     1975#endif
    19361976    DECLR0CALLBACKMEMBER(int,       pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
    19371977    DECLR0CALLBACKMEMBER(int,       pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
    19381978    DECLR0CALLBACKMEMBER(int,       pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
     1979#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    19391980    DECLR0CALLBACKMEMBER(int,       pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
    19401981    DECLR0CALLBACKMEMBER(int,       pfnR0GstUnmonitorCR3,(PVM pVM));
     1982#endif
    19411983    DECLR0CALLBACKMEMBER(int,       pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
    19421984    DECLR0CALLBACKMEMBER(int,       pfnR0GstUnmapCR3,(PVM pVM));
     1985#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    19431986    R0PTRTYPE(PFNPGMRCPHYSHANDLER)  pfnR0GstWriteHandlerCR3;
    19441987    R0PTRTYPE(PFNPGMRCPHYSHANDLER)  pfnR0GstPAEWriteHandlerCR3;
     1988#endif
    19451989    /** @} */
    19461990
    … …  
    20862130    /** @name 32-bit Shadow Paging
    20872131     * @{ */
     2132#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     2133    /** The Physical Address (HC) of the current active shadow CR3. */
     2134    RTHCPHYS                        HCPhysShwCR3;
     2135    /** Pointer to the page of the current active CR3 - R3 Ptr. */
     2136    R3PTRTYPE(PPGMPOOLPAGE)         pShwPageCR3R3;
     2137    /** Pointer to the page of the current active CR3 - R0 Ptr. */
     2138    R0PTRTYPE(PPGMPOOLPAGE)         pShwPageCR3R0;
     2139    /** Pointer to the page of the current active CR3 - RC Ptr. */
     2140    RCPTRTYPE(PPGMPOOLPAGE)         pShwPageCR3RC;
     2141# if HC_ARCH_BITS == 64
     2142    RTRCPTR                         alignment6; /**< structure size alignment. */
     2143# endif
     2144#else
    20882145    /** The 32-Bit PD - R3 Ptr. */
    20892146    R3PTRTYPE(PX86PD)               pShw32BitPdR3;
    … …  
    20922149    /** The 32-Bit PD - RC Ptr. */
    20932150    RCPTRTYPE(PX86PD)               pShw32BitPdRC;
    2094 #if HC_ARCH_BITS == 64
     2151# if HC_ARCH_BITS == 64
    20952152    uint32_t                        u32Padding1; /**< alignment padding. */
    2096 #endif
     2153# endif
    20972154    /** The Physical Address (HC) of the 32-Bit PD. */
    20982155    RTHCPHYS                        HCPhysShw32BitPD;
    … …  
    21052162     * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
    21062163    R3PTRTYPE(PX86PDPAE)            apShwPaePDsR3[4];
    2107 #ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
     2164# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
    21082165    /** The four PDs for the low 4GB - R0 Ptr.
    21092166     * Same kind of mapping as apHCPaePDs. */
    21102167    R0PTRTYPE(PX86PDPAE)            apShwPaePDsR0[4];
    2111 #endif
     2168# endif
    21122169    /** The four PDs for the low 4GB - RC Ptr.
    21132170     * Same kind of mapping as apHCPaePDs. */
    … …  
    21252182    RCPTRTYPE(PX86PDPT)             pShwPaePdptRC;
    21262183    /** @} */
    2127 #if HC_ARCH_BITS == 64
     2184# if HC_ARCH_BITS == 64
    21282185    RTRCPTR                         alignment5; /**< structure size alignment. */
    2129 #endif
     2186# endif
    21302187
    21312188    /** @name AMD64 Shadow Paging
    … …  
    21342191    /** The Page Map Level 4 table - R3 Ptr. */
    21352192    R3PTRTYPE(PX86PML4)             pShwPaePml4R3;
    2136 #ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
     2193# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
    21372194    /** The Page Map Level 4 table - R0 Ptr. */
    21382195    R0PTRTYPE(PX86PML4)             pShwPaePml4R0;
    2139 #endif
     2196# endif
    21402197    /** The Physical Address (HC) of the Page Map Level 4 table. */
    21412198    RTHCPHYS                        HCPhysShwPaePml4;
    … …  
    21502207    /** Root table; format depends on the host paging mode (AMD-V) or EPT - R3 pointer. */
    21512208    RTR3PTR                         pShwNestedRootR3;
    2152 #ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
     2209# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
    21532210    /** Root table; format depends on the host paging mode (AMD-V) or EPT - R0 pointer. */
    21542211    RTR0PTR                         pShwNestedRootR0;
    2155 #endif
     2212# endif
    21562213    /** The Physical Address (HC) of the nested paging root. */
    21572214    RTHCPHYS                        HCPhysShwNestedRoot;
     2215#endif
    21582216    /** @}  */
    21592217
    … …  
    21822240    DECLR3CALLBACKMEMBER(int,       pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
    21832241    DECLR3CALLBACKMEMBER(int,       pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
     2242#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    21842243    DECLR3CALLBACKMEMBER(int,       pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
    21852244    DECLR3CALLBACKMEMBER(int,       pfnR3GstUnmonitorCR3,(PVM pVM));
     2245#endif
    21862246    DECLR3CALLBACKMEMBER(int,       pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
    21872247    DECLR3CALLBACKMEMBER(int,       pfnR3GstUnmapCR3,(PVM pVM));
     2248#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    21882249    R3PTRTYPE(PFNPGMR3PHYSHANDLER)  pfnR3GstWriteHandlerCR3;
    21892250    R3PTRTYPE(const char *)         pszR3GstWriteHandlerCR3;
    21902251    R3PTRTYPE(PFNPGMR3PHYSHANDLER)  pfnR3GstPAEWriteHandlerCR3;
    21912252    R3PTRTYPE(const char *)         pszR3GstPAEWriteHandlerCR3;
    2192 
     2253#endif
    21932254    DECLRCCALLBACKMEMBER(int,       pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
    21942255    DECLRCCALLBACKMEMBER(int,       pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
    21952256    DECLRCCALLBACKMEMBER(int,       pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
     2257#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    21962258    DECLRCCALLBACKMEMBER(int,       pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
    21972259    DECLRCCALLBACKMEMBER(int,       pfnRCGstUnmonitorCR3,(PVM pVM));
     2260#endif
    21982261    DECLRCCALLBACKMEMBER(int,       pfnRCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
    21992262    DECLRCCALLBACKMEMBER(int,       pfnRCGstUnmapCR3,(PVM pVM));
     2263#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    22002264    RCPTRTYPE(PFNPGMRCPHYSHANDLER)  pfnRCGstWriteHandlerCR3;
    22012265    RCPTRTYPE(PFNPGMRCPHYSHANDLER)  pfnRCGstPAEWriteHandlerCR3;
     2266#endif
    22022267#if HC_ARCH_BITS == 64
    22032268    RTRCPTR                         alignment3; /**< structure size alignment. */
    … …  
    22072272    DECLR0CALLBACKMEMBER(int,       pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
    22082273    DECLR0CALLBACKMEMBER(int,       pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
     2274#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    22092275    DECLR0CALLBACKMEMBER(int,       pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
    22102276    DECLR0CALLBACKMEMBER(int,       pfnR0GstUnmonitorCR3,(PVM pVM));
     2277#endif
    22112278    DECLR0CALLBACKMEMBER(int,       pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
    22122279    DECLR0CALLBACKMEMBER(int,       pfnR0GstUnmapCR3,(PVM pVM));
     2280#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    22132281    R0PTRTYPE(PFNPGMRCPHYSHANDLER)  pfnR0GstWriteHandlerCR3;
    22142282    R0PTRTYPE(PFNPGMRCPHYSHANDLER)  pfnR0GstPAEWriteHandlerCR3;
     2283#endif
    22152284    /** @} */
    22162285
    … …  
    38573926DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGM pPGM)
    38583927{
    3859 #ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
     3928#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     3929    return (PX86PD)PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPGM->CTX_SUFF(pShwPageCR3));
     3930#else
     3931# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
    38603932    PX86PD          pShwPd;
    38613933    Assert(pPGM->HCPhysShw32BitPD != 0 && pPGM->HCPhysShw32BitPD != NIL_RTHCPHYS);
    … …  
    38633935    AssertRCReturn(rc, NULL);
    38643936    return pShwPd;
    3865 #else
     3937# else
    38663938    return pPGM->CTX_SUFF(pShw32BitPd);
     3939# endif
    38673940#endif
    38683941}
    … …  
    38783951DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGM pPGM, RTGCPTR GCPtr)
    38793952{
    3880     const unsigned  iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
    3881 #ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
    3882     PCX86PD         pShwPd;
    3883     Assert(pPGM->HCPhysShw32BitPD != 0 && pPGM->HCPhysShw32BitPD != NIL_RTHCPHYS);
    3884     int rc = PGM_HCPHYS_2_PTR(PGM2VM(pPGM), pPGM->HCPhysShw32BitPD, &pShwPd);
    3885     if (RT_FAILURE(rc))
     3953    const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
     3954
     3955    PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
     3956    if (!pShwPde)
    38863957    {
    38873958        X86PDE ZeroPde = {0};
    3888         AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
     3959        return ZeroPde;
    38893960    }
    3890     return pShwPd->a[iPd];
    3891 #else
    3892     return pPGM->CTX_SUFF(pShw32BitPd)->a[iPd];
    3893 #endif
     3961    return pShwPde->a[iPd];
    38943962}
    38953963
    … …  
    39053973DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
    39063974{
    3907     const unsigned  iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
    3908 #ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
    3909     PX86PD          pShwPd;
    3910     Assert(pPGM->HCPhysShw32BitPD != 0 && pPGM->HCPhysShw32BitPD != NIL_RTHCPHYS);
    3911     int rc = PGM_HCPHYS_2_PTR(PGM2VM(pPGM), pPGM->HCPhysShw32BitPD, &pShwPd);
    3912     AssertRCReturn(rc, NULL);
    3913     return &pShwPd->a[iPd];
    3914 #else
    3915     return &pPGM->CTX_SUFF(pShw32BitPd)->a[iPd];
    3916 #endif
     3975    const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
     3976
     3977    PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
     3978    AssertReturn(pPde, NULL);
     3979    return &pPde->a[iPd];
    39173980}
    39183981
    … …  
    39263989DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGM pPGM)
    39273990{
    3928 #ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
     3991#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     3992    return (PX86PDPT)PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPGM->CTX_SUFF(pShwPageCR3));
     3993#else
     3994# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
    39293995    PX86PDPT pShwPdpt;
    39303996    Assert(pPGM->HCPhysShwPaePdpt != 0 && pPGM->HCPhysShwPaePdpt != NIL_RTHCPHYS);
    … …  
    39323998    AssertRCReturn(rc, 0);
    39333999    return pShwPdpt;
    3934 #else
     4000# else
    39354001    return pPGM->CTX_SUFF(pShwPaePdpt);
     4002# endif
    39364003#endif
    39374004}
    … …  
    39434010 * @returns Pointer to the shadow PD.
    39444011 * @param   pPGM        Pointer to the PGM instance data.
    3945  * @param   GCPtr       Address.
     4012 * @param   GCPtr       The address.
    39464013 */
    39474014DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr)
    39484015{
     4016#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
    39494017    const unsigned  iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
    3950 #ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
     4018    PX86PDPT        pPdpt = pgmShwGetPaePDPTPtr(pPGM);
     4019
     4020    /* Fetch the pgm pool shadow descriptor. */
     4021    PPGMPOOLPAGE    pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
     4022    AssertReturn(pShwPde, NULL);
     4023
     4024    return (PX86PDPAE)PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pShwPde);
     4025#else
     4026    const unsigned  iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
     4027# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
    39514028    PX86PDPAE       pPD;
    39524029    int rc = PGM_HCPHYS_2_PTR(PGM2VM(pPGM), pPGM->aHCPhysPaePDs[iPdpt], &pPD);
    39534030    AssertRCReturn(rc, 0);
    39544031    return pPD;
    3955 #else
     4032# else
    39564033    PX86PDPAE       pPD = pPGM->CTX_SUFF(apShwPaePDs)[iPdpt];
    39574034    Assert(pPD);
    39584035    return pPD;
     4036# endif
    39594037#endif
    39604038}
    … …  
    39664044 * @returns PDE.
    39674045 * @param   pPGM        Pointer to the PGM instance data.
    3968  * @param   GCPtr       Address.
     4046 * @param   GCPtr       The address.
    39694047 */
    39704048DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
    39714049{
    3972     const unsigned  iPdpt = (GCPtr >> X86_PDPT_SHIFT)   & X86_PDPT_MASK_PAE;
    39734050    const unsigned  iPd   = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
    3974 #ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
    3975     PCX86PDPAE      pPD;
    3976     int rc = PGM_HCPHYS_2_PTR(PGM2VM(pPGM), pPGM->aHCPhysPaePDs[iPdpt], &pPD);
    3977     if (RT_FAILURE(rc))
     4051
     4052    PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
     4053    if (!pShwPde)
    39784054    {
    39794055        X86PDEPAE ZeroPde = {0};
    3980         AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
     4056        return ZeroPde;
    39814057    }
    3982     return pPD->a[iPd];
    3983 #else
    3984     return pPGM->CTX_SUFF(apShwPaePDs)[iPdpt]->a[iPd];
    3985 #endif
     4058    return pShwPde->a[iPd];
    39864059}
    39874060
    … …  
    39924065 * @returns Pointer to the PDE.
    39934066 * @param   pPGM        Pointer to the PGM instance data.
    3994  * @param   GCPtr       Address.
     4067 * @param   GCPtr       The address.
    39954068 */
    39964069DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
    39974070{
    3998     const unsigned  iPdpt = (GCPtr >> X86_PDPT_SHIFT)   & X86_PDPT_MASK_PAE;
    39994071    const unsigned  iPd   = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
    4000 #ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
    4001     PX86PDPAE       pPD;
    4002     int rc = PGM_HCPHYS_2_PTR(PGM2VM(pPGM), pPGM->aHCPhysPaePDs[iPdpt], &pPD);
    4003     AssertRCReturn(rc, 0);
    4004     return &pPD->a[iPd];
    4005 #else
    4006     Assert(pPGM->CTX_SUFF(apShwPaePDs)[iPdpt]);
    4007     return &pPGM->CTX_SUFF(apShwPaePDs)[iPdpt]->a[iPd];
    4008 #endif
     4072
     4073    PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
     4074    AssertReturn(pPde, NULL);
     4075    return &pPde->a[iPd];
    40094076}
    40104077
    … …  
    40194086DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
    40204087{
    4021 #ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
     4088#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     4089    return (PX86PML4)PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPGM->CTX_SUFF(pShwPageCR3));
     4090#else
     4091# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
    40224092    PX86PML4 pShwPml4;
    40234093    Assert(pPGM->HCPhysShwPaePml4 != 0 && pPGM->HCPhysShwPaePml4 != NIL_RTHCPHYS);
    … …  
    40254095    AssertRCReturn(rc, 0);
    40264096    return pShwPml4;
    4027 #else
     4097# else
    40284098    Assert(pPGM->CTX_SUFF(pShwPaePml4));
    40294099    return pPGM->CTX_SUFF(pShwPaePml4);
     4100# endif
    40304101#endif
    40314102}
    … …  
    40424113{
    40434114    const unsigned  iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
    4044 # ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
    4045     PCX86PML4       pShwPml4;
    4046     Assert(pPGM->HCPhysShwPaePml4 != 0 && pPGM->HCPhysShwPaePml4 != NIL_RTHCPHYS);
    4047     int rc = PGM_HCPHYS_2_PTR(PGM2VM(pPGM), pPGM->HCPhysShwPaePml4, &pShwPml4);
    4048     if (RT_FAILURE(rc))
     4115    PX86PML4        pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
     4116
     4117    if (!pShwPml4)
    40494118    {
    40504119        X86PML4E ZeroPml4e = {0};
    4051         AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
     4120        return ZeroPml4e;
    40524121    }
    40534122    return pShwPml4->a[iPml4];
    4054 # else
    4055     Assert(pPGM->CTX_SUFF(pShwPaePml4));
    4056     return pPGM->CTX_SUFF(pShwPaePml4)->a[iPml4];
    4057 # endif
    40584123}
    40594124
    … …  
    40684133DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
    40694134{
    4070 # ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
    4071     PX86PML4        pShwPml4;
    4072     Assert(pPGM->HCPhysShwPaePml4 != 0 && pPGM->HCPhysShwPaePml4 != NIL_RTHCPHYS);
    4073     int rc = PGM_HCPHYS_2_PTR(PGM2VM(pPGM), pPGM->HCPhysShwPaePml4, &pShwPml4);
    4074     AssertRCReturn(rc, 0);
     4135    PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
     4136
     4137    if (!pShwPml4)
     4138        return NULL;
     4139
    40754140    return &pShwPml4->a[iPml4];
    4076 # else
    4077     Assert(pPGM->CTX_SUFF(pShwPaePml4));
    4078     return &pPGM->CTX_SUFF(pShwPaePml4)->a[iPml4];
    4079 # endif
    40804141}
    40814142

  • trunk/src/VBox/VMM/PGMMap.cpp

    r14154 r14301  
    430430    }
    431431
     432#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    432433    /*
    433434     * Turn off CR3 updating monitoring.
    … …  
    435436    int rc2 = PGM_GST_PFN(UnmonitorCR3, pVM)(pVM);
    436437    AssertRC(rc2);
     438#endif
    437439
    438440    /*
    … …  
    482484    AssertRC(rc);
    483485
     486#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    484487    rc = PGM_GST_PFN(MonitorCR3, pVM)(pVM, pVM->pgm.s.GCPhysCR3);
    485488    AssertRC(rc);
    486 
     489#endif
    487490    return VINF_SUCCESS;
    488491}
    … …  
    723726         */
    724727        pPGM->pInterPD->a[iOldPDE].u        = 0;
     728#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    725729        pPGM->pShw32BitPdR3->a[iOldPDE].u   = 0;
    726 
     730#endif
    727731        /*
    728732         * PAE.
    … …  
    731735        unsigned iPDE = iOldPDE * 2 % 512;
    732736        pPGM->apInterPaePDs[iPD]->a[iPDE].u = 0;
     737#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    733738        pPGM->apShwPaePDsR3[iPD]->a[iPDE].u = 0;
     739#endif
    734740        iPDE++;
    735741        pPGM->apInterPaePDs[iPD]->a[iPDE].u = 0;
     742#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    736743        pPGM->apShwPaePDsR3[iPD]->a[iPDE].u = 0;
    737744
    738745        /* Clear the PGM_PDFLAGS_MAPPING flag for the page directory pointer entry. (legacy PAE guest mode) */
    739746        pPGM->pShwPaePdptR3->a[iPD].u &= ~PGM_PLXFLAGS_MAPPING;
     747#endif
    740748    }
    741749}
    … …  
    771779         * 32-bit.
    772780         */
     781#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    773782        if (pPGM->pShw32BitPdR3->a[iNewPDE].n.u1Present)
    774783            pgmPoolFree(pVM, pPGM->pShw32BitPdR3->a[iNewPDE].u & X86_PDE_PG_MASK, PGMPOOL_IDX_PD, iNewPDE);
     784#endif
    775785        X86PDE Pde;
    776786        /* Default mapping page directory flags are read/write and supervisor; individual page attributes determine the final flags */
    777787        Pde.u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | (uint32_t)pMap->aPTs[i].HCPhysPT;
    778788        pPGM->pInterPD->a[iNewPDE]        = Pde;
     789#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    779790        pPGM->pShw32BitPdR3->a[iNewPDE]   = Pde;
    780 
     791#endif
    781792        /*
    782793         * PAE.
    … …  
    784795        const unsigned iPD = iNewPDE / 256;
    785796        unsigned iPDE = iNewPDE * 2 % 512;
     797#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    786798        if (pPGM->apShwPaePDsR3[iPD]->a[iPDE].n.u1Present)
    787799            pgmPoolFree(pVM, pPGM->apShwPaePDsR3[iPD]->a[iPDE].u & X86_PDE_PAE_PG_MASK, PGMPOOL_IDX_PAE_PD, iNewPDE * 2);
     800#endif
    788801        X86PDEPAE PdePae0;
    789802        PdePae0.u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT0;
    790803        pPGM->apInterPaePDs[iPD]->a[iPDE] = PdePae0;
     804#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    791805        pPGM->apShwPaePDsR3[iPD]->a[iPDE] = PdePae0;
    792 
     806#endif
    793807        iPDE++;
     808#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    794809        if (pPGM->apShwPaePDsR3[iPD]->a[iPDE].n.u1Present)
    795810            pgmPoolFree(pVM, pPGM->apShwPaePDsR3[iPD]->a[iPDE].u & X86_PDE_PAE_PG_MASK, PGMPOOL_IDX_PAE_PD, iNewPDE * 2 + 1);
     811#endif
    796812        X86PDEPAE PdePae1;
    797813        PdePae1.u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT1;
    798814        pPGM->apInterPaePDs[iPD]->a[iPDE] = PdePae1;
     815#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    799816        pPGM->apShwPaePDsR3[iPD]->a[iPDE] = PdePae1;
    800817
    801818        /* Set the PGM_PDFLAGS_MAPPING flag in the page directory pointer entry. (legacy PAE guest mode) */
    802819        pPGM->pShwPaePdptR3->a[iPD].u |= PGM_PLXFLAGS_MAPPING;
     820#endif
    803821    }
    804822}
    … …  
    11291147}
    11301148
     1149#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     1150/**
     1151 * Apply the hypervisor mappings to the active CR3.
     1152 *
     1153 * @returns VBox status.
     1154 * @param   pVM         The virtual machine.
     1155 */
     1156VMMR3DECL(int) PGMR3MapActivate(PVM pVM)
     1157{
     1158    /*
     1159     * Can skip this if mappings are safely fixed.
     1160     */
     1161    if (pVM->pgm.s.fMappingsFixed)
     1162        return VINF_SUCCESS;
     1163
     1164    PGMMODE const enmGuestMode = PGMGetGuestMode(pVM);
     1165    Assert(enmGuestMode <= PGMMODE_PAE_NX);
     1166
     1167    /*
     1168     * Iterate mappings.
     1169     */
     1170    if (enmGuestMode == PGMMODE_32_BIT)
     1171    {
     1172        /*
     1173         * Resolve the page directory.
     1174         */
     1175        PX86PD pPD = (PX86PD)pVM->pgm.s.pShwPageCR3R3;
     1176        Assert(pPD);
     1177
     1178        for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
     1179        {
     1180            unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
     1181            unsigned iPT = pCur->cPTs;
     1182            while (iPT-- > 0)
     1183                pPD->a[iPDE + iPT].u = 0;
     1184        }
     1185    }
     1186    else if (   enmGuestMode == PGMMODE_PAE
     1187             || enmGuestMode == PGMMODE_PAE_NX)
     1188    {
     1189        for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
     1190        {
     1191            RTGCPTR   GCPtr = pCur->GCPtr;
     1192            unsigned  iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
     1193
     1194            unsigned  iPT = pCur->cb >> X86_PD_PAE_SHIFT;
     1195            while (iPT-- > 0)
     1196            {
     1197                PX86PDEPAE pPDE = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtr);
     1198                pPDE->u = 0;
     1199
     1200                GCPtr += (1 << X86_PD_PAE_SHIFT);
     1201            }
     1202        }
     1203    }
     1204    else
     1205        AssertFailed();
     1206
     1207    return VINF_SUCCESS;
     1208}
     1209
     1210/**
     1211 * Remove the hypervisor mappings from the active CR3
     1212 *
     1213 * @returns VBox status.
     1214 * @param   pVM         The virtual machine.
     1215 */
     1216VMMR3DECL(int) PGMR3MapDeactivate(PVM pVM)
     1217{
     1218    /*
     1219     * Can skip this if mappings are safely fixed.
     1220     */
     1221    if (pVM->pgm.s.fMappingsFixed)
     1222        return VINF_SUCCESS;
     1223
     1224    PGMMODE const enmGuestMode = PGMGetGuestMode(pVM);
     1225    Assert(enmGuestMode <= PGMMODE_PAE_NX);
     1226
     1227    /*
     1228     * Iterate mappings.
     1229     */
     1230    if (enmGuestMode == PGMMODE_32_BIT)
     1231    {
     1232        /*
     1233         * Resolve the page directory.
     1234         */
     1235        PX86PD pPD = (PX86PD)pVM->pgm.s.pShwPageCR3R3;
     1236        Assert(pPD);
     1237
     1238        for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
     1239        {
     1240            unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
     1241            unsigned iPT = pCur->cPTs;
     1242            while (iPT-- > 0)
     1243                pPD->a[iPDE + iPT].u = 0;
     1244        }
     1245    }
     1246    else if (   enmGuestMode == PGMMODE_PAE
     1247             || enmGuestMode == PGMMODE_PAE_NX)
     1248    {
     1249        for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
     1250        {
     1251            RTGCPTR   GCPtr = pCur->GCPtr;
     1252
     1253            unsigned  iPT = pCur->cb >> X86_PD_PAE_SHIFT;
     1254            while (iPT-- > 0)
     1255            {
     1256                PX86PDEPAE pPDE = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtr);
     1257                pPDE->u = 0;
     1258
     1259                GCPtr += (1 << X86_PD_PAE_SHIFT);
     1260            }
     1261        }
     1262
     1263        /* Clear the PGM_PDFLAGS_MAPPING flag for the page directory pointer entries. (legacy PAE guest mode) */
     1264        PX86PDPT pPdpt = (PX86PDPT)pVM->pgm.s.pShwPageCR3R3;
     1265        for (unsigned i=0;i<X86_PG_PAE_PDPE_ENTRIES;i++)
     1266            pPdpt->a[i].u &= ~PGM_PLXFLAGS_MAPPING;
     1267    }
     1268    else
     1269        AssertFailed();
     1270
     1271    return VINF_SUCCESS;
     1272}
     1273#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
    11311274
    11321275/**

  • trunk/src/VBox/VMM/PGMPool.cpp

    r14147 r14301  
    255255    pPool->aPages[PGMPOOL_IDX_PD].Core.Key  = NIL_RTHCPHYS;
    256256    pPool->aPages[PGMPOOL_IDX_PD].GCPhys    = NIL_RTGCPHYS;
     257#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     258    pPool->aPages[PGMPOOL_IDX_PD].pvPageR3  = 0;
     259    pPool->aPages[PGMPOOL_IDX_PD].enmKind   = PGMPOOLKIND_32BIT_PD;
     260#else
    257261    pPool->aPages[PGMPOOL_IDX_PD].pvPageR3  = pVM->pgm.s.pShw32BitPdR3;
    258262    pPool->aPages[PGMPOOL_IDX_PD].enmKind   = PGMPOOLKIND_ROOT_32BIT_PD;
     263#endif
    259264    pPool->aPages[PGMPOOL_IDX_PD].idx       = PGMPOOL_IDX_PD;
    260265
     266#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
    261267    /* The Shadow PAE PDs. This is actually 4 pages! (32 bits guest paging)  */
    262268    pPool->aPages[PGMPOOL_IDX_PAE_PD].Core.Key  = NIL_RTHCPHYS;
    … …  
    275281        pPool->aPages[PGMPOOL_IDX_PAE_PD_0 + i].idx       = PGMPOOL_IDX_PAE_PD_0 + i;
    276282    }
     283#endif
    277284
    278285    /* The Shadow PDPT. */
    279286    pPool->aPages[PGMPOOL_IDX_PDPT].Core.Key  = NIL_RTHCPHYS;
    280287    pPool->aPages[PGMPOOL_IDX_PDPT].GCPhys    = NIL_RTGCPHYS;
     288#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     289    pPool->aPages[PGMPOOL_IDX_PDPT].pvPageR3  = 0;
     290    pPool->aPages[PGMPOOL_IDX_PDPT].enmKind   = PGMPOOLKIND_PAE_PDPT;
     291#else
    281292    pPool->aPages[PGMPOOL_IDX_PDPT].pvPageR3  = pVM->pgm.s.pShwPaePdptR3;
    282293    pPool->aPages[PGMPOOL_IDX_PDPT].enmKind   = PGMPOOLKIND_ROOT_PDPT;
     294#endif
    283295    pPool->aPages[PGMPOOL_IDX_PDPT].idx       = PGMPOOL_IDX_PDPT;
    284296
    … …  
    286298    pPool->aPages[PGMPOOL_IDX_AMD64_CR3].Core.Key  = NIL_RTHCPHYS;
    287299    pPool->aPages[PGMPOOL_IDX_AMD64_CR3].GCPhys    = NIL_RTGCPHYS;
     300#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     301    pPool->aPages[PGMPOOL_IDX_AMD64_CR3].pvPageR3  = 0;
     302#else
    288303    pPool->aPages[PGMPOOL_IDX_AMD64_CR3].pvPageR3  = pVM->pgm.s.pShwPaePdptR3;  /* not used - isn't it wrong as well? */
     304#endif
    289305    pPool->aPages[PGMPOOL_IDX_AMD64_CR3].enmKind   = PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4;
    290306    pPool->aPages[PGMPOOL_IDX_AMD64_CR3].idx       = PGMPOOL_IDX_AMD64_CR3;

  • trunk/src/VBox/VMM/VMMSwitcher/32BitToAMD64.asm

    r14267 r14301  
    439439    lss     esp, [edx + CPUMCPU.Host.esp]
    440440
    441         FIXUP FIX_NO_SYSENTER_JMP, 0, gth_sysenter_no - NAME(Start) ; this will insert a jmp gth_sysenter_no if host doesn't use sysenter.
     441    FIXUP FIX_NO_SYSENTER_JMP, 0, gth_sysenter_no - NAME(Start) ; this will insert a jmp gth_sysenter_no if host doesn't use sysenter.
     442   
    442443    ; restore MSR_IA32_SYSENTER_CS register.
    443444    mov     ecx, MSR_IA32_SYSENTER_CS
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