Changeset 14859 in vbox for trunk/src/VBox

Timestamp:

Dec 1, 2008 2:01:55 PM (16 years ago)

Author:

vboxsync

Message:

More updates for 32/64.

Location:

trunk/src/VBox/VMM

Files:

• CPUMInternal.h (modified) (2 diffs)
• VMMAll/CPUMAllA.asm (modified) (2 diffs)
• VMMAll/CPUMAllRegs.cpp (modified) (1 diff)
• VMMR0/CPUMR0.cpp (modified) (4 diffs)
• VMMR0/HWACCMR0.cpp (modified) (1 diff)
• VMMR0/HWSVMR0.cpp (modified) (1 diff)
• VMMR0/HWVMXR0.cpp (modified) (1 diff)

trunk/src/VBox/VMM/CPUMInternal.h

@@ -72 +72 @@
 /** The XMM state was manually restored. (AMD only) */
 #define CPUM_MANUAL_XMM_RESTORE         RT_BIT(6)
+/** Sync the FPU state on entry (32->64 switcher only). */
+#define CPUM_SYNC_FPU_STATE             RT_BIT(7)
+/** Sync the debug state on entry (32->64 switcher only). */
+#define CPUM_SYNC_DEBUG_STATE           RT_BIT(8)
 /** @} */
 
@@ -374 +378 @@
 
 DECLASM(int)      CPUMHandleLazyFPUAsm(PCPUMCPU pCPUM);
+DECLASM(int)      CPUMSaveGuestRestoreHostFPUStateAsm(PCPUMCPU pCPUM);
 DECLASM(int)      CPUMRestoreHostFPUStateAsm(PCPUMCPU pCPUM);
 DECLASM(void)     CPUMLoadFPUAsm(PCPUMCTX pCtx);

trunk/src/VBox/VMM/VMMAll/CPUMAllA.asm

@@ -209 +209 @@
 ;
 align 16
-BEGINPROC CPUMRestoreHostFPUStateAsm
+BEGINPROC CPUMSaveGuestRestoreHostFPUStateAsm
 %ifdef RT_ARCH_AMD64
  %ifdef RT_OS_WINDOWS
@@ -238 +238 @@
     xor     eax, eax
     ret
+ENDPROC   CPUMSaveGuestRestoreHostFPUStateAsm
+
+;;
+; Sets the host's FPU/XMM state
+;
+; @returns  0
+; @param    pCPUMCPU  x86:[esp+4] GCC:rdi MSC:rcx     CPUMCPU pointer
+;
+align 16
+BEGINPROC CPUMRestoreHostFPUStateAsm
+%ifdef RT_ARCH_AMD64
+ %ifdef RT_OS_WINDOWS
+    mov     xDX, rcx
+ %else
+    mov     xDX, rdi
+ %endif
+%else
+    mov     xDX, dword [esp + 4]
+%endif
+
+    ; Restore FPU if guest has used it.
+    ; Using fxrstor should ensure that we're not causing unwanted exception on the host.
+    test    dword [xDX + CPUMCPU.fUseFlags], CPUM_USED_FPU
+    jz short gth_fpu_no_2
+
+    mov     xAX, cr0
+    mov     xCX, xAX                    ; save old CR0
+    and     xAX, ~(X86_CR0_TS | X86_CR0_EM)
+    mov     cr0, xAX
+
+    fxrstor [xDX + CPUMCPU.Host.fpu]
+
+    mov     cr0, xCX                    ; and restore old CR0 again
+    and     dword [xDX + CPUMCPU.fUseFlags], ~CPUM_USED_FPU
+gth_fpu_no_2:
+    xor     eax, eax
+    ret
 ENDPROC   CPUMRestoreHostFPUStateAsm
-
 
 ;;

trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp

@@ -2084 +2084 @@
  * @param   pVCpu       VMCPU handle
  */
+VMMDECL(int) CPUMSaveGuestRestoreHostFPUState(PVM pVM, PVMCPU pVCpu)
+{
+    Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
+    return CPUMSaveGuestRestoreHostFPUStateAsm(&pVCpu->cpum.s);
+}
+
+/**
+ * Set host FPU/XMM state
+ *
+ * @returns VBox status code.
+ * @param   pVM         VM handle.
+ * @param   pVCpu       VMCPU handle
+ */
 VMMDECL(int) CPUMRestoreHostFPUState(PVM pVM, PVMCPU pVCpu)
 {

trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp

@@ -167 +167 @@
     }
 
+#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
+    if (CPUMIsGuestInLongModeEx(pCtx))
+    {
+        /* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
+        pVCpu->cpum.s.fUseFlags |= CPUM_SYNC_FPU_STATE;
+    }
+    else
+#endif
+    {
 #ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
-    uint64_t oldMsrEFERHost;
-    uint32_t oldCR0 = ASMGetCR0();
-
-    /* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
-    if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
-    {
-        /** @todo Do we really need to read this every time?? The host could change this on the fly though.
-         *  bird: what about starting by skipping the ASMWrMsr below if we didn't
-         *        change anything? Ditto for the stuff in CPUMR0SaveGuestFPU. */
-        oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
-        if (oldMsrEFERHost & MSR_K6_EFER_FFXSR)
-        {
-            ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
-            pVCpu->cpum.s.fUseFlags |= CPUM_MANUAL_XMM_RESTORE;
-        }
-    }
-
-    /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
-    int rc = CPUMHandleLazyFPU(pVM, pVCpu);
-    AssertRC(rc);
-    Assert(CPUMIsGuestFPUStateActive(pVCpu));
-
-    /* Restore EFER MSR */
-    if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
-        ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost);
-
-        /* CPUMHandleLazyFPU could have changed CR0; restore it. */
-    ASMSetCR0(oldCR0);
+        uint64_t oldMsrEFERHost;
+        uint32_t oldCR0 = ASMGetCR0();
+
+        /* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
+        if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
+        {
+            /** @todo Do we really need to read this every time?? The host could change this on the fly though.
+             *  bird: what about starting by skipping the ASMWrMsr below if we didn't
+             *        change anything? Ditto for the stuff in CPUMR0SaveGuestFPU. */
+            oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
+            if (oldMsrEFERHost & MSR_K6_EFER_FFXSR)
+            {
+                ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
+                pVCpu->cpum.s.fUseFlags |= CPUM_MANUAL_XMM_RESTORE;
+            }
+        }
+
+        /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
+        int rc = CPUMHandleLazyFPU(pVM, pVCpu);
+        AssertRC(rc);
+        Assert(CPUMIsGuestFPUStateActive(pVCpu));
+
+        /* Restore EFER MSR */
+        if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
+            ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost);
+
+            /* CPUMHandleLazyFPU could have changed CR0; restore it. */
+        ASMSetCR0(oldCR0);
 
 #else  /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
 
-    /*
-     * Save the FPU control word and MXCSR, so we can restore the state properly afterwards.
-     * We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
-     */
-    pVCpu->cpum.s.Host.fpu.FCW = CPUMGetFCW();
-    if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
-        pVCpu->cpum.s.Host.fpu.MXCSR = CPUMGetMXCSR();
-
-    CPUMLoadFPUAsm(pCtx);
-
-    /*
-     * The MSR_K6_EFER_FFXSR feature is AMD only so far, but check the cpuid just in case Intel adds it in the future.
-     *
-     * MSR_K6_EFER_FFXSR changes the behaviour of fxsave and fxrstore: the XMM state isn't saved/restored
-     */
-    if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
-    {
-        /** @todo Do we really need to read this every time?? The host could change this on the fly though. */
-        uint64_t msrEFERHost = ASMRdMsr(MSR_K6_EFER);
-
-        if (msrEFERHost & MSR_K6_EFER_FFXSR)
-        {
-            /* fxrstor doesn't restore the XMM state! */
-            CPUMLoadXMMAsm(pCtx);
-            pVCpu->cpum.s.fUseFlags |= CPUM_MANUAL_XMM_RESTORE;
-        }
-    }
+        /*
+         * Save the FPU control word and MXCSR, so we can restore the state properly afterwards.
+         * We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
+         */
+        pVCpu->cpum.s.Host.fpu.FCW = CPUMGetFCW();
+        if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
+            pVCpu->cpum.s.Host.fpu.MXCSR = CPUMGetMXCSR();
+
+        CPUMLoadFPUAsm(pCtx);
+
+        /*
+         * The MSR_K6_EFER_FFXSR feature is AMD only so far, but check the cpuid just in case Intel adds it in the future.
+         *
+         * MSR_K6_EFER_FFXSR changes the behaviour of fxsave and fxrstore: the XMM state isn't saved/restored
+         */
+        if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
+        {
+            /** @todo Do we really need to read this every time?? The host could change this on the fly though. */
+            uint64_t msrEFERHost = ASMRdMsr(MSR_K6_EFER);
+
+            if (msrEFERHost & MSR_K6_EFER_FFXSR)
+            {
+                /* fxrstor doesn't restore the XMM state! */
+                CPUMLoadXMMAsm(pCtx);
+                pVCpu->cpum.s.fUseFlags |= CPUM_MANUAL_XMM_RESTORE;
+            }
+        }
 #endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
+    }
 
     pVCpu->cpum.s.fUseFlags |= CPUM_USED_FPU;
@@ -247 +257 @@
     AssertReturn((pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU), VINF_SUCCESS);
 
+#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
+    if (CPUMIsGuestInLongModeEx(pCtx))
+    {
+        Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
+        HWACCMR0SaveFPUState(pVM, pVCpu, pCtx);
+        CPUMRestoreHostFPUState(pVCpu);
+    }
+    else
+#endif
+    {
 #ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
-    uint64_t oldMsrEFERHost;
-
-    /* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
-    if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
-    {
-        oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
-        ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
-    }
-    CPUMRestoreHostFPUState(pVM, pVCpu);
-
-    /* Restore EFER MSR */
-    if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
-        ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost | MSR_K6_EFER_FFXSR);
+        uint64_t oldMsrEFERHost;
+
+        /* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
+        if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
+        {
+            oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
+            ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
+        }
+        CPUMSaveGuestRestoreHostFPUState(pVM, pVCpu);
+
+        /* Restore EFER MSR */
+        if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
+            ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost | MSR_K6_EFER_FFXSR);
 
 #else  /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
-    CPUMSaveFPUAsm(pCtx);
-    if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
-    {
-        /* fxsave doesn't save the XMM state! */
-        CPUMSaveXMMAsm(pCtx);
-    }
-
-    /*
-     * Restore the original FPU control word and MXCSR.
-     * We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
-     */
-    CPUMSetFCW(pVCpu->cpum.s.Host.fpu.FCW);
-    if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
-        CPUMSetMXCSR(pVCpu->cpum.s.Host.fpu.MXCSR);
+        CPUMSaveFPUAsm(pCtx);
+        if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
+        {
+            /* fxsave doesn't save the XMM state! */
+            CPUMSaveXMMAsm(pCtx);
+        }
+
+        /*
+         * Restore the original FPU control word and MXCSR.
+         * We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
+         */
+        CPUMSetFCW(pVCpu->cpum.s.Host.fpu.FCW);
+        if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
+            CPUMSetMXCSR(pVCpu->cpum.s.Host.fpu.MXCSR);
 #endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
+    }
 
     pVCpu->cpum.s.fUseFlags &= ~(CPUM_USED_FPU | CPUM_MANUAL_XMM_RESTORE);
@@ -298 +319 @@
 
     /* Save the guest's debug state. The caller is responsible for DR7. */
-    pCtx->dr[0] = ASMGetDR0();
-    pCtx->dr[1] = ASMGetDR1();
-    pCtx->dr[2] = ASMGetDR2();
-    pCtx->dr[3] = ASMGetDR3();
-    if (fDR6)
-        pCtx->dr[6] = ASMGetDR6();
+#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
+    if (CPUMIsGuestInLongModeEx(pCtx))
+    {
+        Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_DEBUG_STATE));
+        HWACCMR0SaveDebugState(pVM, pVCpu, pCtx, fDR6);
+    }
+    else
+#endif
+    {
+        pCtx->dr[0] = ASMGetDR0();
+        pCtx->dr[1] = ASMGetDR1();
+        pCtx->dr[2] = ASMGetDR2();
+        pCtx->dr[3] = ASMGetDR3();
+        if (fDR6)
+            pCtx->dr[6] = ASMGetDR6();
+    }
 
     /*
@@ -344 +375 @@
 
     /* Activate the guest state DR0-3; DR7 is left to the caller. */
-    ASMSetDR0(pCtx->dr[0]);
-    ASMSetDR1(pCtx->dr[1]);
-    ASMSetDR2(pCtx->dr[2]);
-    ASMSetDR3(pCtx->dr[3]);
-    if (fDR6)
-        ASMSetDR6(pCtx->dr[6]);
+#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
+    if (CPUMIsGuestInLongModeEx(pCtx))
+    {
+        /* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
+        pVCpu->cpum.s.fUseFlags |= CPUM_SYNC_DEBUG_STATE;
+    }
+    else
+#endif
+    {
+        ASMSetDR0(pCtx->dr[0]);
+        ASMSetDR1(pCtx->dr[1]);
+        ASMSetDR2(pCtx->dr[2]);
+        ASMSetDR3(pCtx->dr[3]);
+        if (fDR6)
+            ASMSetDR6(pCtx->dr[6]);
+    }
 
     pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS;

trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp

@@ -998 +998 @@
     return rc;
 }
+
+
+#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
+/**
+ * Save guest FPU/XMM state
+ *
+ * @returns VBox status code.
+ * @param   pVM         VM handle.
+ * @param   pVCpu       VMCPU handle.
+ * @param   pCtx        CPU context
+ */
+VMMR0DECL(int)   HWACCMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
+{
+    return VINF_SUCCESS;
+}
+
+/**
+ * Save guest debug state (64 bits guest mode & 32 bits host only)
+ *
+ * @returns VBox status code.
+ * @param   pVM         VM handle.
+ * @param   pVCpu       VMCPU handle.
+ * @param   pCtx        CPU context
+ * @param   fDR6        Include DR6 or not
+ */
+VMMR0DECL(int)   HWACCMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
+{
+    return VINF_SUCCESS;
+}
+#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) */
 
 /**

trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

@@ -2277 +2277 @@
 DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx)
 {
+    /* @todo This code is not guest SMP safe (hyper context) */
+    AssertReturn(pVM->cCPUs == 1, VERR_ACCESS_DENIED);
     return VERR_NOT_IMPLEMENTED;
 }

trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

@@ -3434 +3434 @@
     RTHCPHYS        pPageCpuPhys;
 
+    /* @todo This code is not guest SMP safe (hyper context) */
+    AssertReturn(pVM->cCPUs == 1, VERR_ACCESS_DENIED);
+
     pCpu = HWACCMR0GetCurrentCpuEx(pVCpu->idCpu);
     pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);