Changeset 15030 in vbox for trunk/src/VBox/VMM/VMMGC

Timestamp:

Dec 5, 2008 11:12:26 AM (16 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

40406

Message:

Switcher updates

File:

• trunk/src/VBox/VMM/VMMGC/HWACCMGCA.asm (modified) (10 diffs)

trunk/src/VBox/VMM/VMMGC/HWACCMGCA.asm

@@ -47 +47 @@
 %endif
 
-;; @def MYPUSHAD
-; Macro generating an equivalent to pushad
-
-;; @def MYPOPAD
-; Macro generating an equivalent to popad
-
 ;; @def MYPUSHSEGS
 ; Macro saving all segment registers on the stack.
 ; @param 1  full width register name
-; @param 2  16-bit regsiter name for \a 1.
 
 ;; @def MYPOPSEGS
 ; Macro restoring all segment registers on the stack
 ; @param 1  full width register name
-; @param 2  16-bit regsiter name for \a 1.
 
   ; Load the corresponding guest MSR (trashes rdx & rcx)
@@ -70 +62 @@
   %endmacro
 
-  ; Save a guest and load the corresponding host MSR (trashes rdx & rcx)
+  ; Save a guest MSR (trashes rdx & rcx)
   ; Only really useful for gs kernel base as that one can be changed behind our back (swapgs)
-  %macro LOADHOSTMSREX 2
+  %macro SAVEGUESTMSR 2
     mov     rcx, %1
     rdmsr
@@ -79 +71 @@
   %endmacro
 
- %ifdef ASM_CALL64_GCC
-  %macro MYPUSHAD 0
-    push    r15
-    push    r14
-    push    r13
-    push    r12
-    push    rbx
-  %endmacro
-  %macro MYPOPAD 0
-    pop     rbx
-    pop     r12
-    pop     r13
-    pop     r14
-    pop     r15
-  %endmacro
-
- %else ; ASM_CALL64_MSC
-  %macro MYPUSHAD 0
-    push    r15
-    push    r14
-    push    r13
-    push    r12
-    push    rbx
-    push    rsi
-    push    rdi
-  %endmacro
-  %macro MYPOPAD 0
-    pop     rdi
-    pop     rsi
-    pop     rbx
-    pop     r12
-    pop     r13
-    pop     r14
-    pop     r15
-  %endmacro
- %endif
-
-; trashes, rax, rdx & rcx
- %macro MYPUSHSEGS 2
-    mov     %2, es
+ %macro MYPUSHSEGS 1
+    mov     %1, es
     push    %1
-    mov     %2, ds
+    mov     %1, ds
     push    %1
-
-    ; Special case for FS; Windows and Linux either don't use it or restore it when leaving kernel mode, Solaris OTOH doesn't and we must save it.
-    mov     ecx, MSR_K8_FS_BASE
-    rdmsr
-    push    rdx
-    push    rax
-    push    fs
-
-    ; Special case for GS; OSes typically use swapgs to reset the hidden base register for GS on entry into the kernel. The same happens on exit
-    mov     ecx, MSR_K8_GS_BASE
-    rdmsr
-    push    rdx
-    push    rax
-    push    gs
- %endmacro
-
-; trashes, rax, rdx & rcx
- %macro MYPOPSEGS 2
-    ; Note: do not step through this code with a debugger!
-    pop     gs
-    pop     rax
-    pop     rdx
-    mov     ecx, MSR_K8_GS_BASE
-    wrmsr
-
-    pop     fs
-    pop     rax
-    pop     rdx
-    mov     ecx, MSR_K8_FS_BASE
-    wrmsr
-    ; Now it's safe to step again
-
+ %endmacro
+
+ %macro MYPOPSEGS 1
     pop     %1
-    mov     ds, %2
+    mov     ds, %1
     pop     %1
-    mov     es, %2
- %endmacro
-
-
+    mov     es, %1
+ %endmacro
+
+; trashes rax & rdx
+ %macro VMCSWRITE 2
+    mov     rdx, %2
+    mov     eax, %1
+    vmwrite rax, rdx
+ %endmacro
+
+; trashes rax & rdx
+ %macro VMCSREAD 2
+    mov     eax, %1
+    vmwrite rax, rdx
+    mov     %2, rdx
+ %endmacro
 
 BEGINCODE
@@ -176 +113 @@
     mov     rbp, rsp
 
-    pushf
-    cli
-
-    ; Have to sync half the guest state as we can't access most of the 64 bits state. Sigh
-;    VMCSWRITE VMX_VMCS64_GUEST_CS_BASE,         [rsi + CPUMCTX.csHid.u64Base]
-;    VMCSWRITE VMX_VMCS64_GUEST_DS_BASE,         [rsi + CPUMCTX.dsHid.u64Base]
-;    VMCSWRITE VMX_VMCS64_GUEST_ES_BASE,         [rsi + CPUMCTX.esHid.u64Base]
-;    VMCSWRITE VMX_VMCS64_GUEST_FS_BASE,         [rsi + CPUMCTX.fsHid.u64Base]
-;    VMCSWRITE VMX_VMCS64_GUEST_GS_BASE,         [rsi + CPUMCTX.gsHid.u64Base]
-;    VMCSWRITE VMX_VMCS64_GUEST_SS_BASE,         [rsi + CPUMCTX.ssHid.u64Base]
-;    VMCSWRITE VMX_VMCS64_GUEST_LDTR_BASE,       [rsi + CPUMCTX.ldtrHid.u64Base]
-;    VMCSWRITE VMX_VMCS64_GUEST_GDTR_BASE,       [rsi + CPUMCTX.gdtrHid.u64Base]
-;    VMCSWRITE VMX_VMCS64_GUEST_IDTR_BASE,       [rsi + CPUMCTX.idtrHid.u64Base]
-;    VMCSWRITE VMX_VMCS64_GUEST_TR_BASE,         [rsi + CPUMCTX.trHid.u64Base]
-;    
-;    VMCSWRITE VMX_VMCS64_GUEST_SYSENTER_EIP,    [rsi + CPUMCTX.SysEnter.eip]
-;    VMCSWRITE VMX_VMCS64_GUEST_SYSENTER_ESP,    [rsi + CPUMCTX.SysEnter.esp]
-;    
-;    VMCSWRITE VMX_VMCS64_GUEST_RIP,             [rsi + CPUMCTX.eip]
-;    VMCSWRITE VMX_VMCS64_GUEST_RSP,             [rsi + CPUMCTX.esp]
-    
-
+    ; Have to sync half the guest state as we can't access most of the 64 bits state in 32 bits mode. Sigh.
+    VMCSWRITE VMX_VMCS64_GUEST_CS_BASE,         [rsi + CPUMCTX.csHid.u64Base]
+    VMCSWRITE VMX_VMCS64_GUEST_DS_BASE,         [rsi + CPUMCTX.dsHid.u64Base]
+    VMCSWRITE VMX_VMCS64_GUEST_ES_BASE,         [rsi + CPUMCTX.esHid.u64Base]
+    VMCSWRITE VMX_VMCS64_GUEST_FS_BASE,         [rsi + CPUMCTX.fsHid.u64Base]
+    VMCSWRITE VMX_VMCS64_GUEST_GS_BASE,         [rsi + CPUMCTX.gsHid.u64Base]
+    VMCSWRITE VMX_VMCS64_GUEST_SS_BASE,         [rsi + CPUMCTX.ssHid.u64Base]
+    VMCSWRITE VMX_VMCS64_GUEST_GDTR_BASE,       [rsi + CPUMCTX.gdtr.pGdt]
+    VMCSWRITE VMX_VMCS64_GUEST_IDTR_BASE,       [rsi + CPUMCTX.idtr.pIdt]
+    VMCSWRITE VMX_VMCS64_GUEST_LDTR_BASE,       [rsi + CPUMCTX.ldtrHid.u64Base]
+    VMCSWRITE VMX_VMCS64_GUEST_TR_BASE,         [rsi + CPUMCTX.trHid.u64Base]
+    
+    VMCSWRITE VMX_VMCS64_GUEST_SYSENTER_EIP,    [rsi + CPUMCTX.SysEnter.eip]
+    VMCSWRITE VMX_VMCS64_GUEST_SYSENTER_ESP,    [rsi + CPUMCTX.SysEnter.esp]
+    
+    VMCSWRITE VMX_VMCS64_GUEST_RIP,             [rsi + CPUMCTX.eip]
+    VMCSWRITE VMX_VMCS64_GUEST_RSP,             [rsi + CPUMCTX.esp]
+    
+    ; Save the host state that's relevant in the temporary 64 bits mode
+    mov     rax, cr0
+    VMCSWRITE VMX_VMCS_HOST_CR0,                rax
+    mov     rax, cr3
+    VMCSWRITE VMX_VMCS_HOST_CR3,                rax
+    mov     rax, cr4
+    VMCSWRITE VMX_VMCS_HOST_CR4,                rax
+    mov     rax, cs
+    VMCSWRITE VMX_VMCS_HOST_FIELD_CS,           rax
+    mov     rax, ss
+    VMCSWRITE VMX_VMCS_HOST_FIELD_SS,           rax
+
+    sub     rsp, 8*2
+    sgdt    [rsp]          
+    mov     rax, [rsp+2]
+    VMCSWRITE VMX_VMCS_HOST_GDTR_BASE,          rax
+    add     rsp, 8*2
+    
+    ; hopefully we can ignore TR (we restore it anyway on the way back to 32 bits mode)
+    
     ;/* First we have to save some final CPU context registers. */
-    lea     rax, [.vmlaunch64_done wrt rip]    
-    push    rax
+    lea     rdx, [.vmlaunch64_done wrt rip]    
     mov     rax, VMX_VMCS_HOST_RIP  ;/* return address (too difficult to continue after VMLAUNCH?) */
-    vmwrite rax, [rsp]
+    vmwrite rax, rdx
     ;/* Note: assumes success... */
-    add     rsp, 8
 
     ;/* Manual save and restore:
@@ -218 +169 @@
     ; */
 
-    ;/* Save all general purpose host registers. */
-    MYPUSHAD
-
-    ;/* Save the Guest CPU context pointer. */
-    ; pCtx    already in rsi
-
     ;/* Save segment registers */
-    ; Note: MYPUSHSEGS trashes rdx & rcx, so we moved it here (msvc amd64 case)
-    MYPUSHSEGS rax, ax
-
-    ; Save the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs and restore the guest MSRs
+    MYPUSHSEGS rax
+
+    ; Load the guest LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs
     ;; @todo use the automatic load feature for MSRs
     LOADGUESTMSR MSR_K8_LSTAR,          CPUMCTX.msrLSTAR
+%if 0  ; not supported on Intel CPUs
+    LOADGUESTMSR MSR_K8_CSTAR,          CPUMCTX.msrCSTAR
+%endif
     LOADGUESTMSR MSR_K6_STAR,           CPUMCTX.msrSTAR
     LOADGUESTMSR MSR_K8_SF_MASK,        CPUMCTX.msrSFMASK
@@ -237 +184 @@
     ; Save the pCtx pointer
     push    rsi
-
-    ; Save LDTR
-    xor     eax, eax
-    sldt    ax
-    push    rax
-
-    ; VMX only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
-    sub     rsp, 8*2
-    sgdt    [rsp]
-
-    sub     rsp, 8*2
-    sidt    [rsp]
 
     ; Restore CR2
@@ -286 +221 @@
     jz      near .vmstart64_start_failed
 
-    ; Restore base and limit of the IDTR & GDTR
-    lidt    [rsp]
-    add     rsp, 8*2
-    lgdt    [rsp]
-    add     rsp, 8*2
-
     push    rdi
     mov     rdi, [rsp + 8 * 2]         ; pCtx
@@ -313 +242 @@
     mov     qword [rdi + CPUMCTX.edi], rax
 
-    pop     rax         ; saved LDTR
-    lldt    ax
-
+    pop     rsi         ; pCtx (needed in rsi by the macros below)
+
+    ;; @todo use the automatic load feature for MSRs
+    SAVEGUESTMSR MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
+
+    ; Restore segment registers
+    MYPOPSEGS rax
+
+    mov     eax, VINF_SUCCESS
+
+.vmstart64_end:
+    pop     rbp
+    ret
+
+
+.vmstart64_invalid_vmxon_ptr:
     pop     rsi         ; pCtx (needed in rsi by the macros below)
 
     ; Restore the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs
     ;; @todo use the automatic load feature for MSRs
-    LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
+    SAVEGUESTMSR MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
 
     ; Restore segment registers
-    MYPOPSEGS rax, ax
-
-    ; Restore general purpose registers
-    MYPOPAD
-
-    mov     eax, VINF_SUCCESS
-
-.vmstart64_end:
-    popf
-    pop     rbp
-    ret
-
-
-.vmstart64_invalid_vmxon_ptr:
-    ; Restore base and limit of the IDTR & GDTR
-    lidt    [rsp]
-    add     rsp, 8*2
-    lgdt    [rsp]
-    add     rsp, 8*2
-
-    pop     rax         ; saved LDTR
-    lldt    ax
-
+    MYPOPSEGS rax
+
+    ; Restore all general purpose host registers.
+    mov     eax, VERR_VMX_INVALID_VMXON_PTR
+    jmp     .vmstart64_end
+
+.vmstart64_start_failed:
     pop     rsi         ; pCtx (needed in rsi by the macros below)
 
     ; Restore the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs
     ;; @todo use the automatic load feature for MSRs
-    LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
+    SAVEGUESTMSR MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
 
     ; Restore segment registers
-    MYPOPSEGS rax, ax
+    MYPOPSEGS rax
 
     ; Restore all general purpose host registers.
-    MYPOPAD
-    mov     eax, VERR_VMX_INVALID_VMXON_PTR
-    jmp     .vmstart64_end
-
-.vmstart64_start_failed:
-    ; Restore base and limit of the IDTR & GDTR
-    lidt    [rsp]
-    add     rsp, 8*2
-    lgdt    [rsp]
-    add     rsp, 8*2
-
-    pop     rax         ; saved LDTR
-    lldt    ax
-
-    pop     rsi         ; pCtx (needed in rsi by the macros below)
-
-    ; Restore the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs
-    ;; @todo use the automatic load feature for MSRs
-    LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
-
-    ; Restore segment registers
-    MYPOPSEGS rax, ax
-
-    ; Restore all general purpose host registers.
-    MYPOPAD
     mov     eax, VERR_VMX_UNABLE_TO_START_VM
     jmp     .vmstart64_end
@@ -408 +309 @@
     ; * - DR7 (reset to 0x400)
     ; */
-
-    ;/* Save all general purpose host registers. */
-    MYPUSHAD
 
     ;/* Save the Guest CPU context pointer. */
@@ -482 +380 @@
     mov     qword [rax + CPUMCTX.r14], r14
     mov     qword [rax + CPUMCTX.r15], r15
-
-    ; Restore general purpose registers
-    MYPOPAD
 
     mov     eax, VINF_SUCCESS