Index: /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp	(revision 15376)
+++ /trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp	(revision 15377)
@@ -303,6 +303,6 @@
 
         /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
-        * Set required bits to one and zero according to the MSR capabilities.
-        */
+         * Set required bits to one and zero according to the MSR capabilities.
+         */
         val  = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
         /* External and non-maskable interrupts cause VM-exits. */
@@ -314,6 +314,6 @@
 
         /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
-        * Set required bits to one and zero according to the MSR capabilities.
-        */
+         * Set required bits to one and zero according to the MSR capabilities.
+         */
         val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
         /* Program which event cause VM-exits and which features we want to use. */
@@ -363,6 +363,6 @@
         {
             /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
-            * Set required bits to one and zero according to the MSR capabilities.
-            */
+             * Set required bits to one and zero according to the MSR capabilities.
+             */
             val  = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
             val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
@@ -387,38 +387,21 @@
 
         /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
-        * Set required bits to one and zero according to the MSR capabilities.
-        */
+         * Set required bits to one and zero according to the MSR capabilities.
+         */
         rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
         AssertRC(rc);
 
-        /* VMX_VMCS_CTRL_EXIT_CONTROLS
-        * Set required bits to one and zero according to the MSR capabilities.
-        */
-        val  = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
-
-        /* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
-        val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG;
-#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
-        if (VMX_IS_64BIT_HOST_MODE())
-            val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
-        /* else: Must be zero when AMD64 is not available. */
-#endif
-        val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
-        /* Don't acknowledge external interrupts on VM-exit. */
-        rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
-        AssertRC(rc);
-
         /* Forward all exception except #NM & #PF to the guest.
-        * We always need to check pagefaults since our shadow page table can be out of sync.
-        * And we always lazily sync the FPU & XMM state.
-        */
+         * We always need to check pagefaults since our shadow page table can be out of sync.
+         * And we always lazily sync the FPU & XMM state.
+         */
 
         /** @todo Possible optimization:
-        * Keep the FPU and XMM state current in the EM thread. That way there's no need to
-        * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
-        * registers ourselves of course.
-        *
-        * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
-        */
+         * Keep the FPU and XMM state current in the EM thread. That way there's no need to
+         * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
+         * registers ourselves of course.
+         *
+         * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
+         */
 
         /* Don't filter page faults; all of them should cause a switch. */
@@ -1101,4 +1084,43 @@
     X86EFLAGS   eflags;
 
+    /* VMX_VMCS_CTRL_ENTRY_CONTROLS
+     * Set required bits to one and zero according to the MSR capabilities.
+     */
+    val  = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
+    /* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
+    val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG;
+
+    /* 64 bits guest mode? */
+    if (pCtx->msrEFER & MSR_K6_EFER_LMA)
+        val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
+    /* else Must be zero when AMD64 is not available. */
+
+    /* Mask away the bits that the CPU doesn't support */
+    val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
+    rc = VMXWriteCachedVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
+    AssertRC(rc);
+
+    /* VMX_VMCS_CTRL_EXIT_CONTROLS
+     * Set required bits to one and zero according to the MSR capabilities.
+     */
+    val  = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
+
+    /* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
+    val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG;
+#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
+    if (VMX_IS_64BIT_HOST_MODE())
+        val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
+    /* else: Must be zero when AMD64 is not available. */
+#elif HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
+    if (pCtx->msrEFER & MSR_K6_EFER_LMA)
+        val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;      /* our switcher goes to long mode */
+    else
+        val &= ~VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
+#endif
+    val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
+    /* Don't acknowledge external interrupts on VM-exit. */
+    rc = VMXWriteCachedVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
+    AssertRC(rc);
+
     /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
     if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
@@ -1529,21 +1551,4 @@
         STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
     }
-
-    /* VMX_VMCS_CTRL_ENTRY_CONTROLS
-     * Set required bits to one and zero according to the MSR capabilities.
-     */
-    val  = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
-    /* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
-    val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG;
-
-    /* 64 bits guest mode? */
-    if (pCtx->msrEFER & MSR_K6_EFER_LMA)
-        val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
-    /* else Must be zero when AMD64 is not available. */
-
-    /* Mask away the bits that the CPU doesn't support */
-    val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
-    rc = VMXWriteCachedVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
-    AssertRC(rc);
 
     /* 64 bits guest mode? */
@@ -3513,5 +3518,4 @@
     pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
 
-
 #ifdef DEBUG
     pCache->TestIn.pPageCpuPhys = 0;
