Changeset 15394 in vbox

Timestamp:

Dec 12, 2008 7:40:24 PM (16 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

40842

Message:

Workaround for guest EFER load regression, see defect comment 36.

File:

• trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (modified) (4 diffs)

trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

@@ -1090 +1090 @@
     /* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
     val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG;
+    /* Required for the EFER write below, not supported on all CPUs. */ /** @todo Sander, check this. */
+    val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR;
 
     /* 64 bits guest mode? */
@@ -1573 +1575 @@
     }
 
-    /* Unconditionally update the guest EFER. */
-    rc = VMXWriteVMCS64(VMX_VMCS_GUEST_EFER_FULL, pCtx->msrEFER);
-    AssertRC(rc);
+    /* Unconditionally update the guest EFER - on CPUs that supports it. */
+    if (pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1 & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
+    {
+        rc = VMXWriteVMCS64(VMX_VMCS_GUEST_EFER_FULL, pCtx->msrEFER);
+        AssertRC(rc);
+    }
 
     vmxR0UpdateExceptionBitmap(pVM, pVCpu, pCtx);
@@ -3619 +3624 @@
 
 
-#if HC_ARCH_BITS == 32
+#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
 /**
  * Executes VMWRITE
@@ -3717 +3722 @@
 }
 
-#endif
+#endif /* HC_ARCH_BITS == 32 && !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */