Changeset 15490 in vbox for trunk/src

Timestamp:

Dec 15, 2008 10:06:50 AM (16 years ago)

Author:

vboxsync

Message:

Disabled VMX_VMCS_GUEST_EFER_FULL code. (crashes my Nehalem host)

File:

• trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp (modified) (6 diffs)

trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

@@ -994 +994 @@
         AssertRC(rc);
 
+#if 0 /* @todo deal with 32/64 */
+        /* Restore the host EFER - on CPUs that support it. */
+        if (pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1 & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
+        {
+            uint64_t msrEFER = ASMRdMsr(MSR_IA32_EFER);
+            rc = VMXWriteVMCS64(VMX_VMCS_HOST_FIELD_EFER_FULL, msrEFER);
+            AssertRC(rc);
+        }
+#endif
         pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
     }
@@ -1090 +1099 @@
     /* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
     val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG;
-    /* Required for the EFER write below, not supported on all CPUs. */ /** @todo Sander, check this. */
+#if 0 /* @todo deal with 32/64 */
+    /* Required for the EFER write below, not supported on all CPUs. */
     val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR;
-
+#endif
     /* 64 bits guest mode? */
     if (pCtx->msrEFER & MSR_K6_EFER_LMA)
@@ -1109 +1119 @@
 
     /* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
+#if 0 /* @todo deal with 32/64 */
+    val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG | VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR;
+#else
     val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG;
+#endif 
+
 #if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
     if (VMX_IS_64BIT_HOST_MODE())
@@ -1118 +1133 @@
         val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;      /* our switcher goes to long mode */
     else
-        val &= ~VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
+        Assert(!(val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64));
 #endif
     val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
@@ -1581 +1596 @@
     }
 
+#if 0 /* @todo deal with 32/64 */
     /* Unconditionally update the guest EFER - on CPUs that supports it. */
     if (pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1 & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
@@ -1587 +1603 @@
         AssertRC(rc);
     }
+#endif
 
     vmxR0UpdateExceptionBitmap(pVM, pVCpu, pCtx);