Changeset 16108 in vbox

Timestamp:

Jan 21, 2009 12:16:27 AM (16 years ago)

Author:

vboxsync

Message:

CPUM: Fixed 64-bit FPU management on the mac.

Location:

trunk/src/VBox/VMM

Files:

• CPUMInternal.h (modified) (1 diff)
• VMMAll/CPUMAllA.asm (modified) (2 diffs)
• VMMR0/CPUMR0.cpp (modified) (4 diffs)
• VMMR0/CPUMR0A.asm (modified) (4 diffs)

trunk/src/VBox/VMM/CPUMInternal.h

@@ -390 +390 @@
 
 #ifdef IN_RING0
+DECLASM(int)      cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
 DECLASM(int)      cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
 DECLASM(int)      cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);

trunk/src/VBox/VMM/VMMAll/CPUMAllA.asm

@@ -156 +156 @@
 %endif
 %ifndef RT_ARCH_AMD64
-    mov     eax, edx
-    ; Calculate the PCPUM pointer
+    mov     eax, edx                            ; Calculate the PCPUM pointer
     sub     eax, [edx + CPUMCPU.ulOffCPUM]
     test    dword [eax + CPUM.CPUFeatures.edx], X86_CPUID_FEATURE_EDX_FXSR
@@ -179 +178 @@
     fnsave  [xDX + CPUMCPU.Host.fpu]
     or      dword [xDX + CPUMCPU.fUseFlags], dword (CPUM_USED_FPU | CPUM_USED_FPU_SINCE_REM) ; yasm / nasm
-    mov     eax, [xDX + CPUMCPU.Guest.fpu]    ; control word
+    mov     eax, [xDX + CPUMCPU.Guest.fpu]      ; control word
     not     eax                                 ; 1 means exception ignored (6 LS bits)
     and     eax, byte 03Fh                      ; 6 LS bits only
-    test    eax, [xDX + CPUMCPU.Guest.fpu + 4]; status word
+    test    eax, [xDX + CPUMCPU.Guest.fpu + 4]  ; status word
     jz short hlfpua_no_exceptions_pending
     ; technically incorrect, but we certainly don't want any exceptions now!!

trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp

@@ -171 +171 @@
     if (CPUMIsGuestInLongModeEx(pCtx))
     {
-        /* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
-        pVCpu->cpum.s.fUseFlags |= CPUM_SYNC_FPU_STATE;
+        /* Save/Restore the state on entry as we need to be in 64 bits mode to access the full state. */
+        pVCpu->cpum.s.fUseFlags |= CPUM_SYNC_FPU_STATE | CPUM_USED_FPU;
     }
     else
@@ -178 +178 @@
     {
 #ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
+# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL /** @todo remove the #else here and move cpumHandleLazyFPUAsm back to VMMGC after branching out 2.1. */
+        /* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
+        uint64_t SavedEFER = 0;
+        if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
+        {
+            SavedEFER = ASMRdMsr(MSR_K6_EFER);
+            if (SavedEFER & MSR_K6_EFER_FFXSR)
+            {
+                ASMWrMsr(MSR_K6_EFER, SavedEFER & ~MSR_K6_EFER_FFXSR);
+                pVCpu->cpum.s.fUseFlags |= CPUM_MANUAL_XMM_RESTORE;
+            }
+        }
+
+        /* Do the job and record that we've switched FPU state. */
+        cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
+        pVCpu->cpum.s.fUseFlags |= CPUM_USED_FPU;
+
+        /* Restore EFER. */
+        if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
+            ASMWrMsr(MSR_K6_EFER, SavedEFER);
+
+# else
         uint64_t oldMsrEFERHost = 0;
         uint32_t oldCR0 = ASMGetCR0();
@@ -204 +226 @@
             ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost);
 
-            /* CPUMHandleLazyFPU could have changed CR0; restore it. */
+        /* CPUMHandleLazyFPU could have changed CR0; restore it. */
         ASMSetCR0(oldCR0);
+# endif
 
 #else  /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
@@ -236 +259 @@
             }
         }
+
 #endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
     }
 
-    pVCpu->cpum.s.fUseFlags |= CPUM_USED_FPU;
+    pVCpu->cpum.s.fUseFlags |= CPUM_USED_FPU; /** @todo clean up, this is done above by the ASM worker. */
     return VINF_SUCCESS;
 }

trunk/src/VBox/VMM/VMMR0/CPUMR0A.asm

@@ -66 +66 @@
 
 ;;
-; Restores the host's FPU/XMM state
+; Saves the guest FPU/XMM state and restores the host one.
 ;
 ; @returns  0
@@ -72 +72 @@
 ;
 align 16
+BEGINPROC cpumR0SaveHostRestoreGuestFPUState
+%ifdef RT_ARCH_AMD64
+ %ifdef RT_OS_WINDOWS
+    mov     xDX, rcx
+ %else
+    mov     xDX, rdi
+ %endif
+%else
+    mov     xDX, dword [esp + 4]
+%endif
+
+    ; Switch the state.
+    or      dword [xDX + CPUMCPU.fUseFlags], CPUM_USED_FPU
+
+    mov     xAX, cr0                    ; Make sure its safe to access the FPU state.
+    mov     xCX, xAX                    ; save old CR0
+    and     xAX, ~(X86_CR0_TS | X86_CR0_EM)
+    mov     cr0, xAX                    ;; @todo optimize this.
+
+%ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
+    cmp     byte [NAME(g_fCPUMIs64bitHost)], 0
+    jz      .legacy_mode
+    db      0xea                        ; jmp far .sixtyfourbit_mode
+    dd      .sixtyfourbit_mode, NAME(SUPR0Abs64bitKernelCS)
+.legacy_mode:
+%endif ; VBOX_WITH_HYBRID_32BIT_KERNEL
+
+    fxsave  [xDX + CPUMCPU.Host.fpu]    ; ASSUMES that all VT-x/AMD-V boxes sports fxsave/fxrstor
+    fxrstor [xDX + CPUMCPU.Guest.fpu]
+
+.done:
+    mov     cr0, xCX                    ; and restore old CR0 again ;; @todo optimize this.
+.fpu_not_used:
+    xor     eax, eax
+    ret
+
+%ifdef VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0
+ALIGNCODE(16)
+BITS 64
+.sixtyfourbit_mode:
+    and     edx, 0ffffffffh
+    fxsave  [rdx + CPUMCPU.Host.fpu]
+    fxrstor [rdx + CPUMCPU.Guest.fpu]
+    jmp far [.fpret wrt rip]
+.fpret:                                 ; 16:32 Pointer to .the_end.
+    dd      .done, NAME(SUPR0AbsKernelCS)
+BITS 32
+%endif
+ENDPROC   cpumR0SaveHostRestoreGuestFPUState
+
+
+;;
+; Saves the guest FPU/XMM state and restores the host one.
+;
+; @returns  0
+; @param    pCPUMCPU  x86:[esp+4] GCC:rdi MSC:rcx     CPUMCPU pointer
+;
+align 16
 BEGINPROC cpumR0SaveGuestRestoreHostFPUState
 %ifdef RT_ARCH_AMD64
@@ -83 +141 @@
 %endif
 
-    ; Restore FPU if guest has used it.
+    ; Only restore FPU if guest has used it.
     ; Using fxrstor should ensure that we're not causing unwanted exception on the host.
     test    dword [xDX + CPUMCPU.fUseFlags], CPUM_USED_FPU
     jz short .fpu_not_used
 
-    mov     xAX, cr0
+    mov     xAX, cr0                    ; Make sure it's safe to access the FPU state.
     mov     xCX, xAX                    ; save old CR0
     and     xAX, ~(X86_CR0_TS | X86_CR0_EM)
-    mov     cr0, xAX
-
-%ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
-    cmp     byte [NAME(g_fCPUMIs64bitHost)], 0
-    jz      .legacy_mode
-    db      0xea                        ; jmp far .sixtyfourbit_mode
-    dd      .sixtyfourbit_mode, NAME(SUPR0Abs64bitKernelCS)
-.legacy_mode:
-%endif ; VBOX_WITH_HYBRID_32BIT_KERNEL
-
-    fxsave  [xDX + CPUMCPU.Guest.fpu]
+    mov     cr0, xAX                    ;; @todo optimize this.
+
+%ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
+    cmp     byte [NAME(g_fCPUMIs64bitHost)], 0
+    jz      .legacy_mode
+    db      0xea                        ; jmp far .sixtyfourbit_mode
+    dd      .sixtyfourbit_mode, NAME(SUPR0Abs64bitKernelCS)
+.legacy_mode:
+%endif ; VBOX_WITH_HYBRID_32BIT_KERNEL
+
+    fxsave  [xDX + CPUMCPU.Guest.fpu]   ; ASSUMES that all VT-x/AMD-V boxes sports fxsave/fxrstor
     fxrstor [xDX + CPUMCPU.Host.fpu]
 
 .done:
-    mov     cr0, xCX                    ; and restore old CR0 again
+    mov     cr0, xCX                    ; and restore old CR0 again ;; @todo optimize this.
     and     dword [xDX + CPUMCPU.fUseFlags], ~CPUM_USED_FPU
 .fpu_not_used:
@@ -124 +182 @@
 %endif
 ENDPROC   cpumR0SaveGuestRestoreHostFPUState
+
 
 ;;