VirtualBox

Changeset 1679 in vbox for trunk/src/VBox/Devices/Serial


Ignore:
Timestamp:
Mar 23, 2007 1:36:59 PM (18 years ago)
Author:
vboxsync
Message:

Cleaned it up.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Serial/serial.c

    r1476 r1679  
    1 #ifdef VBOX
    21/** @file
    32 *
    … …  
    7372
    7473#define SERIAL_SAVED_STATE_VERSION 2
    75 
    76 #endif /* VBOX */
    77 
    78 #ifndef VBOX
    79 #include "vl.h"
    80 #endif /* !VBOX */
    8174
    8275/* #define DEBUG_SERIAL */
    … …  
    140133       it can be reset while reading iir */
    141134    int thr_ipending;
    142 #ifndef VBOX
    143     SetIRQFunc *set_irq;
    144     void *irq_opaque;
    145 #endif /* !VBOX */
    146135    int irq;
    147 #ifdef VBOX
    148136#ifdef VBOX_SERIAL_PCI
    149137    PCIDEVICE dev;
    … …  
    156144
    157145    RTSEMEVENT ReceiveSem;
    158 #else /* !VBOX */
    159     CharDriverState *chr;
    160 #endif /* !VBOX */
    161146    int last_break_enable;
    162147    target_ulong base;
    163 #ifndef VBOX
    164     int it_shift;
    165 #endif /* !VBOX */
    166148};
    167149
    168 #ifdef VBOX
    169150#ifdef VBOX_SERIAL_PCI
    170151#define PCIDEV_2_SERIALSTATE(pPciDev) ( (SerialState *)((uintptr_t)(pPciDev) - RT_OFFSETOF(SerialState, dev)) )
    … …  
    172153#define PDMIBASE_2_SERIALSTATE(pInstance) ( (SerialState *)((uintptr_t)(pInterface) - RT_OFFSETOF(SerialState, IBase)) )
    173154#define PDMICHARPORT_2_SERIALSTATE(pInstance) ( (SerialState *)((uintptr_t)(pInterface) - RT_OFFSETOF(SerialState, ICharPort)) )
    174 #endif /* VBOX */
    175155
    176156static void serial_update_irq(SerialState *s)
    … …  
    184164    }
    185165    if (s->iir != UART_IIR_NO_INT) {
    186 #ifdef VBOX
    187166#ifdef VBOX_SERIAL_PCI
    188167        PDMDevHlpPCISetIrqNoWait(s->pDevIns, 0, 1);
    … …  
    190169        PDMDevHlpISASetIrqNoWait(s->pDevIns, s->irq, 1);
    191170#endif /* !VBOX_SERIAL_PCI */
    192 #else /* !VBOX */
    193         s->set_irq(s->irq_opaque, s->irq, 1);
    194 #endif /* !VBOX */
    195171    } else {
    196 #ifdef VBOX
    197172#ifdef VBOX_SERIAL_PCI
    198173        PDMDevHlpPCISetIrqNoWait(s->pDevIns, 0, 0);
    … …  
    200175        PDMDevHlpISASetIrqNoWait(s->pDevIns, s->irq, 0);
    201176#endif /* !VBOX_SERIAL_PCI */
    202 #else /* !VBOX */
    203         s->set_irq(s->irq_opaque, s->irq, 0);
    204 #endif /* !VBOX */
    205177    }
    206178}
    … …  
    231203    ssp.data_bits = data_bits;
    232204    ssp.stop_bits = stop_bits;
    233 #ifndef VBOX
    234     qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
    235 #endif /* !VBOX */
    236 #if 0
    237     printf("speed=%d parity=%c data=%d stop=%d\n",
    238            speed, parity, data_bits, stop_bits);
    239 #endif
     205    Log(("speed=%d parity=%c data=%d stop=%d\n", speed, parity, data_bits, stop_bits));
    240206}
    241207
    … …  
    260226            serial_update_irq(s);
    261227            ch = val;
    262 #ifdef VBOX
    263228            /** @todo implement backpressure for writing (don't set interrupt
    264229             * bits/line until the character is actually written). This way
    … …  
    269234                AssertRC(rc);
    270235            }
    271 #else /* !VBOX */
    272             qemu_chr_write(s->chr, &ch, 1);
    273 #endif /* !VBOX */
    274236            s->thr_ipending = 1;
    275237            s->lsr |= UART_LSR_THRE;
    … …  
    300262            if (break_enable != s->last_break_enable) {
    301263                s->last_break_enable = break_enable;
    302 #ifndef VBOX
    303                 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
    304                                &break_enable);
    305 #endif /* !VBOX */
    306264            }
    307265        }
    … …  
    335293            s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
    336294            serial_update_irq(s);
    337 #ifdef VBOX
    338295            {
    339296                int rc = RTSemEventSignal(s->ReceiveSem);
    340297                AssertRC(rc);
    341298            }
    342 #endif /* VBOX */
    343299        }
    344300        break;
    … …  
    387343}
    388344
    389 #ifdef VBOX
    390345static DECLCALLBACK(int) serialNotifyRead(PPDMICHARPORT pInterface, const void *pvBuf, size_t *pcbRead)
    391346{
    … …  
    404359    return VINF_SUCCESS;
    405360}
    406 #else /* !VBOX */
    407 static int serial_can_receive(SerialState *s)
    408 {
    409     return !(s->lsr & UART_LSR_DR);
    410 }
    411 
    412 static void serial_receive_byte(SerialState *s, int ch)
    413 {
    414     s->rbr = ch;
    415     s->lsr |= UART_LSR_DR;
    416     serial_update_irq(s);
    417 }
    418 
    419 static void serial_receive_break(SerialState *s)
    420 {
    421     s->rbr = 0;
    422     s->lsr |= UART_LSR_BI | UART_LSR_DR;
    423     serial_update_irq(s);
    424 }
    425 
    426 static int serial_can_receive1(void *opaque)
    427 {
    428     SerialState *s = opaque;
    429     return serial_can_receive(s);
    430 }
    431 
    432 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
    433 {
    434     SerialState *s = opaque;
    435     serial_receive_byte(s, buf[0]);
    436 }
    437 
    438 static void serial_event(void *opaque, int event)
    439 {
    440     SerialState *s = opaque;
    441     if (event == CHR_EVENT_BREAK)
    442         serial_receive_break(s);
    443 }
    444 
    445 static void serial_save(QEMUFile *f, void *opaque)
    446 {
    447     SerialState *s = opaque;
    448 
    449     qemu_put_be16s(f,&s->divider);
    450     qemu_put_8s(f,&s->rbr);
    451     qemu_put_8s(f,&s->ier);
    452     qemu_put_8s(f,&s->iir);
    453     qemu_put_8s(f,&s->lcr);
    454     qemu_put_8s(f,&s->mcr);
    455     qemu_put_8s(f,&s->lsr);
    456     qemu_put_8s(f,&s->msr);
    457     qemu_put_8s(f,&s->scr);
    458 }
    459 
    460 static int serial_load(QEMUFile *f, void *opaque, int version_id)
    461 {
    462     SerialState *s = opaque;
    463 
    464     if(version_id > 2)
    465         return -EINVAL;
    466 
    467     if (version_id >= 2)
    468         qemu_get_be16s(f, &s->divider);
    469     else
    470         s->divider = qemu_get_byte(f);
    471     qemu_get_8s(f,&s->rbr);
    472     qemu_get_8s(f,&s->ier);
    473     qemu_get_8s(f,&s->iir);
    474     qemu_get_8s(f,&s->lcr);
    475     qemu_get_8s(f,&s->mcr);
    476     qemu_get_8s(f,&s->lsr);
    477     qemu_get_8s(f,&s->msr);
    478     qemu_get_8s(f,&s->scr);
    479 
    480     return 0;
    481 }
    482 
    483 /* If fd is zero, it means that the serial device uses the console */
    484 SerialState *serial_init(SetIRQFunc *set_irq, void *opaque,
    485                          int base, int irq, CharDriverState *chr)
    486 {
    487     SerialState *s;
    488 
    489     s = qemu_mallocz(sizeof(SerialState));
    490     if (!s)
    491         return NULL;
    492     s->set_irq = set_irq;
    493     s->irq_opaque = opaque;
    494     s->irq = irq;
    495     s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
    496     s->iir = UART_IIR_NO_INT;
    497     s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
    498 
    499     register_savevm("serial", base, 2, serial_save, serial_load, s);
    500 
    501     register_ioport_write(base, 8, 1, serial_ioport_write, s);
    502     register_ioport_read(base, 8, 1, serial_ioport_read, s);
    503     s->chr = chr;
    504     qemu_chr_add_read_handler(chr, serial_can_receive1, serial_receive1, s);
    505     qemu_chr_add_event_handler(chr, serial_event);
    506     return s;
    507 }
    508 
    509 /* Memory mapped interface */
    510 static uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
    511 {
    512     SerialState *s = opaque;
    513 
    514     return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
    515 }
    516 
    517 static void serial_mm_writeb (void *opaque,
    518                               target_phys_addr_t addr, uint32_t value)
    519 {
    520     SerialState *s = opaque;
    521 
    522     serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
    523 }
    524 
    525 static uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
    526 {
    527     SerialState *s = opaque;
    528 
    529     return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
    530 }
    531 
    532 static void serial_mm_writew (void *opaque,
    533                               target_phys_addr_t addr, uint32_t value)
    534 {
    535     SerialState *s = opaque;
    536 
    537     serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
    538 }
    539 
    540 static uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
    541 {
    542     SerialState *s = opaque;
    543 
    544     return serial_ioport_read(s, (addr - s->base) >> s->it_shift);
    545 }
    546 
    547 static void serial_mm_writel (void *opaque,
    548                               target_phys_addr_t addr, uint32_t value)
    549 {
    550     SerialState *s = opaque;
    551 
    552     serial_ioport_write(s, (addr - s->base) >> s->it_shift, value);
    553 }
    554 
    555 static CPUReadMemoryFunc *serial_mm_read[] = {
    556     &serial_mm_readb,
    557     &serial_mm_readw,
    558     &serial_mm_readl,
    559 };
    560 
    561 static CPUWriteMemoryFunc *serial_mm_write[] = {
    562     &serial_mm_writeb,
    563     &serial_mm_writew,
    564     &serial_mm_writel,
    565 };
    566 
    567 SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque,
    568                              target_ulong base, int it_shift,
    569                              int irq, CharDriverState *chr)
    570 {
    571     SerialState *s;
    572     int s_io_memory;
    573 
    574     s = qemu_mallocz(sizeof(SerialState));
    575     if (!s)
    576         return NULL;
    577     s->set_irq = set_irq;
    578     s->irq_opaque = opaque;
    579     s->irq = irq;
    580     s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
    581     s->iir = UART_IIR_NO_INT;
    582     s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
    583     s->base = base;
    584     s->it_shift = it_shift;
    585 
    586     register_savevm("serial", base, 2, serial_save, serial_load, s);
    587 
    588     s_io_memory = cpu_register_io_memory(0, serial_mm_read,
    589                                          serial_mm_write, s);
    590     cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
    591     s->chr = chr;
    592     qemu_chr_add_read_handler(chr, serial_can_receive1, serial_receive1, s);
    593     qemu_chr_add_event_handler(chr, serial_event);
    594     return s;
    595 }
    596 #endif
    597 
    598 #ifdef VBOX
     361
    599362static DECLCALLBACK(int) serial_io_write (PPDMDEVINS pDevIns,
    600363                                       void *pvUser,
    … …  
    921684    NULL
    922685};
    923 #endif /* VBOX */
Note: See TracChangeset for help on using the changeset viewer.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette