Changeset 17035 in vbox for trunk/src/VBox/VMM/VMMAll

Timestamp:

Feb 23, 2009 10:26:39 PM (16 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

43248

Message:

VMM,REM: Brushed up the TR/TSS shadowing. We're now relying on the hidden TR registers in SELM and CPUM/REM will make sure these are always in sync. Joined CPUMGetGuestTRHid and CPUMGetGuestTR. Kicked out sync_tr (unused now) and SELMGCGetRing1Stack.

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• CPUMAllRegs.cpp (modified) (3 diffs)
• SELMAll.cpp (modified) (6 diffs)

trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp

@@ -520 +520 @@
 {
     PCPUMCPU pCpumCpu = cpumGetCpumCpu(pVM);
+    AssertMsgFailed(("Need to load the hidden bits too!\n"));
 
     pCpumCpu->Guest.tr  = tr;
@@ -888 +889 @@
 
 
-VMMDECL(RTSEL) CPUMGetGuestTR(PVM pVM)
-{
-    PCPUMCPU pCpumCpu = cpumGetCpumCpu(pVM);
-
+VMMDECL(RTSEL) CPUMGetGuestTR(PVM pVM, PCPUMSELREGHID pHidden)
+{
+    PCPUMCPU pCpumCpu = cpumGetCpumCpu(pVM);
+    if (pHidden)
+        *pHidden = pCpumCpu->Guest.trHid;
     return pCpumCpu->Guest.tr;
 }
@@ -1077 +1079 @@
 
     return pCpumCpu->Guest.eflags.u32;
-}
-
-
-VMMDECL(CPUMSELREGHID *) CPUMGetGuestTRHid(PVM pVM)
-{
-    PCPUMCPU pCpumCpu = cpumGetCpumCpu(pVM);
-
-    return &pCpumCpu->Guest.trHid;
 }
 

trunk/src/VBox/VMM/VMMAll/SELMAll.cpp

@@ -929 +929 @@
     /* Else compatibility or 32 bits mode. */
     return (pHiddenSel->Attr.n.u1DefBig) ? CPUMODE_32BIT : CPUMODE_16BIT;
-
 }
 
@@ -961 +960 @@
  *
  * @param   pVM     VM Handle.
- * @param   ss      Ring1 SS register value.
+ * @param   ss      Ring1 SS register value. Pass 0 if invalid.
  * @param   esp     Ring1 ESP register value.
  */
-VMMDECL(void) SELMSetRing1Stack(PVM pVM, uint32_t ss, RTGCPTR32 esp)
-{
+void selmSetRing1Stack(PVM pVM, uint32_t ss, RTGCPTR32 esp)
+{
+    Assert((ss & 1) || esp == 0);
     pVM->selm.s.Tss.ss1  = ss;
     pVM->selm.s.Tss.esp1 = (uint32_t)esp;
@@ -974 +974 @@
 /**
  * Gets ss:esp for ring1 in main Hypervisor's TSS.
+ *
+ * Returns SS=0 if the ring-1 stack isn't valid.
  *
  * @returns VBox status code.
@@ -979 +981 @@
  * @param   pSS     Ring1 SS register value.
  * @param   pEsp    Ring1 ESP register value.
- *
- * @todo Merge in the GC version of this, eliminating it - or move this to
- *       SELM.cpp, making it SELMR3GetRing1Stack.
  */
 VMMDECL(int) SELMGetRing1Stack(PVM pVM, uint32_t *pSS, PRTGCPTR32 pEsp)
@@ -1040 +1039 @@
 # endif
         /* Update our TSS structure for the guest's ring 1 stack */
-        SELMSetRing1Stack(pVM, tss.ss0 | 1, (RTGCPTR32)tss.esp0);
+        selmSetRing1Stack(pVM, tss.ss0 | 1, (RTGCPTR32)tss.esp0);
         pVM->selm.s.fSyncTSSRing0Stack = false;
     }
@@ -1190 +1189 @@
 VMMDECL(int) SELMGetTSSInfo(PVM pVM, PRTGCUINTPTR pGCPtrTss, PRTGCUINTPTR pcbTss, bool *pfCanHaveIOBitmap)
 {
-    if (!CPUMAreHiddenSelRegsValid(pVM))
-    {
-        /*
-         * Do we have a valid TSS?
-         */
-        if (    pVM->selm.s.GCSelTss == RTSEL_MAX
-            || !pVM->selm.s.fGuestTss32Bit)
-            return VERR_SELM_NO_TSS;
-
-        /*
-         * Fill in return values.
-         */
-        *pGCPtrTss = (RTGCUINTPTR)pVM->selm.s.GCPtrGuestTss;
-        *pcbTss = pVM->selm.s.cbGuestTss;
-        if (pfCanHaveIOBitmap)
-            *pfCanHaveIOBitmap = pVM->selm.s.fGuestTss32Bit;
-    }
-    else
-    {
-        CPUMSELREGHID *pHiddenTRReg;
-
-        pHiddenTRReg = CPUMGetGuestTRHid(pVM);
-
-        *pGCPtrTss = pHiddenTRReg->u64Base;
-        *pcbTss    = pHiddenTRReg->u32Limit;
-
-        if (pfCanHaveIOBitmap)
-            *pfCanHaveIOBitmap =  pHiddenTRReg->Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
-                               || pHiddenTRReg->Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
-    }
+    /*
+     * The TR hidden register is always valid.
+     */
+    CPUMSELREGHID trHid;
+    RTSEL tr = CPUMGetGuestTR(pVM, &trHid);
+    if (!(tr & X86_SEL_MASK))
+        return VERR_SELM_NO_TSS;
+
+    *pGCPtrTss = trHid.u64Base;
+    *pcbTss    = trHid.u32Limit + (trHid.u32Limit != UINT32_MAX); /* be careful. */
+    if (pfCanHaveIOBitmap)
+        *pfCanHaveIOBitmap = trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
+                          || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
     return VINF_SUCCESS;
 }