Index: trunk/include/VBox/cpum.h
===================================================================
--- trunk/include/VBox/cpum.h	(revision 18842)
+++ trunk/include/VBox/cpum.h	(revision 18927)
@@ -620,37 +620,37 @@
 /** @name Guest Register Getters.
  * @{ */
-VMMDECL(void)       CPUMGetGuestGDTR(PVM pVM, PVBOXGDTR pGDTR);
-VMMDECL(RTGCPTR)    CPUMGetGuestIDTR(PVM pVM, uint16_t *pcbLimit);
-VMMDECL(RTSEL)      CPUMGetGuestTR(PVM pVM, PCPUMSELREGHID pHidden);
-VMMDECL(RTSEL)      CPUMGetGuestLDTR(PVM pVM);
-VMMDECL(uint64_t)   CPUMGetGuestCR0(PVM pVM);
-VMMDECL(uint64_t)   CPUMGetGuestCR2(PVM pVM);
-VMMDECL(uint64_t)   CPUMGetGuestCR3(PVM pVM);
-VMMDECL(uint64_t)   CPUMGetGuestCR4(PVM pVM);
-VMMDECL(int)        CPUMGetGuestCRx(PVM pVM, unsigned iReg, uint64_t *pValue);
-VMMDECL(uint32_t)   CPUMGetGuestEFlags(PVM pVM);
-VMMDECL(uint32_t)   CPUMGetGuestEIP(PVM pVM);
-VMMDECL(uint64_t)   CPUMGetGuestRIP(PVM pVM);
-VMMDECL(uint32_t)   CPUMGetGuestEAX(PVM pVM);
-VMMDECL(uint32_t)   CPUMGetGuestEBX(PVM pVM);
-VMMDECL(uint32_t)   CPUMGetGuestECX(PVM pVM);
-VMMDECL(uint32_t)   CPUMGetGuestEDX(PVM pVM);
-VMMDECL(uint32_t)   CPUMGetGuestESI(PVM pVM);
-VMMDECL(uint32_t)   CPUMGetGuestEDI(PVM pVM);
-VMMDECL(uint32_t)   CPUMGetGuestESP(PVM pVM);
-VMMDECL(uint32_t)   CPUMGetGuestEBP(PVM pVM);
-VMMDECL(RTSEL)      CPUMGetGuestCS(PVM pVM);
-VMMDECL(RTSEL)      CPUMGetGuestDS(PVM pVM);
-VMMDECL(RTSEL)      CPUMGetGuestES(PVM pVM);
-VMMDECL(RTSEL)      CPUMGetGuestFS(PVM pVM);
-VMMDECL(RTSEL)      CPUMGetGuestGS(PVM pVM);
-VMMDECL(RTSEL)      CPUMGetGuestSS(PVM pVM);
-VMMDECL(uint64_t)   CPUMGetGuestDR0(PVM pVM);
-VMMDECL(uint64_t)   CPUMGetGuestDR1(PVM pVM);
-VMMDECL(uint64_t)   CPUMGetGuestDR2(PVM pVM);
-VMMDECL(uint64_t)   CPUMGetGuestDR3(PVM pVM);
-VMMDECL(uint64_t)   CPUMGetGuestDR6(PVM pVM);
-VMMDECL(uint64_t)   CPUMGetGuestDR7(PVM pVM);
-VMMDECL(int)        CPUMGetGuestDRx(PVM pVM, uint32_t iReg, uint64_t *pValue);
+VMMDECL(void)       CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR);
+VMMDECL(RTGCPTR)    CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
+VMMDECL(RTSEL)      CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden);
+VMMDECL(RTSEL)      CPUMGetGuestLDTR(PVMCPU pVCpu);
+VMMDECL(uint64_t)   CPUMGetGuestCR0(PVMCPU pVCpu);
+VMMDECL(uint64_t)   CPUMGetGuestCR2(PVMCPU pVCpu);
+VMMDECL(uint64_t)   CPUMGetGuestCR3(PVMCPU pVCpu);
+VMMDECL(uint64_t)   CPUMGetGuestCR4(PVMCPU pVCpu);
+VMMDECL(int)        CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue);
+VMMDECL(uint32_t)   CPUMGetGuestEFlags(PVMCPU pVCpu);
+VMMDECL(uint32_t)   CPUMGetGuestEIP(PVMCPU pVCpu);
+VMMDECL(uint64_t)   CPUMGetGuestRIP(PVMCPU pVCpu);
+VMMDECL(uint32_t)   CPUMGetGuestEAX(PVMCPU pVCpu);
+VMMDECL(uint32_t)   CPUMGetGuestEBX(PVMCPU pVCpu);
+VMMDECL(uint32_t)   CPUMGetGuestECX(PVMCPU pVCpu);
+VMMDECL(uint32_t)   CPUMGetGuestEDX(PVMCPU pVCpu);
+VMMDECL(uint32_t)   CPUMGetGuestESI(PVMCPU pVCpu);
+VMMDECL(uint32_t)   CPUMGetGuestEDI(PVMCPU pVCpu);
+VMMDECL(uint32_t)   CPUMGetGuestESP(PVMCPU pVCpu);
+VMMDECL(uint32_t)   CPUMGetGuestEBP(PVMCPU pVCpu);
+VMMDECL(RTSEL)      CPUMGetGuestCS(PVMCPU pVCpu);
+VMMDECL(RTSEL)      CPUMGetGuestDS(PVMCPU pVCpu);
+VMMDECL(RTSEL)      CPUMGetGuestES(PVMCPU pVCpu);
+VMMDECL(RTSEL)      CPUMGetGuestFS(PVMCPU pVCpu);
+VMMDECL(RTSEL)      CPUMGetGuestGS(PVMCPU pVCpu);
+VMMDECL(RTSEL)      CPUMGetGuestSS(PVMCPU pVCpu);
+VMMDECL(uint64_t)   CPUMGetGuestDR0(PVMCPU pVCpu);
+VMMDECL(uint64_t)   CPUMGetGuestDR1(PVMCPU pVCpu);
+VMMDECL(uint64_t)   CPUMGetGuestDR2(PVMCPU pVCpu);
+VMMDECL(uint64_t)   CPUMGetGuestDR3(PVMCPU pVCpu);
+VMMDECL(uint64_t)   CPUMGetGuestDR6(PVMCPU pVCpu);
+VMMDECL(uint64_t)   CPUMGetGuestDR7(PVMCPU pVCpu);
+VMMDECL(int)        CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue);
 VMMDECL(void)       CPUMGetGuestCpuId(PVM pVM, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
 VMMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdStdRCPtr(PVM pVM);
@@ -661,47 +661,47 @@
 VMMDECL(uint32_t)   CPUMGetGuestCpuIdExtMax(PVM pVM);
 VMMDECL(uint32_t)   CPUMGetGuestCpuIdCentaurMax(PVM pVM);
-VMMDECL(uint64_t)   CPUMGetGuestEFER(PVM pVM);
-VMMDECL(uint64_t)   CPUMGetGuestMsr(PVM pVM, unsigned idMsr);
-VMMDECL(void)       CPUMSetGuestMsr(PVM pVM, unsigned idMsr, uint64_t valMsr);
+VMMDECL(uint64_t)   CPUMGetGuestEFER(PVMCPU pVCpu);
+VMMDECL(uint64_t)   CPUMGetGuestMsr(PVMCPU pVCpu, unsigned idMsr);
+VMMDECL(void)       CPUMSetGuestMsr(PVMCPU pVCpu, unsigned idMsr, uint64_t valMsr);
 /** @} */
 
 /** @name Guest Register Setters.
  * @{ */
-VMMDECL(int)        CPUMSetGuestGDTR(PVM pVM, uint32_t addr, uint16_t limit);
-VMMDECL(int)        CPUMSetGuestIDTR(PVM pVM, uint32_t addr, uint16_t limit);
-VMMDECL(int)        CPUMSetGuestTR(PVM pVM, uint16_t tr);
-VMMDECL(int)        CPUMSetGuestLDTR(PVM pVM, uint16_t ldtr);
-VMMDECL(int)        CPUMSetGuestCR0(PVM pVM, uint64_t cr0);
-VMMDECL(int)        CPUMSetGuestCR2(PVM pVM, uint64_t cr2);
-VMMDECL(int)        CPUMSetGuestCR3(PVM pVM, uint64_t cr3);
-VMMDECL(int)        CPUMSetGuestCR4(PVM pVM, uint64_t cr4);
-VMMDECL(int)        CPUMSetGuestDR0(PVM pVM, uint64_t uDr0);
-VMMDECL(int)        CPUMSetGuestDR1(PVM pVM, uint64_t uDr1);
-VMMDECL(int)        CPUMSetGuestDR2(PVM pVM, uint64_t uDr2);
-VMMDECL(int)        CPUMSetGuestDR3(PVM pVM, uint64_t uDr3);
-VMMDECL(int)        CPUMSetGuestDR6(PVM pVM, uint64_t uDr6);
-VMMDECL(int)        CPUMSetGuestDR7(PVM pVM, uint64_t uDr7);
-VMMDECL(int)        CPUMSetGuestDRx(PVM pVM, uint32_t iReg, uint64_t Value);
-VMMDECL(int)        CPUMSetGuestEFlags(PVM pVM, uint32_t eflags);
-VMMDECL(int)        CPUMSetGuestEIP(PVM pVM, uint32_t eip);
-VMMDECL(int)        CPUMSetGuestEAX(PVM pVM, uint32_t eax);
-VMMDECL(int)        CPUMSetGuestEBX(PVM pVM, uint32_t ebx);
-VMMDECL(int)        CPUMSetGuestECX(PVM pVM, uint32_t ecx);
-VMMDECL(int)        CPUMSetGuestEDX(PVM pVM, uint32_t edx);
-VMMDECL(int)        CPUMSetGuestESI(PVM pVM, uint32_t esi);
-VMMDECL(int)        CPUMSetGuestEDI(PVM pVM, uint32_t edi);
-VMMDECL(int)        CPUMSetGuestESP(PVM pVM, uint32_t esp);
-VMMDECL(int)        CPUMSetGuestEBP(PVM pVM, uint32_t ebp);
-VMMDECL(int)        CPUMSetGuestCS(PVM pVM, uint16_t cs);
-VMMDECL(int)        CPUMSetGuestDS(PVM pVM, uint16_t ds);
-VMMDECL(int)        CPUMSetGuestES(PVM pVM, uint16_t es);
-VMMDECL(int)        CPUMSetGuestFS(PVM pVM, uint16_t fs);
-VMMDECL(int)        CPUMSetGuestGS(PVM pVM, uint16_t gs);
-VMMDECL(int)        CPUMSetGuestSS(PVM pVM, uint16_t ss);
-VMMDECL(void)       CPUMSetGuestEFER(PVM pVM, uint64_t val);
+VMMDECL(int)        CPUMSetGuestGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
+VMMDECL(int)        CPUMSetGuestIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
+VMMDECL(int)        CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr);
+VMMDECL(int)        CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr);
+VMMDECL(int)        CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0);
+VMMDECL(int)        CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2);
+VMMDECL(int)        CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3);
+VMMDECL(int)        CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4);
+VMMDECL(int)        CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0);
+VMMDECL(int)        CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1);
+VMMDECL(int)        CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2);
+VMMDECL(int)        CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3);
+VMMDECL(int)        CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6);
+VMMDECL(int)        CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7);
+VMMDECL(int)        CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value);
+VMMDECL(int)        CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags);
+VMMDECL(int)        CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip);
+VMMDECL(int)        CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax);
+VMMDECL(int)        CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx);
+VMMDECL(int)        CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx);
+VMMDECL(int)        CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx);
+VMMDECL(int)        CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi);
+VMMDECL(int)        CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi);
+VMMDECL(int)        CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp);
+VMMDECL(int)        CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp);
+VMMDECL(int)        CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs);
+VMMDECL(int)        CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds);
+VMMDECL(int)        CPUMSetGuestES(PVMCPU pVCpu, uint16_t es);
+VMMDECL(int)        CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs);
+VMMDECL(int)        CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs);
+VMMDECL(int)        CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss);
+VMMDECL(void)       CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val);
 VMMDECL(void)       CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
 VMMDECL(void)       CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
 VMMDECL(bool)       CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
-VMMDECL(void)       CPUMSetGuestCtx(PVM pVM, const PCPUMCTX pCtx);
+VMMDECL(void)       CPUMSetGuestCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
 /** @} */
 
@@ -710,6 +710,6 @@
 
 
-VMMDECL(bool)       CPUMIsGuestIn16BitCode(PVM pVM);
-VMMDECL(bool)       CPUMIsGuestIn32BitCode(PVM pVM);
+VMMDECL(bool)       CPUMIsGuestIn16BitCode(PVMCPU pVCpu);
+VMMDECL(bool)       CPUMIsGuestIn32BitCode(PVMCPU pVCpu);
 VMMDECL(CPUMCPUVENDOR) CPUMGetCPUVendor(PVM pVM);
 
@@ -720,7 +720,7 @@
  * @param   pVM     The VM handle.
  */
-DECLINLINE(bool) CPUMIsGuestInRealMode(PVM pVM)
-{
-    return !(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
+DECLINLINE(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu)
+{
+    return !(CPUMGetGuestCR0(pVCpu) & X86_CR0_PE);
 }
 
@@ -742,7 +742,7 @@
  * @param   pVM     The VM handle.
  */
-DECLINLINE(bool) CPUMIsGuestInProtectedMode(PVM pVM)
-{
-    return !!(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
+DECLINLINE(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu)
+{
+    return !!(CPUMGetGuestCR0(pVCpu) & X86_CR0_PE);
 }
 
@@ -753,7 +753,7 @@
  * @param   pVM     The VM handle.
  */
-DECLINLINE(bool) CPUMIsGuestInPagedProtectedMode(PVM pVM)
-{
-    return (CPUMGetGuestCR0(pVM) & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
+DECLINLINE(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu)
+{
+    return (CPUMGetGuestCR0(pVCpu) & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
 }
 
@@ -775,7 +775,7 @@
  * @param   pVM     The VM handle.
  */
-DECLINLINE(bool) CPUMIsGuestInLongMode(PVM pVM)
-{
-    return (CPUMGetGuestEFER(pVM) & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
+DECLINLINE(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu)
+{
+    return (CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
 }
 
@@ -798,7 +798,7 @@
  * @param   pCtx    Current CPU context
  */
-DECLINLINE(bool) CPUMIsGuestIn64BitCode(PVM pVM, PCCPUMCTXCORE pCtx)
-{
-    if (!CPUMIsGuestInLongMode(pVM))
+DECLINLINE(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu, PCCPUMCTXCORE pCtx)
+{
+    if (!CPUMIsGuestInLongMode(pVCpu))
         return false;
 
@@ -827,9 +827,9 @@
  * @param   pVM     The VM handle.
  */
-DECLINLINE(bool) CPUMIsGuestInPAEMode(PVM pVM)
-{
-    return (    CPUMIsGuestInPagedProtectedMode(pVM)
-            &&  (CPUMGetGuestCR4(pVM) & X86_CR4_PAE)
-            &&  !CPUMIsGuestInLongMode(pVM));
+DECLINLINE(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu)
+{
+    return (    CPUMIsGuestInPagedProtectedMode(pVCpu)
+            &&  (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
+            &&  !CPUMIsGuestInLongMode(pVCpu));
 }
 
@@ -852,83 +852,81 @@
 /** @name Hypervisor Register Getters.
  * @{ */
-VMMDECL(RTSEL)          CPUMGetHyperCS(PVM pVM);
-VMMDECL(RTSEL)          CPUMGetHyperDS(PVM pVM);
-VMMDECL(RTSEL)          CPUMGetHyperES(PVM pVM);
-VMMDECL(RTSEL)          CPUMGetHyperFS(PVM pVM);
-VMMDECL(RTSEL)          CPUMGetHyperGS(PVM pVM);
-VMMDECL(RTSEL)          CPUMGetHyperSS(PVM pVM);
+VMMDECL(RTSEL)          CPUMGetHyperCS(PVMCPU pVCpu);
+VMMDECL(RTSEL)          CPUMGetHyperDS(PVMCPU pVCpu);
+VMMDECL(RTSEL)          CPUMGetHyperES(PVMCPU pVCpu);
+VMMDECL(RTSEL)          CPUMGetHyperFS(PVMCPU pVCpu);
+VMMDECL(RTSEL)          CPUMGetHyperGS(PVMCPU pVCpu);
+VMMDECL(RTSEL)          CPUMGetHyperSS(PVMCPU pVCpu);
 #if 0 /* these are not correct. */
-VMMDECL(uint32_t)       CPUMGetHyperCR0(PVM pVM);
-VMMDECL(uint32_t)       CPUMGetHyperCR2(PVM pVM);
-VMMDECL(uint32_t)       CPUMGetHyperCR3(PVM pVM);
-VMMDECL(uint32_t)       CPUMGetHyperCR4(PVM pVM);
+VMMDECL(uint32_t)       CPUMGetHyperCR0(PVMCPU pVCpu);
+VMMDECL(uint32_t)       CPUMGetHyperCR2(PVMCPU pVCpu);
+VMMDECL(uint32_t)       CPUMGetHyperCR3(PVMCPU pVCpu);
+VMMDECL(uint32_t)       CPUMGetHyperCR4(PVMCPU pVCpu);
 #endif
 /** This register is only saved on fatal traps. */
-VMMDECL(uint32_t)       CPUMGetHyperEAX(PVM pVM);
-VMMDECL(uint32_t)       CPUMGetHyperEBX(PVM pVM);
+VMMDECL(uint32_t)       CPUMGetHyperEAX(PVMCPU pVCpu);
+VMMDECL(uint32_t)       CPUMGetHyperEBX(PVMCPU pVCpu);
 /** This register is only saved on fatal traps. */
-VMMDECL(uint32_t)       CPUMGetHyperECX(PVM pVM);
+VMMDECL(uint32_t)       CPUMGetHyperECX(PVMCPU pVCpu);
 /** This register is only saved on fatal traps. */
-VMMDECL(uint32_t)       CPUMGetHyperEDX(PVM pVM);
-VMMDECL(uint32_t)       CPUMGetHyperESI(PVM pVM);
-VMMDECL(uint32_t)       CPUMGetHyperEDI(PVM pVM);
-VMMDECL(uint32_t)       CPUMGetHyperEBP(PVM pVM);
-VMMDECL(uint32_t)       CPUMGetHyperESP(PVM pVM);
-VMMDECL(uint32_t)       CPUMGetHyperEFlags(PVM pVM);
-VMMDECL(uint32_t)       CPUMGetHyperEIP(PVM pVM);
-VMMDECL(uint64_t)       CPUMGetHyperRIP(PVM pVM);
-VMMDECL(uint32_t)       CPUMGetHyperIDTR(PVM pVM, uint16_t *pcbLimit);
-VMMDECL(uint32_t)       CPUMGetHyperGDTR(PVM pVM, uint16_t *pcbLimit);
-VMMDECL(RTSEL)          CPUMGetHyperLDTR(PVM pVM);
-VMMDECL(RTGCUINTREG)    CPUMGetHyperDR0(PVM pVM);
-VMMDECL(RTGCUINTREG)    CPUMGetHyperDR1(PVM pVM);
-VMMDECL(RTGCUINTREG)    CPUMGetHyperDR2(PVM pVM);
-VMMDECL(RTGCUINTREG)    CPUMGetHyperDR3(PVM pVM);
-VMMDECL(RTGCUINTREG)    CPUMGetHyperDR6(PVM pVM);
-VMMDECL(RTGCUINTREG)    CPUMGetHyperDR7(PVM pVM);
-VMMDECL(void)           CPUMGetHyperCtx(PVM pVM, PCPUMCTX pCtx);
-VMMDECL(uint32_t)       CPUMGetHyperCR3(PVM pVM);
+VMMDECL(uint32_t)       CPUMGetHyperEDX(PVMCPU pVCpu);
+VMMDECL(uint32_t)       CPUMGetHyperESI(PVMCPU pVCpu);
+VMMDECL(uint32_t)       CPUMGetHyperEDI(PVMCPU pVCpu);
+VMMDECL(uint32_t)       CPUMGetHyperEBP(PVMCPU pVCpu);
+VMMDECL(uint32_t)       CPUMGetHyperESP(PVMCPU pVCpu);
+VMMDECL(uint32_t)       CPUMGetHyperEFlags(PVMCPU pVCpu);
+VMMDECL(uint32_t)       CPUMGetHyperEIP(PVMCPU pVCpu);
+VMMDECL(uint64_t)       CPUMGetHyperRIP(PVMCPU pVCpu);
+VMMDECL(uint32_t)       CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
+VMMDECL(uint32_t)       CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
+VMMDECL(RTSEL)          CPUMGetHyperLDTR(PVMCPU pVCpu);
+VMMDECL(RTGCUINTREG)    CPUMGetHyperDR0(PVMCPU pVCpu);
+VMMDECL(RTGCUINTREG)    CPUMGetHyperDR1(PVMCPU pVCpu);
+VMMDECL(RTGCUINTREG)    CPUMGetHyperDR2(PVMCPU pVCpu);
+VMMDECL(RTGCUINTREG)    CPUMGetHyperDR3(PVMCPU pVCpu);
+VMMDECL(RTGCUINTREG)    CPUMGetHyperDR6(PVMCPU pVCpu);
+VMMDECL(RTGCUINTREG)    CPUMGetHyperDR7(PVMCPU pVCpu);
+VMMDECL(void)           CPUMGetHyperCtx(PVMCPU pVCpu, PCPUMCTX pCtx);
+VMMDECL(uint32_t)       CPUMGetHyperCR3(PVMCPU pVCpu);
 /** @} */
 
 /** @name Hypervisor Register Setters.
  * @{ */
-VMMDECL(void)           CPUMSetHyperGDTR(PVM pVM, uint32_t addr, uint16_t limit);
-VMMDECL(void)           CPUMSetHyperLDTR(PVM pVM, RTSEL SelLDTR);
-VMMDECL(void)           CPUMSetHyperIDTR(PVM pVM, uint32_t addr, uint16_t limit);
-VMMDECL(void)           CPUMSetHyperCR3(PVM pVM, uint32_t cr3);
-VMMDECL(void)           CPUMSetHyperTR(PVM pVM, RTSEL SelTR);
-VMMDECL(void)           CPUMSetHyperCS(PVM pVM, RTSEL SelCS);
-VMMDECL(void)           CPUMSetHyperDS(PVM pVM, RTSEL SelDS);
-VMMDECL(void)           CPUMSetHyperES(PVM pVM, RTSEL SelDS);
-VMMDECL(void)           CPUMSetHyperFS(PVM pVM, RTSEL SelDS);
-VMMDECL(void)           CPUMSetHyperGS(PVM pVM, RTSEL SelDS);
-VMMDECL(void)           CPUMSetHyperSS(PVM pVM, RTSEL SelSS);
-VMMDECL(void)           CPUMSetHyperESP(PVM pVM, uint32_t u32ESP);
-VMMDECL(int)            CPUMSetHyperEFlags(PVM pVM, uint32_t Efl);
-VMMDECL(void)           CPUMSetHyperEIP(PVM pVM, uint32_t u32EIP);
-VMMDECL(void)           CPUMSetHyperDR0(PVM pVM, RTGCUINTREG uDr0);
-VMMDECL(void)           CPUMSetHyperDR1(PVM pVM, RTGCUINTREG uDr1);
-VMMDECL(void)           CPUMSetHyperDR2(PVM pVM, RTGCUINTREG uDr2);
-VMMDECL(void)           CPUMSetHyperDR3(PVM pVM, RTGCUINTREG uDr3);
-VMMDECL(void)           CPUMSetHyperDR6(PVM pVM, RTGCUINTREG uDr6);
-VMMDECL(void)           CPUMSetHyperDR7(PVM pVM, RTGCUINTREG uDr7);
-VMMDECL(void)           CPUMSetHyperCtx(PVM pVM, const PCPUMCTX pCtx);
-VMMDECL(int)            CPUMRecalcHyperDRx(PVM pVM);
+VMMDECL(void)           CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
+VMMDECL(void)           CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR);
+VMMDECL(void)           CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
+VMMDECL(void)           CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3);
+VMMDECL(void)           CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR);
+VMMDECL(void)           CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS);
+VMMDECL(void)           CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS);
+VMMDECL(void)           CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelDS);
+VMMDECL(void)           CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelDS);
+VMMDECL(void)           CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelDS);
+VMMDECL(void)           CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS);
+VMMDECL(void)           CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP);
+VMMDECL(int)            CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl);
+VMMDECL(void)           CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP);
+VMMDECL(void)           CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0);
+VMMDECL(void)           CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1);
+VMMDECL(void)           CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2);
+VMMDECL(void)           CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3);
+VMMDECL(void)           CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6);
+VMMDECL(void)           CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7);
+VMMDECL(void)           CPUMSetHyperCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
+VMMDECL(int)            CPUMRecalcHyperDRx(PVMCPU pVCpu);
 /** @} */
 
-VMMDECL(void)           CPUMPushHyper(PVM pVM, uint32_t u32);
-VMMDECL(void)           CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore);
-VMMDECL(PCPUMCTX)       CPUMQueryGuestCtxPtr(PVM pVM);
-VMMDECL(PCPUMCTX)       CPUMQueryGuestCtxPtrEx(PVM pVM, PVMCPU pVCpu);
-VMMDECL(int)            CPUMQueryHyperCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
-VMMDECL(PCCPUMCTXCORE)  CPUMGetGuestCtxCore(PVM pVM);
-VMMDECL(PCCPUMCTXCORE)  CPUMGetGuestCtxCoreEx(PVM pVM, PVMCPU pVCpu);
-VMMDECL(PCCPUMCTXCORE)  CPUMGetHyperCtxCore(PVM pVM);
-VMMDECL(void)           CPUMSetGuestCtxCore(PVM pVM, PCCPUMCTXCORE pCtxCore);
-VMMDECL(int)            CPUMRawEnter(PVM pVM, PCPUMCTXCORE pCtxCore);
-VMMDECL(int)            CPUMRawLeave(PVM pVM, PCPUMCTXCORE pCtxCore, int rc);
-VMMDECL(uint32_t)       CPUMRawGetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore);
-VMMDECL(void)           CPUMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t eflags);
-VMMDECL(int)            CPUMHandleLazyFPU(PVM pVM, PVMCPU pVCpu);
+VMMDECL(void)           CPUMPushHyper(PVMCPU pVCpu, uint32_t u32);
+VMMDECL(void)           CPUMHyperSetCtxCore(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
+VMMDECL(int)            CPUMQueryHyperCtxPtr(PVMCPU pVCpu, PCPUMCTX *ppCtx);
+VMMDECL(PCCPUMCTXCORE)  CPUMGetHyperCtxCore(PVMCPU pVCpu);
+VMMDECL(PCPUMCTX)       CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
+VMMDECL(PCCPUMCTXCORE)  CPUMGetGuestCtxCore(PVMCPU pVCpu);
+VMMDECL(void)           CPUMSetGuestCtxCore(PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore);
+VMMDECL(int)            CPUMRawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
+VMMDECL(int)            CPUMRawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc);
+VMMDECL(uint32_t)       CPUMRawGetEFlags(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
+VMMDECL(void)           CPUMRawSetEFlags(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t eflags);
+VMMDECL(int)            CPUMHandleLazyFPU(PVMCPU pVCpu);
 
 /** @name Changed flags
@@ -953,16 +951,15 @@
 /** @} */
 
-VMMDECL(unsigned)       CPUMGetAndClearChangedFlagsREM(PVM pVM);
-VMMDECL(void)           CPUMSetChangedFlags(PVM pVM, uint32_t fChangedFlags);
+VMMDECL(unsigned)       CPUMGetAndClearChangedFlagsREM(PVMCPU pVCpu);
+VMMDECL(void)           CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags);
 VMMDECL(bool)           CPUMSupportsFXSR(PVM pVM);
 VMMDECL(bool)           CPUMIsHostUsingSysEnter(PVM pVM);
 VMMDECL(bool)           CPUMIsHostUsingSysCall(PVM pVM);
 VMMDECL(bool)           CPUMIsGuestFPUStateActive(PVMCPU pVCPU);
-VMMDECL(void)           CPUMDeactivateGuestFPUState(PVM pVM);
-VMMDECL(bool)           CPUMIsGuestDebugStateActive(PVM pVM);
-VMMDECL(void)           CPUMDeactivateGuestDebugState(PVM pVM);
+VMMDECL(void)           CPUMDeactivateGuestFPUState(PVMCPU pVCpu);
+VMMDECL(bool)           CPUMIsGuestDebugStateActive(PVMCPU pVCpu);
+VMMDECL(void)           CPUMDeactivateGuestDebugState(PVMCPU pVCpu);
+VMMDECL(uint32_t)       CPUMGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
 VMMDECL(bool)           CPUMAreHiddenSelRegsValid(PVM pVM);
-VMMDECL(void)           CPUMSetHiddenSelRegsValid(PVM pVM, bool fValid);
-VMMDECL(uint32_t)       CPUMGetGuestCPL(PVM pVM, PCPUMCTXCORE pCtxCore);
 
 /**
@@ -981,5 +978,5 @@
 } CPUMMODE;
 
-VMMDECL(CPUMMODE)  CPUMGetGuestMode(PVM pVM);
+VMMDECL(CPUMMODE)  CPUMGetGuestMode(PVMCPU pVCpu);
 
 
Index: trunk/include/VBox/cpumdis.h
===================================================================
--- trunk/include/VBox/cpumdis.h	(revision 18842)
+++ trunk/include/VBox/cpumdis.h	(revision 18927)
@@ -44,16 +44,12 @@
 
 #ifdef IN_RING3
-VMMR3DECL(int)  CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix);
+VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix);
 
 # ifdef DEBUG
 /** @deprecated  Use DBGFR3DisasInstrCurrentLog().  */
-VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix);
-/** @deprecated  Create new DBGFR3Disas function to do this. */
-VMMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix, int nrInstructions);
+VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix);
 # else
 /** @deprecated  Use DBGFR3DisasInstrCurrentLog(). */
-#  define CPUMR3DisasmInstr(pVM, pCtx, pc, pszPrefix)                   do {} while (0)
-/** @deprecated  Create new DBGFR3Disas function to do this. */
-#  define CPUMR3DisasmBlock(pVM, pCtx, pc, pszPrefix, nrInstructions)   do {} while (0)
+#  define CPUMR3DisasmInstr(pVM, pVCpu, pCtx, pc, pszPrefix)                   do {} while (0)
 # endif
 
Index: trunk/include/VBox/dbgf.h
===================================================================
--- trunk/include/VBox/dbgf.h	(revision 18842)
+++ trunk/include/VBox/dbgf.h	(revision 18927)
@@ -766,6 +766,6 @@
 #define DBGF_SEL_FLAT                       1
 
-VMMR3DECL(int) DBGFR3DisasInstrEx(PVM pVM, RTSEL Sel, RTGCPTR GCPtr, unsigned fFlags, char *pszOutput, uint32_t cchOutput, uint32_t *pcbInstr);
-VMMR3DECL(int) DBGFR3DisasInstr(PVM pVM, RTSEL Sel, RTGCPTR GCPtr, char *pszOutput, uint32_t cbOutput);
+VMMR3DECL(int) DBGFR3DisasInstrEx(PVM pVM, PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr, unsigned fFlags, char *pszOutput, uint32_t cchOutput, uint32_t *pcbInstr);
+VMMR3DECL(int) DBGFR3DisasInstr(PVM pVM, PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr, char *pszOutput, uint32_t cbOutput);
 VMMR3DECL(int) DBGFR3DisasInstrCurrent(PVM pVM, char *pszOutput, uint32_t cbOutput);
 VMMR3DECL(int) DBGFR3DisasInstrCurrentLogInternal(PVM pVM, const char *pszPrefix);
@@ -785,5 +785,5 @@
 #endif
 
-VMMR3DECL(int) DBGFR3DisasInstrLogInternal(PVM pVM, RTSEL Sel, RTGCPTR GCPtr);
+VMMR3DECL(int) DBGFR3DisasInstrLogInternal(PVM pVM, PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr);
 
 /** @def DBGFR3DisasInstrLog
@@ -805,4 +805,6 @@
 VMMR3DECL(int) DBGFR3MemRead(PVM pVM, PCDBGFADDRESS pAddress, void *pvBuf, size_t cbRead);
 VMMR3DECL(int) DBGFR3MemReadString(PVM pVM, PCDBGFADDRESS pAddress, char *pszBuf, size_t cbBuf);
+VMMR3DECL(int) DBGFR3ReadGCVirt(PVM pVM, PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtr, size_t cb);
+VMMR3DECL(int) DBGFR3WriteGCVirt(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
 
 
Index: trunk/include/VBox/em.h
===================================================================
--- trunk/include/VBox/em.h	(revision 18842)
+++ trunk/include/VBox/em.h	(revision 18927)
@@ -80,5 +80,5 @@
 } EMSTATE;
 
-VMMDECL(EMSTATE) EMGetState(PVM pVM);
+VMMDECL(EMSTATE) EMGetState(PVMCPU pVCpu);
 
 /** @name Callback handlers for instruction emulation functions.
@@ -117,26 +117,26 @@
 #define EMIsRawRing0Enabled(pVM) ((pVM)->fRawR0Enabled)
 
-VMMDECL(void)       EMSetInhibitInterruptsPC(PVM pVM, RTGCUINTPTR PC);
-VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVM pVM);
-VMMDECL(int)        EMInterpretDisasOne(PVM pVM, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr);
-VMMDECL(int)        EMInterpretDisasOneEx(PVM pVM, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
-                                         PDISCPUSTATE pCpu, unsigned *pcbInstr);
-VMMDECL(int)        EMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
-VMMDECL(int)        EMInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
-VMMDECL(int)        EMInterpretCpuId(PVM pVM, PCPUMCTXCORE pRegFrame);
-VMMDECL(int)        EMInterpretRdtsc(PVM pVM, PCPUMCTXCORE pRegFrame);
-VMMDECL(int)        EMInterpretRdpmc(PVM pVM, PCPUMCTXCORE pRegFrame);
-VMMDECL(int)        EMInterpretRdtscp(PVM pVM, PCPUMCTX pCtx);
-VMMDECL(int)        EMInterpretInvlpg(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC);
-VMMDECL(int)        EMInterpretIret(PVM pVM, PCPUMCTXCORE pRegFrame);
-VMMDECL(int)        EMInterpretDRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen);
-VMMDECL(int)        EMInterpretDRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx);
-VMMDECL(int)        EMInterpretCRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen);
-VMMDECL(int)        EMInterpretCRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx);
-VMMDECL(int)        EMInterpretLMSW(PVM pVM, PCPUMCTXCORE pRegFrame, uint16_t u16Data);
-VMMDECL(int)        EMInterpretCLTS(PVM pVM);
-VMMDECL(int)        EMInterpretPortIO(PVM pVM, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, uint32_t cbOp);
-VMMDECL(int)        EMInterpretRdmsr(PVM pVM, PCPUMCTXCORE pRegFrame);
-VMMDECL(int)        EMInterpretWrmsr(PVM pVM, PCPUMCTXCORE pRegFrame);
+VMMDECL(void)       EMSetInhibitInterruptsPC(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR PC);
+VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVM pVM, PVMCPU pVCpu);
+VMMDECL(int)        EMInterpretDisasOne(PVM pVM, PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr);
+VMMDECL(int)        EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
+                                          PDISCPUSTATE pDISState, unsigned *pcbInstr);
+VMMDECL(int)        EMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
+VMMDECL(int)        EMInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
+VMMDECL(int)        EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
+VMMDECL(int)        EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
+VMMDECL(int)        EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
+VMMDECL(int)        EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
+VMMDECL(int)        EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC);
+VMMDECL(int)        EMInterpretIret(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
+VMMDECL(int)        EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen);
+VMMDECL(int)        EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx);
+VMMDECL(int)        EMInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen);
+VMMDECL(int)        EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx);
+VMMDECL(int)        EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data);
+VMMDECL(int)        EMInterpretCLTS(PVM pVM, PVMCPU pVCpu);
+VMMDECL(int)        EMInterpretPortIO(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, uint32_t cbOp);
+VMMDECL(int)        EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
+VMMDECL(int)        EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
 
 /** @name Assembly routines
@@ -173,7 +173,7 @@
 VMMR3DECL(int)      EMR3Term(PVM pVM);
 VMMR3DECL(int)      EMR3TermCPU(PVM pVM);
-VMMR3DECL(DECLNORETURN(void)) EMR3FatalError(PVM pVM, int rc);
-VMMR3DECL(int)      EMR3ExecuteVM(PVM pVM, RTCPUID idCpu);
-VMMR3DECL(int)      EMR3CheckRawForcedActions(PVM pVM);
+VMMR3DECL(DECLNORETURN(void)) EMR3FatalError(PVMCPU pVCpu, int rc);
+VMMR3DECL(int)      EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu);
+VMMR3DECL(int)      EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu);
 VMMR3DECL(int)      EMR3Interpret(PVM pVM);
 
Index: trunk/include/VBox/err.h
===================================================================
--- trunk/include/VBox/err.h	(revision 18842)
+++ trunk/include/VBox/err.h	(revision 18927)
@@ -74,4 +74,6 @@
 /** Page directory pointer not present. */
 #define VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT (-1014)
+/** Raw mode doesn't support SMP. */
+#define VERR_RAW_MODE_INVALID_SMP           (-1015)
 /** @} */
 
Index: trunk/include/VBox/hwaccm.h
===================================================================
--- trunk/include/VBox/hwaccm.h	(revision 18842)
+++ trunk/include/VBox/hwaccm.h	(revision 18927)
@@ -73,5 +73,5 @@
  * @param   pCtx        CPU context
  */
-#define HWACCMCanEmulateIoBlock(pVM)       (!CPUMIsGuestInPagedProtectedMode(pVM))
+#define HWACCMCanEmulateIoBlock(pVCpu)     (!CPUMIsGuestInPagedProtectedMode(pVCpu))
 #define HWACCMCanEmulateIoBlockEx(pCtx)    (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
 
@@ -127,5 +127,5 @@
 VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM);
 VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM);
-VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode, PGMMODE enmGuestMode);
+VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode);
 VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM);
 VMMR3DECL(int)  HWACCMR3InjectNMI(PVM pVM);
Index: trunk/include/VBox/mm.h
===================================================================
--- trunk/include/VBox/mm.h	(revision 18842)
+++ trunk/include/VBox/mm.h	(revision 18927)
@@ -252,6 +252,4 @@
 
 VMMR3DECL(int)      MMR3HCPhys2HCVirt(PVM pVM, RTHCPHYS HCPhys, void **ppv);
-VMMR3DECL(int)      MMR3ReadGCVirt(PVM pVM, void *pvDst, RTGCPTR GCPtr, size_t cb);
-VMMR3DECL(int)      MMR3WriteGCVirt(PVM pVM, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
 
 
Index: trunk/include/VBox/pdmdev.h
===================================================================
--- trunk/include/VBox/pdmdev.h	(revision 18842)
+++ trunk/include/VBox/pdmdev.h	(revision 18927)
@@ -2843,4 +2843,12 @@
     DECLR3CALLBACKMEMBER(int, pfnUnregisterVMMDevHeap,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
 
+    /**
+     * Gets the VMCPU handle. Restricted API.
+     *
+     * @returns VMCPU Handle.
+     * @param   pDevIns             Device instance.
+     */
+    DECLR3CALLBACKMEMBER(PVMCPU, pfnGetVMCPU,(PPDMDEVINS pDevIns));
+
     /** @} */
 
@@ -2984,4 +2992,12 @@
     DECLRCCALLBACKMEMBER(PVM, pfnGetVM,(PPDMDEVINS pDevIns));
 
+    /**
+     * Gets the VMCPU handle. Restricted API.
+     *
+     * @returns VMCPU Handle.
+     * @param   pDevIns             Device instance.
+     */
+    DECLRCCALLBACKMEMBER(PVMCPU, pfnGetVMCPU,(PPDMDEVINS pDevIns));
+
     /** Just a safety precaution. */
     uint32_t                        u32TheEnd;
@@ -3129,4 +3145,12 @@
      */
     DECLR0CALLBACKMEMBER(bool, pfnCanEmulateIoBlock,(PPDMDEVINS pDevIns));
+
+    /**
+     * Gets the VMCPU handle. Restricted API.
+     *
+     * @returns VMCPU Handle.
+     * @param   pDevIns             Device instance.
+     */
+    DECLR0CALLBACKMEMBER(PVMCPU, pfnGetVMCPU,(PPDMDEVINS pDevIns));
 
     /** Just a safety precaution. */
@@ -3715,4 +3739,12 @@
 }
 
+/**
+ * @copydoc PDMDEVHLPR3::pfnGetVMCPU
+ */
+DECLINLINE(PVMCPU) PDMDevHlpGetVMCPU(PPDMDEVINS pDevIns)
+{
+    return pDevIns->CTX_SUFF(pDevHlp)->pfnGetVMCPU(pDevIns);
+}
+
 #ifdef IN_RING0
 /**
Index: trunk/include/VBox/pgm.h
===================================================================
--- trunk/include/VBox/pgm.h	(revision 18842)
+++ trunk/include/VBox/pgm.h	(revision 18927)
@@ -286,19 +286,16 @@
 VMMDECL(int)        PGMRegisterStringFormatTypes(void);
 VMMDECL(void)       PGMDeregisterStringFormatTypes(void);
-VMMDECL(RTHCPHYS)   PGMGetHyperCR3(PVM pVM);
-VMMDECL(RTHCPHYS)   PGMGetNestedCR3(PVM pVM, PGMMODE enmShadowMode);
-VMMDECL(RTHCPHYS)   PGMGetHyper32BitCR3(PVM pVM);
-VMMDECL(RTHCPHYS)   PGMGetHyperPaeCR3(PVM pVM);
-VMMDECL(RTHCPHYS)   PGMGetHyperAmd64CR3(PVM pVM);
+VMMDECL(RTHCPHYS)   PGMGetHyperCR3(PVMCPU pVCpu);
+VMMDECL(RTHCPHYS)   PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode);
 VMMDECL(RTHCPHYS)   PGMGetInterHCCR3(PVM pVM);
-VMMDECL(RTHCPHYS)   PGMGetInterRCCR3(PVM pVM);
+VMMDECL(RTHCPHYS)   PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu);
 VMMDECL(RTHCPHYS)   PGMGetInter32BitCR3(PVM pVM);
 VMMDECL(RTHCPHYS)   PGMGetInterPaeCR3(PVM pVM);
 VMMDECL(RTHCPHYS)   PGMGetInterAmd64CR3(PVM pVM);
-VMMDECL(int)        PGMTrap0eHandler(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
-VMMDECL(int)        PGMPrefetchPage(PVM pVM, RTGCPTR GCPtrPage);
-VMMDECL(int)        PGMVerifyAccess(PVM pVM, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
-VMMDECL(int)        PGMIsValidAccess(PVM pVM, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
-VMMDECL(int)        PGMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
+VMMDECL(int)        PGMTrap0eHandler(PVM pVM, PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
+VMMDECL(int)        PGMPrefetchPage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrPage);
+VMMDECL(int)        PGMVerifyAccess(PVM pVM, PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
+VMMDECL(int)        PGMIsValidAccess(PVM pVM, PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
+VMMDECL(int)        PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
 VMMDECL(int)        PGMMap(PVM pVM, RTGCPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags);
 VMMDECL(int)        PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags);
@@ -311,20 +308,20 @@
 VMMDECL(void)       PGMMapCheck(PVM pVM);
 #endif
-VMMDECL(int)        PGMShwGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
-VMMDECL(int)        PGMShwSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
-VMMDECL(int)        PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
-VMMDECL(int)        PGMGstGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
-VMMDECL(bool)       PGMGstIsPagePresent(PVM pVM, RTGCPTR GCPtr);
-VMMDECL(int)        PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
-VMMDECL(int)        PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
-VMMDECL(X86PDPE)    PGMGstGetPaePDPtr(PVM pVM, unsigned iPdPt);
-
-VMMDECL(int)        PGMInvalidatePage(PVM pVM, RTGCPTR GCPtrPage);
-VMMDECL(int)        PGMFlushTLB(PVM pVM, uint64_t cr3, bool fGlobal);
-VMMDECL(int)        PGMSyncCR3(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
-VMMDECL(int)        PGMUpdateCR3(PVM pVM, uint64_t cr3);
-VMMDECL(int)        PGMChangeMode(PVM pVM, uint64_t cr0, uint64_t cr4, uint64_t efer);
-VMMDECL(PGMMODE)    PGMGetGuestMode(PVM pVM);
-VMMDECL(PGMMODE)    PGMGetShadowMode(PVM pVM);
+VMMDECL(int)        PGMShwGetPage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
+VMMDECL(int)        PGMShwSetPage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
+VMMDECL(int)        PGMShwModifyPage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
+VMMDECL(int)        PGMGstGetPage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
+VMMDECL(bool)       PGMGstIsPagePresent(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr);
+VMMDECL(int)        PGMGstSetPage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
+VMMDECL(int)        PGMGstModifyPage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
+VMMDECL(X86PDPE)    PGMGstGetPaePDPtr(PVMCPU pVCpu, unsigned iPdPt);
+
+VMMDECL(int)        PGMInvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrPage);
+VMMDECL(int)        PGMFlushTLB(PVM pVM, PVMCPU pVCpu, uint64_t cr3, bool fGlobal);
+VMMDECL(int)        PGMSyncCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
+VMMDECL(int)        PGMUpdateCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3);
+VMMDECL(int)        PGMChangeMode(PVM pVM, PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer);
+VMMDECL(PGMMODE)    PGMGetGuestMode(PVMCPU pVCpu);
+VMMDECL(PGMMODE)    PGMGetShadowMode(PVMCPU pVCpu);
 VMMDECL(PGMMODE)    PGMGetHostMode(PVM pVM);
 VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
@@ -348,10 +345,10 @@
 VMMDECL(bool)       PGMHandlerPhysicalIsRegistered(PVM pVM, RTGCPHYS GCPhys);
 VMMDECL(bool)       PGMHandlerVirtualIsRegistered(PVM pVM, RTGCPTR GCPtr);
-VMMDECL(bool)       PGMPhysIsA20Enabled(PVM pVM);
+VMMDECL(bool)       PGMPhysIsA20Enabled(PVMCPU pVCpu);
 VMMDECL(bool)       PGMPhysIsGCPhysValid(PVM pVM, RTGCPHYS GCPhys);
 VMMDECL(bool)       PGMPhysIsGCPhysNormal(PVM pVM, RTGCPHYS GCPhys);
 VMMDECL(int)        PGMPhysGCPhys2HCPhys(PVM pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
-VMMDECL(int)        PGMPhysGCPtr2GCPhys(PVM pVM, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
-VMMDECL(int)        PGMPhysGCPtr2HCPhys(PVM pVM, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
+VMMDECL(int)        PGMPhysGCPtr2GCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
+VMMDECL(int)        PGMPhysGCPtr2HCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
 VMMDECL(void)       PGMPhysInvalidatePageGCMapTLB(PVM pVM);
 VMMDECL(void)       PGMPhysInvalidatePageR0MapTLB(PVM pVM);
@@ -360,6 +357,6 @@
 VMMDECL(int)        PGMPhysGCPhys2CCPtr(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
 VMMDECL(int)        PGMPhysGCPhys2CCPtrReadOnly(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
-VMMDECL(int)        PGMPhysGCPtr2CCPtr(PVM pVM, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
-VMMDECL(int)        PGMPhysGCPtr2CCPtrReadOnly(PVM pVM, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
+VMMDECL(int)        PGMPhysGCPtr2CCPtr(PVMCPU pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
+VMMDECL(int)        PGMPhysGCPtr2CCPtrReadOnly(PVMCPU pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
 VMMDECL(void)       PGMPhysReleasePageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
 
@@ -384,5 +381,5 @@
 VMMDECL(RTR3PTR)    PGMPhysGCPhys2R3PtrAssert(PVM pVM, RTGCPHYS GCPhys, RTUINT cbRange);
 #endif
-VMMDECL(int)        PGMPhysGCPtr2R3Ptr(PVM pVM, RTGCPTR GCPtr, PRTR3PTR pR3Ptr);
+VMMDECL(int)        PGMPhysGCPtr2R3Ptr(PVMCPU pVCpu, RTGCPTR GCPtr, PRTR3PTR pR3Ptr);
 VMMDECL(int)        PGMPhysRead(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead);
 VMMDECL(int)        PGMPhysWrite(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite);
@@ -390,17 +387,17 @@
 #ifndef IN_RC /* Only ring 0 & 3. */
 VMMDECL(int)        PGMPhysSimpleWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
-VMMDECL(int)        PGMPhysSimpleReadGCPtr(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
-VMMDECL(int)        PGMPhysSimpleWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
-VMMDECL(int)        PGMPhysReadGCPtr(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
-VMMDECL(int)        PGMPhysWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
-VMMDECL(int)        PGMPhysSimpleDirtyWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
+VMMDECL(int)        PGMPhysSimpleReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
+VMMDECL(int)        PGMPhysSimpleWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
+VMMDECL(int)        PGMPhysReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
+VMMDECL(int)        PGMPhysWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
+VMMDECL(int)        PGMPhysSimpleDirtyWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
 #endif /* !IN_RC */
-VMMDECL(int)        PGMPhysInterpretedRead(PVM pVM, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
-VMMDECL(int)        PGMPhysInterpretedReadNoHandlers(PVM pVM, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb, bool fRaiseTrap);
-VMMDECL(int)        PGMPhysInterpretedWriteNoHandlers(PVM pVM, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, void const *pvSrc, size_t cb, bool fRaiseTrap);
+VMMDECL(int)        PGMPhysInterpretedRead(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
+VMMDECL(int)        PGMPhysInterpretedReadNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb, bool fRaiseTrap);
+VMMDECL(int)        PGMPhysInterpretedWriteNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, void const *pvSrc, size_t cb, bool fRaiseTrap);
 #ifdef VBOX_STRICT
 VMMDECL(unsigned)   PGMAssertHandlerAndFlagsInSync(PVM pVM);
 VMMDECL(unsigned)   PGMAssertNoMappingConflicts(PVM pVM);
-VMMDECL(unsigned)   PGMAssertCR3(PVM pVM, uint64_t cr3, uint64_t cr4);
+VMMDECL(unsigned)   PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4);
 #endif /* VBOX_STRICT */
 
@@ -440,5 +437,5 @@
  */
 VMMR0DECL(int)      PGMR0PhysAllocateHandyPages(PVM pVM);
-VMMR0DECL(int)      PGMR0Trap0eHandlerNestedPaging(PVM pVM, PGMMODE enmShwPagingMode, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
+VMMR0DECL(int)      PGMR0Trap0eHandlerNestedPaging(PVM pVM, PVMCPU pVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
 # ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
 VMMR0DECL(int)      PGMR0DynMapInit(void);
@@ -467,5 +464,5 @@
 VMMR3DECL(int)      PGMR3TermCPU(PVM pVM);
 VMMR3DECL(int)      PGMR3LockCall(PVM pVM);
-VMMR3DECL(int)      PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode);
+VMMR3DECL(int)      PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode);
 
 VMMR3DECL(int)      PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
@@ -497,5 +494,5 @@
 VMMR3DECL(int)      PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
 VMMR3DECL(int)      PGMR3PhysRegister(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc);
-VMMDECL(void)       PGMR3PhysSetA20(PVM pVM, bool fEnable);
+VMMDECL(void)       PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable);
 /** @name PGMR3MapPT flags.
  * @{ */
Index: trunk/include/VBox/rem.h
===================================================================
--- trunk/include/VBox/rem.h	(revision 18842)
+++ trunk/include/VBox/rem.h	(revision 18927)
@@ -65,17 +65,17 @@
 REMR3DECL(int)  REMR3Term(PVM pVM);
 REMR3DECL(void) REMR3Reset(PVM pVM);
-REMR3DECL(int)  REMR3Run(PVM pVM);
-REMR3DECL(int)  REMR3EmulateInstruction(PVM pVM);
-REMR3DECL(int)  REMR3Step(PVM pVM);
+REMR3DECL(int)  REMR3Run(PVM pVM, PVMCPU pVCpu);
+REMR3DECL(int)  REMR3EmulateInstruction(PVM pVM, PVMCPU pVCpu);
+REMR3DECL(int)  REMR3Step(PVM pVM, PVMCPU pVCpu);
 REMR3DECL(int)  REMR3BreakpointSet(PVM pVM, RTGCUINTPTR Address);
 REMR3DECL(int)  REMR3BreakpointClear(PVM pVM, RTGCUINTPTR Address);
-REMR3DECL(int)  REMR3State(PVM pVM);
-REMR3DECL(int)  REMR3StateBack(PVM pVM);
-REMR3DECL(void) REMR3StateUpdate(PVM pVM);
-REMR3DECL(void) REMR3A20Set(PVM pVM, bool fEnable);
+REMR3DECL(int)  REMR3State(PVM pVM, PVMCPU pVCpu);
+REMR3DECL(int)  REMR3StateBack(PVM pVM, PVMCPU pVCpu);
+REMR3DECL(void) REMR3StateUpdate(PVM pVM, PVMCPU pVCpu);
+REMR3DECL(void) REMR3A20Set(PVM pVM, PVMCPU pVCpu, bool fEnable);
 REMR3DECL(int)  REMR3DisasEnableStepping(PVM pVM, bool fEnable);
-REMR3DECL(void) REMR3ReplayInvalidatedPages(PVM pVM);
+REMR3DECL(void) REMR3ReplayInvalidatedPages(PVM pVM, PVMCPU pVCpu);
 REMR3DECL(void) REMR3ReplayHandlerNotifications(PVM pVM);
-REMR3DECL(int)  REMR3NotifyCodePageChanged(PVM pVM, RTGCPTR pvCodePage);
+REMR3DECL(int)  REMR3NotifyCodePageChanged(PVM pVM, PVMCPU pVCpu, RTGCPTR pvCodePage);
 REMR3DECL(void) REMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, unsigned fFlags);
 /** @name Flags for REMR3NotifyPhysRamRegister.
@@ -89,8 +89,8 @@
 REMR3DECL(void) REMR3NotifyHandlerPhysicalDeregister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS cb, bool fHasHCHandler, bool fRestoreAsRAM);
 REMR3DECL(void) REMR3NotifyHandlerPhysicalModify(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhysOld, RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fHasHCHandler, bool fRestoreAsRAM);
-REMR3DECL(void) REMR3NotifyPendingInterrupt(PVM pVM, uint8_t u8Interrupt);
-REMR3DECL(uint32_t) REMR3QueryPendingInterrupt(PVM pVM);
-REMR3DECL(void) REMR3NotifyInterruptSet(PVM pVM);
-REMR3DECL(void) REMR3NotifyInterruptClear(PVM pVM);
+REMR3DECL(void) REMR3NotifyPendingInterrupt(PVM pVM, PVMCPU pVCpu, uint8_t u8Interrupt);
+REMR3DECL(uint32_t) REMR3QueryPendingInterrupt(PVM pVM, PVMCPU pVCpu);
+REMR3DECL(void) REMR3NotifyInterruptSet(PVM pVM, PVMCPU pVCpu);
+REMR3DECL(void) REMR3NotifyInterruptClear(PVM pVM, PVMCPU pVCpu);
 REMR3DECL(void) REMR3NotifyTimerPending(PVM pVM);
 REMR3DECL(void) REMR3NotifyDmaPending(PVM pVM);
Index: trunk/include/VBox/selm.h
===================================================================
--- trunk/include/VBox/selm.h	(revision 18842)
+++ trunk/include/VBox/selm.h	(revision 18927)
@@ -53,8 +53,8 @@
 VMMDECL(RTSEL)      SELMGetHyperTSSTrap08(PVM pVM);
 VMMDECL(RTRCPTR)    SELMGetHyperGDT(PVM pVM);
-VMMDECL(int)        SELMGetTSSInfo(PVM pVM, PRTGCUINTPTR pGCPtrTss, PRTGCUINTPTR pcbTss, bool *pfCanHaveIOBitmap);
+VMMDECL(int)        SELMGetTSSInfo(PVM pVM, PVMCPU pVCpu, PRTGCUINTPTR pGCPtrTss, PRTGCUINTPTR pcbTss, bool *pfCanHaveIOBitmap);
 VMMDECL(RTGCPTR)    SELMToFlat(PVM pVM, DIS_SELREG SelReg, PCPUMCTXCORE pCtxCore, RTGCPTR Addr);
 VMMDECL(RTGCPTR)    SELMToFlatBySel(PVM pVM, RTSEL Sel, RTGCPTR Addr);
-VMMDECL(void)       SELMShadowCR3Changed(PVM pVM);
+VMMDECL(void)       SELMShadowCR3Changed(PVM pVM, PVMCPU pVCpu);
 
 /** Flags for SELMToFlatEx().
@@ -138,7 +138,7 @@
 VMMR3DECL(int)      SELMR3Term(PVM pVM);
 VMMR3DECL(void)     SELMR3Reset(PVM pVM);
-VMMR3DECL(int)      SELMR3UpdateFromCPUM(PVM pVM);
-VMMR3DECL(int)      SELMR3SyncTSS(PVM pVM);
-VMMR3DECL(int)      SELMR3GetSelectorInfo(PVM pVM, RTSEL Sel, PSELMSELINFO pSelInfo);
+VMMR3DECL(int)      SELMR3UpdateFromCPUM(PVM pVM, PVMCPU pVCpu);
+VMMR3DECL(int)      SELMR3SyncTSS(PVM pVM, PVMCPU pVCpu);
+VMMR3DECL(int)      SELMR3GetSelectorInfo(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PSELMSELINFO pSelInfo);
 VMMR3DECL(int)      SELMR3GetShadowSelectorInfo(PVM pVM, RTSEL Sel, PSELMSELINFO pSelInfo);
 VMMR3DECL(void)     SELMR3DisableMonitoring(PVM pVM);
Index: trunk/include/VBox/trpm.h
===================================================================
--- trunk/include/VBox/trpm.h	(revision 18842)
+++ trunk/include/VBox/trpm.h	(revision 18927)
@@ -106,8 +106,8 @@
 VMMR3DECL(RTRCPTR)  TRPMR3GetGuestTrapHandler(PVM pVM, unsigned iTrap);
 VMMR3DECL(void)     TRPMR3DisableMonitoring(PVM pVM);
-VMMR3DECL(int)      TRPMR3SyncIDT(PVM pVM);
+VMMR3DECL(int)      TRPMR3SyncIDT(PVM pVM, PVMCPU pVCpu);
 VMMR3DECL(bool)     TRPMR3IsGateHandler(PVM pVM, RTRCPTR GCPtr);
 VMMR3DECL(uint32_t) TRPMR3QueryGateByHandler(PVM pVM, RTRCPTR GCPtr);
-VMMR3DECL(int)      TRPMR3InjectEvent(PVM pVM, TRPMEVENT enmEvent);
+VMMR3DECL(int)      TRPMR3InjectEvent(PVM pVM, PVMCPU pVCpu, TRPMEVENT enmEvent);
 /** @} */
 #endif
Index: trunk/include/VBox/vm.h
===================================================================
--- trunk/include/VBox/vm.h	(revision 18842)
+++ trunk/include/VBox/vm.h	(revision 18927)
@@ -113,5 +113,5 @@
         struct CPUMCPU      s;
 #endif
-        char                padding[2560];      /* multiple of 64 */
+        char                padding[4096];      /* multiple of 64 */
     } cpum;
     /** VMM part. */
@@ -130,5 +130,5 @@
         struct PGMCPU       s;
 #endif
-        char                padding[2048];       /* multiple of 64 */
+        char                padding[32*1024];       /* multiple of 64 */
     } pgm;
 
@@ -148,5 +148,5 @@
         struct EMCPU        s;
 #endif
-        char                padding[64];        /* multiple of 64 */
+        char                padding[2048];        /* multiple of 64 */
     } em;
 
@@ -619,5 +619,5 @@
         struct CPUM s;
 #endif
-        char        padding[4096];      /* multiple of 32 */
+        char        padding[2048];        /* multiple of 32 */
     } cpum;
 
@@ -637,5 +637,5 @@
         struct PGM  s;
 #endif
-        char        padding[50*1024];   /* multiple of 32 */
+        char        padding[16*1024];   /* multiple of 32 */
     } pgm;
 
@@ -736,5 +736,5 @@
         struct EM   s;
 #endif
-        char        padding[1344];      /* multiple of 32 */
+        char        padding[64];         /* multiple of 32 */
     } em;
 
Index: trunk/include/VBox/vm.mac
===================================================================
--- trunk/include/VBox/vm.mac	(revision 18842)
+++ trunk/include/VBox/vm.mac	(revision 18927)
@@ -97,5 +97,5 @@
 
     alignb 64
-    .cpum                 resb 4096
+    .cpum                 resb 2048
     .vmm                  resb 1024
 
Index: trunk/include/VBox/vmm.h
===================================================================
--- trunk/include/VBox/vmm.h	(revision 18842)
+++ trunk/include/VBox/vmm.h	(revision 18927)
@@ -110,7 +110,8 @@
 } VMMCALLHOST;
 
-RTRCPTR              VMMGetStackRC(PVM pVM);
-VMCPUID              VMMGetCpuId(PVM pVM);
-PVMCPU               VMMGetCpu(PVM pVM);
+VMMDECL(RTRCPTR)     VMMGetStackRC(PVM pVM);
+VMMDECL(VMCPUID)     VMMGetCpuId(PVM pVM);
+VMMDECL(PVMCPU)      VMMGetCpu(PVM pVM);
+VMMDECL(PVMCPU)      VMMGetCpu0(PVM pVM);
 VMMDECL(PVMCPU)      VMMGetCpuEx(PVM pVM, RTCPUID idCpu);
 VMMDECL(uint32_t)    VMMGetSvnRev(void);
@@ -148,11 +149,11 @@
 VMMR3DECL(int)      VMMR3DisableSwitcher(PVM pVM);
 VMMR3DECL(RTR0PTR)  VMMR3GetHostToGuestSwitcher(PVM pVM, VMMSWITCHER enmSwitcher);
-VMMR3DECL(int)      VMMR3RawRunGC(PVM pVM);
-VMMR3DECL(int)      VMMR3HwAccRunGC(PVM pVM, RTCPUID idCpu);
+VMMR3DECL(int)      VMMR3RawRunGC(PVM pVM, PVMCPU pVCpu);
+VMMR3DECL(int)      VMMR3HwAccRunGC(PVM pVM, PVMCPU pVCpu);
 VMMR3DECL(int)      VMMR3CallRC(PVM pVM, RTRCPTR RCPtrEntry, unsigned cArgs, ...);
 VMMR3DECL(int)      VMMR3CallRCV(PVM pVM, RTRCPTR RCPtrEntry, unsigned cArgs, va_list args);
 VMMR3DECL(int)      VMMR3CallR0(PVM pVM, uint32_t uOperation, uint64_t u64Arg, PSUPVMMR0REQHDR pReqHdr);
-VMMR3DECL(int)      VMMR3ResumeHyper(PVM pVM);
-VMMR3DECL(void)     VMMR3FatalDump(PVM pVM, int rcErr);
+VMMR3DECL(int)      VMMR3ResumeHyper(PVM pVM, PVMCPU pVCpu);
+VMMR3DECL(void)     VMMR3FatalDump(PVM pVM, PVMCPU pVCpu, int rcErr);
 VMMR3DECL(int)      VMMR3Lock(PVM pVM);
 VMMR3DECL(int)      VMMR3Unlock(PVM pVM);
