Changeset 18927 in vbox for trunk/src/VBox/VMM/PATM

Timestamp:

Apr 16, 2009 11:41:38 AM (16 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

46003

Message:

Big step to separate VMM data structures for guest SMP. (pgm, em)

Location:

trunk/src/VBox/VMM/PATM

Files:

• CSAM.cpp (modified) (39 diffs)
• PATM.cpp (modified) (47 diffs)
• PATMGuest.cpp (modified) (6 diffs)
• PATMInternal.h (modified) (1 diff)
• PATMPatch.cpp (modified) (1 diff)
• PATMSSM.cpp (modified) (3 diffs)
• VMMAll/PATMAll.cpp (modified) (4 diffs)
• VMMGC/CSAMGC.cpp (modified) (3 diffs)
• VMMGC/PATMGC.cpp (modified) (3 diffs)

trunk/src/VBox/VMM/PATM/CSAM.cpp

@@ -562 +562 @@
     int rc;
     R3PTRTYPE(void *) pHCPtr;
+    Assert(pVM->cCPUs == 1);
+    PVMCPU pVCpu = VMMGetCpu0(pVM);
 
     STAM_PROFILE_START(&pVM->csam.s.StatTimeAddrConv, a);
@@ -578 +580 @@
     }
 
-    rc = PGMPhysGCPtr2R3Ptr(pVM, pGCPtr, &pHCPtr);
+    rc = PGMPhysGCPtr2R3Ptr(pVCpu, pGCPtr, &pHCPtr);
     if (rc != VINF_SUCCESS)
     {
@@ -585 +587 @@
         return NULL;
     }
-////invalid?    Assert(sizeof(R3PTRTYPE(uint8_t*)) == sizeof(uint32_t));
 
     pCacheRec->pPageLocStartHC = (R3PTRTYPE(uint8_t*))((RTHCUINTPTR)pHCPtr & PAGE_BASE_HC_MASK);
-    pCacheRec->pGuestLoc      = pGCPtr & PAGE_BASE_GC_MASK;
+    pCacheRec->pGuestLoc       = pGCPtr & PAGE_BASE_GC_MASK;
     STAM_PROFILE_STOP(&pVM->csam.s.StatTimeAddrConv, a);
     return pHCPtr;
@@ -608 +609 @@
     PVM           pVM      = (PVM)pCpu->apvUserData[0];
     RTHCUINTPTR   pInstrHC = (RTHCUINTPTR)pCpu->apvUserData[1];
-    RTGCUINTPTR32   pInstrGC = (uintptr_t)pCpu->apvUserData[2];
+    RTGCUINTPTR32 pInstrGC = (uintptr_t)pCpu->apvUserData[2];
     int           orgsize  = size;
+    Assert(pVM->cCPUs == 1);
+    PVMCPU        pVCpu = VMMGetCpu0(pVM);
 
     /* We are not interested in patched instructions, so read the original opcode bytes. */
@@ -630 +633 @@
     if (PAGE_ADDRESS(pInstrGC) != PAGE_ADDRESS(pSrc + size - 1) && !PATMIsPatchGCAddr(pVM, pSrc))
     {
-        return PGMPhysSimpleReadGCPtr(pVM, pDest, pSrc, size);
+        return PGMPhysSimpleReadGCPtr(pVCpu, pDest, pSrc, size);
     }
     else
@@ -1080 +1083 @@
     R3PTRTYPE(uint8_t *) pCurInstrHC = 0;
     int rc2;
+    Assert(pVM->cCPUs == 1);
+    PVMCPU pVCpu = VMMGetCpu0(pVM);
 
 #ifdef DEBUG
@@ -1162 +1167 @@
         if (PAGE_ADDRESS(pCurInstrGC) != PAGE_ADDRESS(pCurInstrGC + opsize - 1))
         {
-            if (!PGMGstIsPagePresent(pVM, pCurInstrGC + opsize - 1))
+            if (!PGMGstIsPagePresent(pVM, pVCpu, pCurInstrGC + opsize - 1))
             {
                 /// @todo fault in the page
@@ -1206 +1211 @@
             {
                 addr = 0;
-                PGMPhysSimpleReadGCPtr(pVM, &addr, (RTRCUINTPTR)cpu.param1.disp32, sizeof(addr));
+                PGMPhysSimpleReadGCPtr(pVCpu, &addr, (RTRCUINTPTR)cpu.param1.disp32, sizeof(addr));
             }
             else
@@ -1225 +1230 @@
             if (PAGE_ADDRESS(addr) != PAGE_ADDRESS(pCurInstrGC ))
             {
-                if (!PGMGstIsPagePresent(pVM, addr))
+                if (!PGMGstIsPagePresent(pVM, pVCpu, addr))
                 {
                     Log(("Page for current instruction %RRv is not present!!\n", addr));
@@ -1279 +1284 @@
             Log(("Jump through jump table\n"));
 
-            rc2 = PGMPhysGCPtr2R3Ptr(pVM, pJumpTableGC, (PRTHCPTR)&pJumpTableHC);
+            rc2 = PGMPhysGCPtr2R3Ptr(pVCpu, pJumpTableGC, (PRTHCPTR)&pJumpTableHC);
             if (rc2 == VINF_SUCCESS)
             {
@@ -1293 +1298 @@
                     addr = *(RTRCPTR *)(pJumpTableHC + cpu.param1.scale * i);
 
-                    rc2 = PGMGstGetPage(pVM, addr, &fFlags, NULL);
+                    rc2 = PGMGstGetPage(pVM, pVCpu, addr, &fFlags, NULL);
                     if (    rc2 != VINF_SUCCESS
                         ||  (fFlags & X86_PTE_US)
@@ -1354 +1359 @@
     uint32_t val[5];
     int      rc;
+    Assert(pVM->cCPUs == 1);
+    PVMCPU pVCpu = VMMGetCpu0(pVM);
 
     Assert((pInstr & PAGE_OFFSET_MASK) == 0);
 
-    rc = PGMPhysSimpleReadGCPtr(pVM, &val[0], pInstr, sizeof(val[0]));
+    rc = PGMPhysSimpleReadGCPtr(pVCpu, &val[0], pInstr, sizeof(val[0]));
     AssertMsg(RT_SUCCESS(rc) || rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc = %Rrc\n", rc));
     if (rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT)
@@ -1365 +1372 @@
     }
 
-    rc = PGMPhysSimpleReadGCPtr(pVM, &val[1], pInstr+1024, sizeof(val[0]));
+    rc = PGMPhysSimpleReadGCPtr(pVCpu, &val[1], pInstr+1024, sizeof(val[0]));
     AssertMsg(RT_SUCCESS(rc) || rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc = %Rrc\n", rc));
     if (rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT)
@@ -1373 +1380 @@
     }
 
-    rc = PGMPhysSimpleReadGCPtr(pVM, &val[2], pInstr+2048, sizeof(val[0]));
+    rc = PGMPhysSimpleReadGCPtr(pVCpu, &val[2], pInstr+2048, sizeof(val[0]));
     AssertMsg(RT_SUCCESS(rc) || rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc = %Rrc\n", rc));
     if (rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT)
@@ -1381 +1388 @@
     }
 
-    rc = PGMPhysSimpleReadGCPtr(pVM, &val[3], pInstr+3072, sizeof(val[0]));
+    rc = PGMPhysSimpleReadGCPtr(pVCpu, &val[3], pInstr+3072, sizeof(val[0]));
     AssertMsg(RT_SUCCESS(rc) || rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc = %Rrc\n", rc));
     if (rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT)
@@ -1389 +1396 @@
     }
 
-    rc = PGMPhysSimpleReadGCPtr(pVM, &val[4], pInstr+4092, sizeof(val[0]));
+    rc = PGMPhysSimpleReadGCPtr(pVCpu, &val[4], pInstr+4092, sizeof(val[0]));
     AssertMsg(RT_SUCCESS(rc) || rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc = %Rrc\n", rc));
     if (rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT)
@@ -1420 +1427 @@
     RTGCPHYS GCPhys = 0;
     uint64_t fFlags = 0;
+    Assert(pVM->cCPUs == 1);
+    PVMCPU pVCpu = VMMGetCpu0(pVM);
 
     if (!CSAMIsEnabled(pVM))
@@ -1437 +1446 @@
     }
 
-    rc = PGMGstGetPage(pVM, addr, &fFlags, &GCPhys);
+    rc = PGMGstGetPage(pVM, pVCpu, addr, &fFlags, &GCPhys);
     /* Returned at a very early stage (no paging yet presumably). */
     if (rc == VERR_NOT_SUPPORTED)
@@ -1483 +1492 @@
             pPageRec->page.GCPhys = 0;
             pPageRec->page.fFlags = 0;
-            rc = PGMGstGetPage(pVM, addr, &pPageRec->page.fFlags, &pPageRec->page.GCPhys);
+            rc = PGMGstGetPage(pVM, pVCpu, addr, &pPageRec->page.fFlags, &pPageRec->page.GCPhys);
             if (rc == VINF_SUCCESS)
                 pPageRec->page.u64Hash = csamR3CalcPageHash(pVM, addr);
@@ -1610 +1619 @@
     int          rc;
     bool         ret;
+    Assert(pVM->cCPUs == 1);
+    PVMCPU pVCpu = VMMGetCpu0(pVM);
 
     Log(("New page record for %RRv\n", GCPtr & PAGE_BASE_GC_MASK));
@@ -1628 +1639 @@
     pPage->page.fMonitorActive       = false;
     pPage->page.pBitmap              = (uint8_t *)MMR3HeapAllocZ(pVM, MM_TAG_CSAM_PATCH, PAGE_SIZE/sizeof(uint8_t));
-    rc = PGMGstGetPage(pVM, GCPtr, &pPage->page.fFlags, &pPage->page.GCPhys);
+    rc = PGMGstGetPage(pVM, pVCpu, GCPtr, &pPage->page.fFlags, &pPage->page.GCPhys);
     AssertMsg(RT_SUCCESS(rc) || rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc = %Rrc\n", rc));
 
@@ -1656 +1667 @@
 
         /* Prefetch it in case it's not there yet. */
-        rc = PGMPrefetchPage(pVM, GCPtr);
+        rc = PGMPrefetchPage(pVM, pVCpu, GCPtr);
         AssertRC(rc);
 
-        rc = PGMShwModifyPage(pVM, GCPtr, 1, 0, ~(uint64_t)X86_PTE_RW);
+        rc = PGMShwModifyPage(pVM, pVCpu, GCPtr, 1, 0, ~(uint64_t)X86_PTE_RW);
         Assert(rc == VINF_SUCCESS || rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT);
 
@@ -1711 +1722 @@
     int          rc;
     bool         fMonitorInvalidation;
+    Assert(pVM->cCPUs == 1);
+    PVMCPU pVCpu = VMMGetCpu0(pVM);
 
     /* Dirty pages must be handled before calling this function!. */
@@ -1730 +1743 @@
         uint64_t fFlags;
 
-        rc = PGMGstGetPage(pVM, pPageAddrGC, &fFlags, NULL);
+        rc = PGMGstGetPage(pVM, pVCpu, pPageAddrGC, &fFlags, NULL);
         AssertMsg(RT_SUCCESS(rc) || rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc = %Rrc\n", rc));
         if (    rc == VINF_SUCCESS
@@ -1766 +1779 @@
 
         /* Prefetch it in case it's not there yet. */
-        rc = PGMPrefetchPage(pVM, pPageAddrGC);
+        rc = PGMPrefetchPage(pVM, pVCpu, pPageAddrGC);
         AssertRC(rc);
 
-        rc = PGMShwModifyPage(pVM, pPageAddrGC, 1, 0, ~(uint64_t)X86_PTE_RW);
+        rc = PGMShwModifyPage(pVM, pVCpu, pPageAddrGC, 1, 0, ~(uint64_t)X86_PTE_RW);
         Assert(rc == VINF_SUCCESS || rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT);
 
@@ -1787 +1800 @@
 
         /* Prefetch it in case it's not there yet. */
-        rc = PGMPrefetchPage(pVM, pPageAddrGC);
+        rc = PGMPrefetchPage(pVM, pVCpu, pPageAddrGC);
         AssertRC(rc);
 
         /* Make sure it's readonly. Page invalidation may have modified the attributes. */
-        rc = PGMShwModifyPage(pVM, pPageAddrGC, 1, 0, ~(uint64_t)X86_PTE_RW);
+        rc = PGMShwModifyPage(pVM, pVCpu, pPageAddrGC, 1, 0, ~(uint64_t)X86_PTE_RW);
         Assert(rc == VINF_SUCCESS || rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT);
     }
@@ -1800 +1813 @@
         uint64_t fPageShw;
         RTHCPHYS GCPhys;
-        rc = PGMShwGetPage(pVM, pPageAddrGC, &fPageShw, &GCPhys);
+        rc = PGMShwGetPage(pVM, pVCpu, pPageAddrGC, &fPageShw, &GCPhys);
 //        AssertMsg(     (rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT)
 //                ||  !(fPageShw & X86_PTE_RW)
@@ -1810 +1823 @@
     {
         /* Prefetch it in case it's not there yet. */
-        rc = PGMPrefetchPage(pVM, pPageAddrGC);
+        rc = PGMPrefetchPage(pVM, pVCpu, pPageAddrGC);
         AssertRC(rc);
         /* The page was changed behind our back. It won't be made read-only until the next SyncCR3, so force it here. */
-        rc = PGMShwModifyPage(pVM, pPageAddrGC, 1, 0, ~(uint64_t)X86_PTE_RW);
+        rc = PGMShwModifyPage(pVM, pVCpu, pPageAddrGC, 1, 0, ~(uint64_t)X86_PTE_RW);
         Assert(rc == VINF_SUCCESS || rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT);
     }
@@ -1855 +1868 @@
 {
     PCSAMPAGEREC pPageRec;
+    Assert(pVM->cCPUs == 1);
+    PVMCPU pVCpu = VMMGetCpu0(pVM);
 
     Log(("csamRemovePageRecord %RRv\n", GCPtr));
@@ -1877 +1892 @@
             /* Make sure the recompiler flushes its cache as this page is no longer monitored. */
             STAM_COUNTER_INC(&pVM->csam.s.StatPageRemoveREMFlush);
-            CPUMSetChangedFlags(pVM, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
+            CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
         }
 #endif
@@ -2174 +2189 @@
 static int csamR3FlushDirtyPages(PVM pVM)
 {
+    Assert(pVM->cCPUs == 1);
+    PVMCPU pVCpu = VMMGetCpu0(pVM);
+
     STAM_PROFILE_START(&pVM->csam.s.StatFlushDirtyPages, a);
 
@@ -2185 +2203 @@
 
         /* Notify the recompiler that this page has been changed. */
-        REMR3NotifyCodePageChanged(pVM, GCPtr);
+        REMR3NotifyCodePageChanged(pVM, pVCpu, GCPtr);
 
         /* Enable write protection again. (use the fault address as it might be an alias) */
-        rc = PGMShwModifyPage(pVM, pVM->csam.s.pvDirtyFaultPage[i], 1, 0, ~(uint64_t)X86_PTE_RW);
+        rc = PGMShwModifyPage(pVM, pVCpu, pVM->csam.s.pvDirtyFaultPage[i], 1, 0, ~(uint64_t)X86_PTE_RW);
         Assert(rc == VINF_SUCCESS || rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT);
 
@@ -2198 +2216 @@
             uint64_t fFlags;
 
-            rc = PGMGstGetPage(pVM, GCPtr, &fFlags, NULL);
+            rc = PGMGstGetPage(pVM, pVCpu, GCPtr, &fFlags, NULL);
             AssertMsg(RT_SUCCESS(rc) || rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc = %Rrc\n", rc));
             if (    rc == VINF_SUCCESS
@@ -2222 +2240 @@
 static int csamR3FlushCodePages(PVM pVM)
 {
+    Assert(pVM->cCPUs == 1);
+    PVMCPU pVCpu = VMMGetCpu0(pVM);
+
     for (uint32_t i=0;i<pVM->csam.s.cPossibleCodePages;i++)
     {
-        RTRCPTR      GCPtr = pVM->csam.s.pvPossibleCodePage[i];
+        RTRCPTR GCPtr = pVM->csam.s.pvPossibleCodePage[i];
 
         GCPtr = GCPtr & PAGE_BASE_GC_MASK;
 
         Log(("csamR3FlushCodePages: %RRv\n", GCPtr));
-        PGMShwSetPage(pVM, GCPtr, 1, 0);
+        PGMShwSetPage(pVM, pVCpu, GCPtr, 1, 0);
         /* Resync the page to make sure instruction fetch will fault */
         CSAMMarkPage(pVM, GCPtr, false);
@@ -2262 +2283 @@
 VMMR3DECL(int) CSAMR3CheckGates(PVM pVM, uint32_t iGate, uint32_t cGates)
 {
+    Assert(pVM->cCPUs == 1);
+    PVMCPU      pVCpu = VMMGetCpu0(pVM);
     uint16_t    cbIDT;
-    RTRCPTR     GCPtrIDT = CPUMGetGuestIDTR(pVM, &cbIDT);
+    RTRCPTR     GCPtrIDT = CPUMGetGuestIDTR(pVCpu, &cbIDT);
     uint32_t    iGateEnd;
     uint32_t    maxGates;
@@ -2336 +2359 @@
     {
         /* Just convert the IDT address to a R3 pointer. The whole IDT fits in one page. */
-        rc = PGMPhysGCPtr2R3Ptr(pVM, GCPtrIDT, (PRTR3PTR)&pGuestIdte);
+        rc = PGMPhysGCPtr2R3Ptr(pVCpu, GCPtrIDT, (PRTR3PTR)&pGuestIdte);
         if (RT_FAILURE(rc))
         {
@@ -2347 +2370 @@
     {
         /* Slow method when it crosses a page boundary. */
-        rc = PGMPhysSimpleReadGCPtr(pVM, aIDT, GCPtrIDT,  cGates*sizeof(VBOXIDTE));
+        rc = PGMPhysSimpleReadGCPtr(pVCpu, aIDT, GCPtrIDT,  cGates*sizeof(VBOXIDTE));
         if (RT_FAILURE(rc))
         {
@@ -2374 +2397 @@
             pHandler = SELMToFlatBySel(pVM, pGuestIdte->Gen.u16SegSel, pHandler);
 
-            rc = SELMR3GetSelectorInfo(pVM, pGuestIdte->Gen.u16SegSel, &selInfo);
+            rc = SELMR3GetSelectorInfo(pVM, pVCpu, pGuestIdte->Gen.u16SegSel, &selInfo);
             if (    RT_FAILURE(rc)
                 ||  selInfo.GCPtrBase != 0
@@ -2412 +2435 @@
                                                        0x2F};      /* OpenBSD 4.0 after install */
 
-                pCtx = CPUMQueryGuestCtxPtr(pVM);
+                pCtx = CPUMQueryGuestCtxPtr(pVCpu);
 
                 for (unsigned i=0;i<RT_ELEMENTS(aOpenBsdPushCSOffset);i++)
                 {
-                    rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pHandler - aOpenBsdPushCSOffset[i], &cpu, NULL);
+                    rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pHandler - aOpenBsdPushCSOffset[i], &cpu, NULL);
                     if (    rc == VINF_SUCCESS
                         &&  cpu.pCurInstr->opcode == OP_PUSH

trunk/src/VBox/VMM/PATM/PATM.cpp

@@ -346 +346 @@
 
     /* Needed for future patching of sldt/sgdt/sidt/str etc. */
-    pVM->patm.s.pCPUMCtxGC = VM_RC_ADDR(pVM, CPUMQueryGuestCtxPtr(pVM));
+    pVM->patm.s.pCPUMCtxGC = VM_RC_ADDR(pVM, CPUMQueryGuestCtxPtr(VMMGetCpu0(pVM)));
 
     Assert(pVM->patm.s.PatchLookupTreeHC);
@@ -426 +426 @@
         RTAvloU32DoWithAll(&pVM->patm.s.PatchLookupTreeHC->PatchTree, true, RelocatePatches, (void *)pVM);
 
-        pCtx = CPUMQueryGuestCtxPtr(pVM);
+        pCtx = CPUMQueryGuestCtxPtr(VMMGetCpu0(pVM));
 
         /* If we are running patch code right now, then also adjust EIP. */
@@ -557 +557 @@
     if (PAGE_ADDRESS(pDisInfo->pInstrGC) != PAGE_ADDRESS(pSrc + size - 1) && !PATMIsPatchGCAddr(pDisInfo->pVM, pSrc))
     {
-        return PGMPhysSimpleReadGCPtr(pDisInfo->pVM, pDest, pSrc, size);
+        return PGMPhysSimpleReadGCPtr(&pDisInfo->pVM->aCpus[0], pDest, pSrc, size);
     }
     else
@@ -604 +604 @@
     {
         /** @note pPrivInstrHC is probably not valid anymore */
-        rc = PGMPhysGCPtr2R3Ptr(pVM, pPatch->patch.pPrivInstrGC, (PRTR3PTR)&pPatch->patch.pPrivInstrHC);
+        rc = PGMPhysGCPtr2R3Ptr(VMMGetCpu0(pVM), pPatch->patch.pPrivInstrGC, (PRTR3PTR)&pPatch->patch.pPrivInstrHC);
         if (rc == VINF_SUCCESS)
         {
@@ -651 +651 @@
                 *(RTRCPTR *)&oldInstr[pPatch->patch.cbPrivInstr - sizeof(RTRCPTR)] = pRec->pDest;
 
-                rc = PGMPhysSimpleReadGCPtr(pVM, curInstr, pPatch->patch.pPrivInstrGC, pPatch->patch.cbPrivInstr);
+                rc = PGMPhysSimpleReadGCPtr(VMMGetCpu0(pVM), curInstr, pPatch->patch.pPrivInstrGC, pPatch->patch.cbPrivInstr);
                 Assert(RT_SUCCESS(rc) || rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT);
 
@@ -678 +678 @@
                 {
                     *(RTRCPTR *)&curInstr[pPatch->patch.cbPrivInstr - sizeof(RTRCPTR)] = pRec->pDest;
-                    rc = PGMPhysSimpleDirtyWriteGCPtr(pVM, pRec->pSource, curInstr, pPatch->patch.cbPrivInstr);
+                    rc = PGMPhysSimpleDirtyWriteGCPtr(VMMGetCpu0(pVM), pRec->pSource, curInstr, pPatch->patch.cbPrivInstr);
                     AssertRC(rc);
                 }
@@ -728 +728 @@
                  * Read old patch jump and compare it to the one we previously installed
                  */
-                rc = PGMPhysSimpleReadGCPtr(pVM, temp, pPatch->patch.pPrivInstrGC, pPatch->patch.cbPatchJump);
+                rc = PGMPhysSimpleReadGCPtr(VMMGetCpu0(pVM), temp, pPatch->patch.pPrivInstrGC, pPatch->patch.cbPatchJump);
                 Assert(RT_SUCCESS(rc) || rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT);
 
@@ -751 +751 @@
                 if (RT_SUCCESS(rc))
                 {
-                    rc = PGMPhysSimpleDirtyWriteGCPtr(pVM, pJumpOffGC, &displ, sizeof(displ));
+                    rc = PGMPhysSimpleDirtyWriteGCPtr(VMMGetCpu0(pVM), pJumpOffGC, &displ, sizeof(displ));
                     AssertRC(rc);
                 }
@@ -790 +790 @@
     {
         /** @note pPrivInstrHC is probably not valid anymore */
-        rc = PGMPhysGCPtr2R3Ptr(pVM, pPatch->patch.pPrivInstrGC, (PRTR3PTR)&pPatch->patch.pPrivInstrHC);
+        rc = PGMPhysGCPtr2R3Ptr(VMMGetCpu0(pVM), pPatch->patch.pPrivInstrGC, (PRTR3PTR)&pPatch->patch.pPrivInstrHC);
         if (rc == VINF_SUCCESS)
         {
@@ -995 +995 @@
     }
 
-    rc = PGMPhysGCPtr2R3Ptr(pVM, pGCPtr, (void **)&pHCPtr);
+    rc = PGMPhysGCPtr2R3Ptr(VMMGetCpu0(pVM), pGCPtr, (void **)&pHCPtr);
     if (rc != VINF_SUCCESS)
     {
@@ -2529 +2529 @@
         *(uint32_t *)&temp[1] = (RTRCUINTPTR)PATCHCODE_PTR_GC(pPatch) - ((RTRCUINTPTR)pPatch->pPrivInstrGC + SIZEOF_NEARJUMP32);    //return address
     }
-    rc = PGMPhysSimpleDirtyWriteGCPtr(pVM, pPatch->pPrivInstrGC, temp, pPatch->cbPatchJump);
+    rc = PGMPhysSimpleDirtyWriteGCPtr(VMMGetCpu0(pVM), pPatch->pPrivInstrGC, temp, pPatch->cbPatchJump);
     AssertRC(rc);
 
@@ -2567 +2567 @@
 
     /* Restore original code (privileged instruction + following instructions that were overwritten because of the 5/6 byte jmp). */
-    int rc = PGMPhysSimpleDirtyWriteGCPtr(pVM, pPatch->pPrivInstrGC, pPatch->aPrivInstr, pPatch->cbPatchJump);
+    int rc = PGMPhysSimpleDirtyWriteGCPtr(VMMGetCpu0(pVM), pPatch->pPrivInstrGC, pPatch->aPrivInstr, pPatch->cbPatchJump);
 #ifdef DEBUG
     if (rc == VINF_SUCCESS)
@@ -2626 +2626 @@
     *(uint32_t *)&temp[1] = (uint32_t)pTargetGC - ((uint32_t)pPatch->pPrivInstrGC + SIZEOF_NEARJUMP32);    //return address
 
-    rc = PGMPhysSimpleDirtyWriteGCPtr(pVM, pPatch->pPrivInstrGC, temp, pPatch->cbPatchJump);
+    rc = PGMPhysSimpleDirtyWriteGCPtr(VMMGetCpu0(pVM), pPatch->pPrivInstrGC, temp, pPatch->cbPatchJump);
     AssertRC(rc);
 
@@ -2792 +2792 @@
     pPatch->cbPatchJump = SIZEOF_NEARJUMP32;
 
-    rc = PGMPhysSimpleReadGCPtr(pVM, pPatch->aPrivInstr, pPatch->pPrivInstrGC, pPatch->cbPatchJump);
+    rc = PGMPhysSimpleReadGCPtr(VMMGetCpu0(pVM), pPatch->aPrivInstr, pPatch->pPrivInstrGC, pPatch->cbPatchJump);
     AssertRC(rc);
 
@@ -3524 +3524 @@
     pPatch->cbPatchJump = SIZEOF_NEARJUMP32;
 
-    rc = PGMPhysSimpleReadGCPtr(pVM, pPatch->aPrivInstr, pPatch->pPrivInstrGC, pPatch->cbPatchJump);
+    rc = PGMPhysSimpleReadGCPtr(VMMGetCpu0(pVM), pPatch->aPrivInstr, pPatch->pPrivInstrGC, pPatch->cbPatchJump);
     AssertRC(rc);
 
@@ -3600 +3600 @@
 
     /* Save original instruction. */
-    rc = PGMPhysSimpleReadGCPtr(pVM, pPatch->aPrivInstr, pPatch->pPrivInstrGC, pPatch->cbPrivInstr);
+    rc = PGMPhysSimpleReadGCPtr(VMMGetCpu0(pVM), pPatch->aPrivInstr, pPatch->pPrivInstrGC, pPatch->cbPrivInstr);
     AssertRC(rc);
 
@@ -3606 +3606 @@
 
     /* Replace address with that of the cached item. */
-    rc = PGMPhysSimpleDirtyWriteGCPtr(pVM, pInstrGC + pCpu->opsize - sizeof(RTRCPTR), &pVM->patm.s.mmio.pCachedData, sizeof(RTRCPTR));
+    rc = PGMPhysSimpleDirtyWriteGCPtr(VMMGetCpu0(pVM), pInstrGC + pCpu->opsize - sizeof(RTRCPTR), &pVM->patm.s.mmio.pCachedData, sizeof(RTRCPTR));
     AssertRC(rc);
     if (RT_FAILURE(rc))
@@ -3713 +3713 @@
 
     /* Replace first opcode byte with 'int 3'. */
-    rc = PGMPhysSimpleDirtyWriteGCPtr(pVM, pPatch->pPrivInstrGC, &ASMInt3, sizeof(ASMInt3));
+    rc = PGMPhysSimpleDirtyWriteGCPtr(VMMGetCpu0(pVM), pPatch->pPrivInstrGC, &ASMInt3, sizeof(ASMInt3));
     AssertRC(rc);
 
@@ -3737 +3737 @@
 
     /* Restore first opcode byte. */
-    rc = PGMPhysSimpleDirtyWriteGCPtr(pVM, pPatch->pPrivInstrGC, pPatch->aPrivInstr, sizeof(ASMInt3));
+    rc = PGMPhysSimpleDirtyWriteGCPtr(VMMGetCpu0(pVM), pPatch->pPrivInstrGC, pPatch->aPrivInstr, sizeof(ASMInt3));
     AssertRC(rc);
     return rc;
@@ -3773 +3773 @@
 
     /* Save the original instruction. */
-    rc = PGMPhysSimpleReadGCPtr(pVM, pPatch->aPrivInstr, pPatch->pPrivInstrGC, pPatch->cbPrivInstr);
+    rc = PGMPhysSimpleReadGCPtr(VMMGetCpu0(pVM), pPatch->aPrivInstr, pPatch->pPrivInstrGC, pPatch->cbPrivInstr);
     AssertRC(rc);
     pPatch->cbPatchJump = sizeof(ASMInt3);  /* bit of a misnomer in this case; size of replacement instruction. */
@@ -3877 +3877 @@
     pPatch->cbPatchJump = pCpu->opsize;
 
-    rc = PGMPhysSimpleReadGCPtr(pVM, pPatch->aPrivInstr, pPatch->pPrivInstrGC, pPatch->cbPatchJump);
+    rc = PGMPhysSimpleReadGCPtr(VMMGetCpu0(pVM), pPatch->aPrivInstr, pPatch->pPrivInstrGC, pPatch->cbPatchJump);
     AssertRC(rc);
 
@@ -3959 +3959 @@
     bool disret;
     int rc;
+    PVMCPU pVCpu = VMMGetCpu0(pVM);
 
     if (!pVM || pInstrGC == 0 || (flags & ~(PATMFL_CODE32|PATMFL_IDTHANDLER|PATMFL_INTHANDLER|PATMFL_SYSENTER|PATMFL_TRAPHANDLER|PATMFL_DUPLICATE_FUNCTION|PATMFL_REPLACE_FUNCTION_CALL|PATMFL_GUEST_SPECIFIC|PATMFL_INT3_REPLACEMENT|PATMFL_TRAPHANDLER_WITH_ERRORCODE|PATMFL_IDTHANDLER_WITHOUT_ENTRYPOINT|PATMFL_MMIO_ACCESS|PATMFL_TRAMPOLINE|PATMFL_INSTR_HINT|PATMFL_JUMP_CONFLICT)))
@@ -3990 +3991 @@
 
     /* Make sure the code selector is wide open; otherwise refuse. */
-    pCtx = CPUMQueryGuestCtxPtr(pVM);
-    if (CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx)) == 0)
+    pCtx = CPUMQueryGuestCtxPtr(pVCpu);
+    if (CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0)
     {
         RTRCPTR pInstrGCFlat = SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pInstrGC);
@@ -4107 +4108 @@
 
     RTGCPHYS GCPhys;
-    rc = PGMGstGetPage(pVM, pInstrGC, NULL, &GCPhys);
+    rc = PGMGstGetPage(pVM, pVCpu, pInstrGC, NULL, &GCPhys);
     if (rc != VINF_SUCCESS)
     {
@@ -4402 +4403 @@
     uint8_t *pInstrHC;
 
-    int rc = PGMPhysGCPtr2R3Ptr(pVM, pInstrGC, (PRTR3PTR)&pInstrHC);
+    int rc = PGMPhysGCPtr2R3Ptr(VMMGetCpu0(pVM), pInstrGC, (PRTR3PTR)&pInstrHC);
     if (rc == VINF_SUCCESS)
     {
@@ -4999 +5000 @@
 
                 /** pPrivInstrHC is probably not valid anymore */
-                rc = PGMPhysGCPtr2R3Ptr(pVM, pPatchRec->patch.pPrivInstrGC, (PRTR3PTR)&pPatchRec->patch.pPrivInstrHC);
+                rc = PGMPhysGCPtr2R3Ptr(VMMGetCpu0(pVM), pPatchRec->patch.pPrivInstrGC, (PRTR3PTR)&pPatchRec->patch.pPrivInstrHC);
                 if (rc == VINF_SUCCESS)
                 {
@@ -5007 +5008 @@
 
                     /* Let's first check if the guest code is still the same. */
-                    rc = PGMPhysSimpleReadGCPtr(pVM, temp, pPatch->pPrivInstrGC, pPatch->cbPatchJump);
+                    rc = PGMPhysSimpleReadGCPtr(VMMGetCpu0(pVM), temp, pPatch->pPrivInstrGC, pPatch->cbPatchJump);
                     Assert(rc == VINF_SUCCESS || rc == VERR_PAGE_TABLE_NOT_PRESENT || rc == VERR_PAGE_NOT_PRESENT);
                     if (rc == VINF_SUCCESS)
@@ -5049 +5050 @@
 
             /* Let's first check if the guest code is still the same. */
-            rc = PGMPhysSimpleReadGCPtr(pVM, temp, pPatch->pPrivInstrGC, pPatch->cbPatchJump);
+            rc = PGMPhysSimpleReadGCPtr(VMMGetCpu0(pVM), temp, pPatch->pPrivInstrGC, pPatch->cbPatchJump);
             Assert(rc == VINF_SUCCESS || rc == VERR_PAGE_TABLE_NOT_PRESENT || rc == VERR_PAGE_NOT_PRESENT);
             if (rc == VINF_SUCCESS)
@@ -5218 +5219 @@
                 Assert(!(pPatch->flags & PATMFL_PATCHED_GUEST_CODE));
                 /** @todo -> pPrivInstrHC is probably not valid anymore */
-                rc = PGMPhysGCPtr2R3Ptr(pVM, pPatchRec->patch.pPrivInstrGC, (PRTR3PTR)&pPatchRec->patch.pPrivInstrHC);
+                rc = PGMPhysGCPtr2R3Ptr(VMMGetCpu0(pVM), pPatchRec->patch.pPrivInstrGC, (PRTR3PTR)&pPatchRec->patch.pPrivInstrHC);
                 if (rc == VINF_SUCCESS)
                 {
@@ -5231 +5232 @@
 
                     // let's first check if the guest code is still the same
-                    int rc = PGMPhysSimpleReadGCPtr(pVM, temp, pPatch->pPrivInstrGC, pPatch->cbPatchJump);
+                    int rc = PGMPhysSimpleReadGCPtr(VMMGetCpu0(pVM), temp, pPatch->pPrivInstrGC, pPatch->cbPatchJump);
                     AssertRC(rc);
 
@@ -5270 +5271 @@
 
                 /* Let's first check if the guest code is still the same. */
-                int rc = PGMPhysSimpleReadGCPtr(pVM, temp, pPatch->pPrivInstrGC, pPatch->cbPatchJump);
+                int rc = PGMPhysSimpleReadGCPtr(VMMGetCpu0(pVM), temp, pPatch->pPrivInstrGC, pPatch->cbPatchJump);
                 AssertRC(rc);
 
@@ -5817 +5818 @@
     uint32_t     cbDirty;
     PRECPATCHTOGUEST pRec;
+    PVMCPU       pVCpu = VMMGetCpu0(pVM);
 
     Log(("patmR3HandleDirtyInstr: dirty instruction at %RRv (%RRv)\n", pEip, pPatchToGuestRec->pOrgInstrGC));
@@ -5841 +5843 @@
 
         /* Only harmless instructions are acceptable. */
-        rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCurPatchInstrGC, &CpuOld, 0);
+        rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCurPatchInstrGC, &CpuOld, 0);
         if (    RT_FAILURE(rc)
             ||  !(CpuOld.pCurInstr->optype & OPTYPE_HARMLESS))
@@ -5856 +5858 @@
         char szBuf[256];
         szBuf[0] = '\0';
-        DBGFR3DisasInstr(pVM, pCtx->cs, pCurPatchInstrGC, szBuf, sizeof(szBuf));
+        DBGFR3DisasInstr(pVM, pVCpu, pCtx->cs, pCurPatchInstrGC, szBuf, sizeof(szBuf));
         Log(("DIRTY: %s\n", szBuf));
 #endif
@@ -5891 +5893 @@
             bool fValidInstr;
 
-            rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCurInstrGC, &CpuNew, 0);
+            rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCurInstrGC, &CpuNew, 0);
 
             fValidInstr = !!(CpuNew.pCurInstr->optype & OPTYPE_HARMLESS);
@@ -5918 +5920 @@
                 char szBuf[256];
                 szBuf[0] = '\0';
-                DBGFR3DisasInstr(pVM, pCtx->cs, pCurInstrGC, szBuf, sizeof(szBuf));
+                DBGFR3DisasInstr(pVM, pVCpu, pCtx->cs, pCurInstrGC, szBuf, sizeof(szBuf));
                 Log(("NEW:   %s\n", szBuf));
 #endif
 
                 /* Copy the new instruction. */
-                rc = PGMPhysSimpleReadGCPtr(pVM, pCurPatchInstrHC, pCurInstrGC, CpuNew.opsize);
+                rc = PGMPhysSimpleReadGCPtr(VMMGetCpu0(pVM), pCurPatchInstrHC, pCurInstrGC, CpuNew.opsize);
                 AssertRC(rc);
 
@@ -5934 +5936 @@
                 char szBuf[256];
                 szBuf[0] = '\0';
-                DBGFR3DisasInstr(pVM, pCtx->cs, pCurInstrGC, szBuf, sizeof(szBuf));
+                DBGFR3DisasInstr(pVM, pVCpu, pCtx->cs, pCurInstrGC, szBuf, sizeof(szBuf));
                 Log(("NEW:   %s (FAILED)\n", szBuf));
 #endif
@@ -5998 +6000 @@
     int              rc ;
     PRECPATCHTOGUEST pPatchToGuestRec = 0;
+    PVMCPU           pVCpu = VMMGetCpu0(pVM);
+
+    Assert(pVM->cCPUs == 1);
 
     pNewEip   = 0;
@@ -6058 +6063 @@
     {
         DISCPUSTATE Cpu;
-        rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pEip, &Cpu, "PIF Trap: ");
+        rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pEip, &Cpu, "PIF Trap: ");
         AssertRC(rc);
 
@@ -6073 +6078 @@
             if (Cpu.pCurInstr->opcode == OP_PUSH)
             {
-                rc = PGMShwGetPage(pVM, pCtx->esp, &fFlags, NULL);
+                rc = PGMShwGetPage(pVM, pVCpu, pCtx->esp, &fFlags, NULL);
                 if (    rc == VINF_SUCCESS
                     &&  ((fFlags & (X86_PTE_P|X86_PTE_RW)) == (X86_PTE_P|X86_PTE_RW)) )
@@ -6094 +6099 @@
 
             /* Typical pushf (most patches)/push (call patch) trap because of a monitored page. */
-            rc = PGMShwModifyPage(pVM, pCtx->esp, 1, X86_PTE_RW, ~(uint64_t)X86_PTE_RW);
+            rc = PGMShwModifyPage(pVM, pVCpu, pCtx->esp, 1, X86_PTE_RW, ~(uint64_t)X86_PTE_RW);
             AssertMsgRC(rc, ("PGMShwModifyPage -> rc=%Rrc\n", rc));
             if (rc == VINF_SUCCESS)
@@ -6100 +6105 @@
 
                 /* The guest page *must* be present. */
-                rc = PGMGstGetPage(pVM, pCtx->esp, &fFlags, NULL);
+                rc = PGMGstGetPage(pVM, pVCpu, pCtx->esp, &fFlags, NULL);
                 if (rc == VINF_SUCCESS && (fFlags & X86_PTE_P))
                 {
@@ -6129 +6134 @@
         char szBuf[256];
         szBuf[0] = '\0';
-        DBGFR3DisasInstr(pVM, pCtx->cs, pEip, szBuf, sizeof(szBuf));
+        DBGFR3DisasInstr(pVM, pVCpu, pCtx->cs, pEip, szBuf, sizeof(szBuf));
 
         /* Very bad. We crashed in emitted code. Probably stack? */
@@ -6135 +6140 @@
         {
             AssertReleaseMsg(pVM->patm.s.pGCStateHC->fPIF == 1,
-                            ("Crash in patch code %RRv (%RRv) esp=%RX32\nPatch state=%x flags=%x fDirty=%d\n%s\n", pEip, pNewEip, CPUMGetGuestESP(pVM), pPatch->patch.uState, pPatch->patch.flags, pPatchToGuestRec->fDirty, szBuf));
+                            ("Crash in patch code %RRv (%RRv) esp=%RX32\nPatch state=%x flags=%x fDirty=%d\n%s\n", pEip, pNewEip, CPUMGetGuestESP(pVCpu), pPatch->patch.uState, pPatch->patch.flags, pPatchToGuestRec->fDirty, szBuf));
         }
         else
             AssertReleaseMsg(pVM->patm.s.pGCStateHC->fPIF == 1,
-                            ("Crash in patch code %RRv (%RRv) esp=%RX32\n%s\n", pEip, pNewEip, CPUMGetGuestESP(pVM), szBuf));
-        EMR3FatalError(pVM, VERR_INTERNAL_ERROR);
+                            ("Crash in patch code %RRv (%RRv) esp=%RX32\n%s\n", pEip, pNewEip, CPUMGetGuestESP(pVCpu), szBuf));
+        EMR3FatalError(pVCpu, VERR_INTERNAL_ERROR);
     }
 
@@ -6191 +6196 @@
             PCPUMCTX pCtx;
 
-            pCtx = CPUMQueryGuestCtxPtr(pVM);
-
-            rc = PGMPhysSimpleReadGCPtr(pVM, &retaddr, pCtx->esp, sizeof(retaddr));
+            pCtx = CPUMQueryGuestCtxPtr(pVCpu);
+
+            rc = PGMPhysSimpleReadGCPtr(pVCpu,  &retaddr, pCtx->esp, sizeof(retaddr));
             AssertRC(rc);
 
@@ -6228 +6233 @@
         }
 #endif
-        EMSetInhibitInterruptsPC(pVM, pNewEip);
+        EMSetInhibitInterruptsPC(pVM, pVCpu, pNewEip);
         pVM->patm.s.pGCStateHC->GCPtrInhibitInterrupts = 0;
     }
@@ -6234 +6239 @@
     Log2(("pPatchBlockGC %RRv - pEip %RRv corresponding GC address %RRv\n", PATCHCODE_PTR_GC(&pPatch->patch), pEip, pNewEip));
 #ifdef LOG_ENABLED
-    CPUMR3DisasmInstr(pVM, pCtx, pNewEip, "PATCHRET: ");
+    CPUMR3DisasmInstr(pVM, pVCpu, pCtx, pNewEip, "PATCHRET: ");
 #endif
     if (pNewEip >= pPatch->patch.pPrivInstrGC && pNewEip < pPatch->patch.pPrivInstrGC + pPatch->patch.cbPatchJump)

trunk/src/VBox/VMM/PATM/PATMGuest.cpp

@@ -99 +99 @@
 int PATMPatchSysenterXP(PVM pVM, RTGCPTR32 pInstrGC, PPATMPATCHREC pPatchRec)
 {
-    PPATCHINFO pPatch = &pPatchRec->patch;
-    uint8_t   uTemp[16];
+    PPATCHINFO  pPatch = &pPatchRec->patch;
+    uint8_t     uTemp[16];
     RTGCPTR32   lpfnKiFastSystemCall, lpfnKiIntSystemCall = 0; /* (initializing it to shut up warning.) */
-    int       rc, i;
+    int         rc, i;
+    PVMCPU      pVCpu = VMMGetCpu0(pVM); 
 
     Assert(sizeof(uTemp) > sizeof(uFnKiIntSystemCall));
@@ -111 +112 @@
     /* check the epilog of KiFastSystemCall */
     lpfnKiFastSystemCall = pInstrGC - 2;
-    rc = PGMPhysSimpleReadGCPtr(pVM, uTemp, lpfnKiFastSystemCall, sizeof(uFnKiFastSystemCall));
+    rc = PGMPhysSimpleReadGCPtr(pVCpu, uTemp, lpfnKiFastSystemCall, sizeof(uFnKiFastSystemCall));
     if (    RT_FAILURE(rc)
         ||  memcmp(uFnKiFastSystemCall, uTemp, sizeof(uFnKiFastSystemCall)))
@@ -121 +122 @@
     for (i=0;i<64;i++)
     {
-        rc = PGMPhysSimpleReadGCPtr(pVM, uTemp, pInstrGC + i, sizeof(uFnKiIntSystemCall));
+        rc = PGMPhysSimpleReadGCPtr(pVCpu, uTemp, pInstrGC + i, sizeof(uFnKiIntSystemCall));
         if(RT_FAILURE(rc))
         {
@@ -146 +147 @@
 
     // make a copy of the guest code bytes that will be overwritten
-    rc = PGMPhysSimpleReadGCPtr(pVM, pPatch->aPrivInstr, pPatch->pPrivInstrGC, SIZEOF_NEARJUMP32);
+    rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aPrivInstr, pPatch->pPrivInstrGC, SIZEOF_NEARJUMP32);
     AssertRC(rc);
 
@@ -152 +153 @@
     uTemp[0] = 0xE9;
     *(RTGCPTR32 *)&uTemp[1] = lpfnKiIntSystemCall - (pInstrGC + SIZEOF_NEARJUMP32);
-    rc = PGMPhysSimpleDirtyWriteGCPtr(pVM, pInstrGC, uTemp, SIZEOF_NEARJUMP32);
+    rc = PGMPhysSimpleDirtyWriteGCPtr(pVCpu, pInstrGC, uTemp, SIZEOF_NEARJUMP32);
     if (RT_FAILURE(rc))
     {
@@ -189 +190 @@
     /* Guest OS specific patch; check heuristics first */
 
-    rc = PGMPhysSimpleReadGCPtr(pVM, uTemp, pInstrGC, RT_MAX(sizeof(uFnOpenBSDHandlerPrefix1), sizeof(uFnOpenBSDHandlerPrefix2)));
+    rc = PGMPhysSimpleReadGCPtr(VMMGetCpu0(pVM), uTemp, pInstrGC, RT_MAX(sizeof(uFnOpenBSDHandlerPrefix1), sizeof(uFnOpenBSDHandlerPrefix2)));
     if (    RT_FAILURE(rc)
         || (    memcmp(uFnOpenBSDHandlerPrefix1, uTemp, sizeof(uFnOpenBSDHandlerPrefix1))

trunk/src/VBox/VMM/PATM/PATMInternal.h

@@ -704 +704 @@
 {
     PATMDISASM disinfo;
-    disinfo.pVM    = pVM;
-    disinfo.pPatchInfo = pPatch;
-    disinfo.pInstrHC = InstrHC;
-    disinfo.pInstrGC = InstrGC;
-    disinfo.fReadFlags = fReadFlags;
-    (pCpu)->pfnReadBytes  = patmReadBytes;
+    disinfo.pVM         = pVM;
+    disinfo.pPatchInfo  = pPatch;
+    disinfo.pInstrHC    = InstrHC;
+    disinfo.pInstrGC    = InstrGC;
+    disinfo.fReadFlags  = fReadFlags;
+    (pCpu)->pfnReadBytes = patmReadBytes;
     (pCpu)->apvUserData[0] = &disinfo;
     return RT_SUCCESS(DISInstr(pCpu, InstrGC, 0, pOpsize, pszOutput));

trunk/src/VBox/VMM/PATM/PATMPatch.cpp

@@ -404 +404 @@
 static int patmPatchReadBytes(PVM pVM, uint8_t *pDest, RTRCPTR pSrc, uint32_t cb)
 {
-    int rc = PGMPhysSimpleReadGCPtr(pVM, pDest, pSrc, cb);
+    int rc = PGMPhysSimpleReadGCPtr(&pVM->aCpus[0], pDest, pSrc, cb);
     AssertRCReturn(rc, rc);
     /*

trunk/src/VBox/VMM/PATM/PATMSSM.cpp

@@ -583 +583 @@
         pPatchRec->patch.pPrivInstrHC   = 0;
         /* The GC virtual ptr is fixed, but we must convert it manually again to HC. */
-        int rc2 = rc = PGMPhysGCPtr2R3Ptr(pVM, pPatchRec->patch.pPrivInstrGC, (PRTR3PTR)&pPatchRec->patch.pPrivInstrHC);
+        int rc2 = rc = PGMPhysGCPtr2R3Ptr(VMMGetCpu0(pVM), pPatchRec->patch.pPrivInstrGC, (PRTR3PTR)&pPatchRec->patch.pPrivInstrHC);
         /* Can fail due to page or page table not present. */
 
@@ -961 +961 @@
              * Read old patch jump and compare it to the one we previously installed
              */
-            int rc = PGMPhysSimpleReadGCPtr(pVM, temp, pPatch->pPrivInstrGC, pPatch->cbPatchJump);
+            int rc = PGMPhysSimpleReadGCPtr(VMMGetCpu0(pVM), temp, pPatch->pPrivInstrGC, pPatch->cbPatchJump);
             Assert(RT_SUCCESS(rc) || rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT);
 
@@ -984 +984 @@
             if (RT_SUCCESS(rc))
             {
-                rc = PGMPhysSimpleDirtyWriteGCPtr(pVM, pJumpOffGC, &displ, sizeof(displ));
+                rc = PGMPhysSimpleDirtyWriteGCPtr(VMMGetCpu0(pVM), pJumpOffGC, &displ, sizeof(displ));
                 AssertRC(rc);
             }

trunk/src/VBox/VMM/PATM/VMMAll/PATMAll.cpp

@@ -34 +34 @@
 #include "PATMInternal.h"
 #include <VBox/vm.h>
+#include <VBox/vmm.h>
 #include "PATMA.h"
 
@@ -190 +191 @@
         if (CTXSUFF(pVM->patm.s.pGCState)->GCPtrInhibitInterrupts == (RTRCPTR)pCtxCore->eip)
         {
-            EMSetInhibitInterruptsPC(pVM, pCtxCore->eip);
+            EMSetInhibitInterruptsPC(pVM, VMMGetCpu0(pVM), pCtxCore->eip);
         }
         CTXSUFF(pVM->patm.s.pGCState)->GCPtrInhibitInterrupts = 0;
@@ -298 +299 @@
 VMMDECL(bool) PATMAreInterruptsEnabled(PVM pVM)
 {
-    PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVM);
+    PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpu0(pVM));
 
     return PATMAreInterruptsEnabledByCtxCore(pVM, CPUMCTX2CORE(pCtx));
@@ -382 +383 @@
 VMMDECL(int) PATMSysCall(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu)
 {
-    PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVM);
+    PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpu0(pVM));
 
     if (pCpu->pCurInstr->opcode == OP_SYSENTER)

trunk/src/VBox/VMM/PATM/VMMGC/CSAMGC.cpp

@@ -67 +67 @@
     bool         fPatchCode = PATMIsPatchGCAddr(pVM, (RTRCPTR)pRegFrame->eip);
     int          rc;
+    PVMCPU       pVCpu = VMMGetCpu0(pVM);
 
     Assert(pVM->csam.s.cDirtyPages < CSAM_MAX_DIRTY_PAGES);
@@ -87 +88 @@
          * Make this particular page R/W.
          */
-        int rc = PGMShwModifyPage(pVM, pvFault, 1, X86_PTE_RW, ~(uint64_t)X86_PTE_RW);
+        int rc = PGMShwModifyPage(pVM, pVCpu, pvFault, 1, X86_PTE_RW, ~(uint64_t)X86_PTE_RW);
         AssertMsgRC(rc, ("PGMShwModifyPage -> rc=%Rrc\n", rc));
         ASMInvalidatePage((void *)pvFault);
@@ -128 +129 @@
      */
     Log(("CSAMGCCodePageWriteHandler: enabled r/w for page %RGv\n", pvFault));
-    rc = PGMShwModifyPage(pVM, pvFault, 1, X86_PTE_RW, ~(uint64_t)X86_PTE_RW);
+    rc = PGMShwModifyPage(pVM, pVCpu, pvFault, 1, X86_PTE_RW, ~(uint64_t)X86_PTE_RW);
     AssertMsgRC(rc, ("PGMShwModifyPage -> rc=%Rrc\n", rc));
     ASMInvalidatePage((void *)pvFault);

trunk/src/VBox/VMM/PATM/VMMGC/PATMGC.cpp

@@ -117 +117 @@
 
             LogFlow(("PATMHandleWriteToPatchPage: Interpret %x accessing %RRv\n", pRegFrame->eip, GCPtr));
-            int rc = EMInterpretInstruction(pVM, pRegFrame, (RTGCPTR)(RTRCUINTPTR)GCPtr, &cb);
+            int rc = EMInterpretInstruction(pVM, VMMGetCpu0(pVM), pRegFrame, (RTGCPTR)(RTRCUINTPTR)GCPtr, &cb);
             if (rc == VINF_SUCCESS)
             {
@@ -281 +281 @@
                 pVM->patm.s.CTXSUFF(pGCState)->Restore.uFlags = 0;
 
-                rc = EMInterpretIret(pVM, pRegFrame);
+                rc = EMInterpretIret(pVM, VMMGetCpu0(pVM), pRegFrame);
                 if (RT_SUCCESS(rc))
                 {
@@ -517 +517 @@
             }
 
-            rc = EMInterpretInstructionCPU(pVM, &cpu, pRegFrame, 0 /* not relevant here */, &size);
+            rc = EMInterpretInstructionCPU(pVM, VMMGetCpu0(pVM), &cpu, pRegFrame, 0 /* not relevant here */, &size);
             if (rc != VINF_SUCCESS)
             {