Changeset 19326 in vbox for trunk

Timestamp:

May 4, 2009 2:05:45 PM (16 years ago)

Author:

vboxsync

Message:

Started with TLB shootdown.

Location:

trunk

Files:

• include/VBox/vm.h (modified) (1 diff)
• src/VBox/VMM/HWACCM.cpp (modified) (1 diff)
• src/VBox/VMM/HWACCMInternal.h (modified) (3 diffs)
• src/VBox/VMM/VMMR0/HWSVMR0.cpp (modified) (1 diff)
• src/VBox/VMM/VMMR0/HWVMXR0.cpp (modified) (2 diffs)

trunk/include/VBox/vm.h

@@ -258 +258 @@
 /** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
 #define VMCPU_FF_INHIBIT_INTERRUPTS         RT_BIT_32(24)
+/** Check for pending TLB shootdown actions. */
+#define VMCPU_FF_TLB_SHOOTDOWN              RT_BIT_32(25)
 /** CSAM needs to scan the page that's being executed */
 #define VMCPU_FF_CSAM_SCAN_PAGE             RT_BIT_32(26)

trunk/src/VBox/VMM/HWACCM.cpp

@@ -342 +342 @@
         HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID,              "/HWACCM/CPU%d/Flush/TLB/ASID");
         HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga,        "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
-
+        HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown,           "/HWACCM/CPU%d/Flush/TLB/Shootdown");
+        
         HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset,              "/HWACCM/CPU%d/TSC/Offset");
         HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept,           "/HWACCM/CPU%d/TSC/Intercept");

trunk/src/VBox/VMM/HWACCMInternal.h

@@ -122 +122 @@
 /** Maxium resume loops allowed in ring 0 (safety precaution) */
 #define HWACCM_MAX_RESUME_LOOPS             1024
+
+/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
+#define HWACCM_MAX_TLB_SHOOTDOWN_PAGES      16
 
 /** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
@@ -475 +478 @@
     /* Current ASID in use by the VM */
     RTUINT                      uCurrentASID;
+
+    /** To keep track of pending TLB shootdown pages. (SMP guest only) */
+    RTGCPTR                     aTlbShootdownPages[HWACCM_MAX_TLB_SHOOTDOWN_PAGES];
+    unsigned                    cTlbShootdownPages;
 
     struct
@@ -632 +639 @@
     STAMCOUNTER             StatFlushASID;
     STAMCOUNTER             StatFlushTLBInvlpga;
+    STAMCOUNTER             StatTlbShootdown;
 
     STAMCOUNTER             StatSwitchGuestIrq;

trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

@@ -1028 +1028 @@
         Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB || pVCpu->hwaccm.s.fForceTLBFlush);
         pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVCpu->hwaccm.s.fForceTLBFlush;
-    }
+
+        if (    !pVM->hwaccm.s.svm.fAlwaysFlushTLB
+            &&  VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
+        {
+            /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
+            STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
+            for (unsigned i=0;i<pVCpu->hwaccm.s.cTlbShootdownPages;i++)
+                SVMR0InvlpgA(pVCpu->hwaccm.s.aTlbShootdownPages[i], pVMCB->ctrl.TLBCtrl.n.u32ASID);
+        }
+    }
+    pVCpu->hwaccm.s.cTlbShootdownPages = 0;
+    VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
+
     AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
     AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));

trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

@@ -1829 +1829 @@
 
     pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
-    pCpu->fFlushTLB         = false;
+    pCpu->fFlushTLB           = false;
 
     if (pVCpu->hwaccm.s.fForceTLBFlush)
+    {
         vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
+    }
+    else
+    if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
+    {
+        /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
+        STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
+        for (unsigned i=0;i<pVCpu->hwaccm.s.cTlbShootdownPages;i++)
+        {
+            /* aTlbShootdownPages contains physical addresses in this case. */
+            vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, pVCpu->hwaccm.s.aTlbShootdownPages[i]);
+        }
+    }
+    pVCpu->hwaccm.s.cTlbShootdownPages = 0;
+    VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
 
 #ifdef VBOX_WITH_STATISTICS
@@ -1895 +1910 @@
     {
         Assert(!pCpu->fFlushTLB);
-
-        if (!pCpu->uCurrentASID || !pVCpu->hwaccm.s.uCurrentASID)
-            pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
-    }
+        Assert(pVCpu->hwaccm.s.uCurrentASID && pCpu->uCurrentASID);
+
+        if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
+        {
+            /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
+            STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
+            for (unsigned i=0;i<pVCpu->hwaccm.s.cTlbShootdownPages;i++)
+                vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, pVCpu->hwaccm.s.aTlbShootdownPages[i]);
+        }
+    }
+    pVCpu->hwaccm.s.cTlbShootdownPages = 0;
+    VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
+
     AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
     AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));