- Timestamp:
- May 19, 2009 3:12:25 PM (16 years ago)
- svn:sync-xref-src-repo-rev:
- 47489
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 7 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/PGMInternal.h
r19808 r19833 352 352 #endif 353 353 354 /** @def PGM_INVL_ GUEST_TLBS()354 /** @def PGM_INVL_VCPU_TLBS() 355 355 * Invalidates all guest TLBs. 356 356 */ 357 357 #ifdef IN_RC 358 # define PGM_INVL_ GUEST_TLBS(pVCpu) ASMReloadCR3()358 # define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3() 359 359 #elif defined(IN_RING0) 360 # define PGM_INVL_ GUEST_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)360 # define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu) 361 361 #else 362 # define PGM_INVL_ GUEST_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)362 # define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu) 363 363 #endif 364 364 -
trunk/src/VBox/VMM/PGMPhys.cpp
r19808 r19833 2682 2682 pgmUnlock(pVM); 2683 2683 if (fFlushTLB) 2684 PGM_INVL_ GUEST_TLBS(VMMGetCpu(pVM));2684 PGM_INVL_VCPU_TLBS(VMMGetCpu(pVM)); 2685 2685 2686 2686 return rc; -
trunk/src/VBox/VMM/VMMAll/PGMAll.cpp
r19808 r19833 1867 1867 */ 1868 1868 if (rc == VINF_SUCCESS) 1869 PGM_INVL_ GUEST_TLBS(pVCpu);1869 PGM_INVL_VCPU_TLBS(pVCpu); 1870 1870 return rc; 1871 1871 } … … 1924 1924 1925 1925 /* Flush the TLB */ 1926 PGM_INVL_ GUEST_TLBS(pVCpu);1926 PGM_INVL_VCPU_TLBS(pVCpu); 1927 1927 1928 1928 #ifdef IN_RING3 -
trunk/src/VBox/VMM/VMMAll/PGMAllBth.h
r19808 r19833 989 989 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped)); 990 990 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)) 991 PGM_INVL_ GUEST_TLBS(pVCpu);991 PGM_INVL_VCPU_TLBS(pVCpu); 992 992 return VINF_SUCCESS; 993 993 } … … 1001 1001 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped)); 1002 1002 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)) 1003 PGM_INVL_ GUEST_TLBS(pVCpu);1003 PGM_INVL_VCPU_TLBS(pVCpu); 1004 1004 return VINF_SUCCESS; 1005 1005 } … … 1092 1092 ASMAtomicWriteSize(pPml4eDst, 0); 1093 1093 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs)); 1094 PGM_INVL_ GUEST_TLBS(pVCpu);1094 PGM_INVL_VCPU_TLBS(pVCpu); 1095 1095 return VINF_SUCCESS; 1096 1096 } … … 1106 1106 ASMAtomicWriteSize(pPml4eDst, 0); 1107 1107 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync)); 1108 PGM_INVL_ GUEST_TLBS(pVCpu);1108 PGM_INVL_VCPU_TLBS(pVCpu); 1109 1109 } 1110 1110 else if (!pPml4eSrc->n.u1Accessed) … … 1118 1118 ASMAtomicWriteSize(pPml4eDst, 0); 1119 1119 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs)); 1120 PGM_INVL_ GUEST_TLBS(pVCpu);1120 PGM_INVL_VCPU_TLBS(pVCpu); 1121 1121 } 1122 1122 … … 1132 1132 ASMAtomicWriteSize(pPdpeDst, 0); 1133 1133 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs)); 1134 PGM_INVL_ GUEST_TLBS(pVCpu);1134 PGM_INVL_VCPU_TLBS(pVCpu); 1135 1135 return VINF_SUCCESS; 1136 1136 } … … 1146 1146 ASMAtomicWriteSize(pPdpeDst, 0); 1147 1147 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync)); 1148 PGM_INVL_ GUEST_TLBS(pVCpu);1148 PGM_INVL_VCPU_TLBS(pVCpu); 1149 1149 } 1150 1150 else if (!PdpeSrc.lm.u1Accessed) … … 1158 1158 ASMAtomicWriteSize(pPdpeDst, 0); 1159 1159 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs)); 1160 PGM_INVL_ GUEST_TLBS(pVCpu);1160 PGM_INVL_VCPU_TLBS(pVCpu); 1161 1161 } 1162 1162 # endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */ … … 1190 1190 ASMAtomicWriteSize(pPdeDst, 0); 1191 1191 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync)); 1192 PGM_INVL_ GUEST_TLBS(pVCpu);1192 PGM_INVL_VCPU_TLBS(pVCpu); 1193 1193 } 1194 1194 else if (!PdeSrc.n.u1Accessed) … … 1202 1202 ASMAtomicWriteSize(pPdeDst, 0); 1203 1203 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs)); 1204 PGM_INVL_ GUEST_TLBS(pVCpu);1204 PGM_INVL_VCPU_TLBS(pVCpu); 1205 1205 } 1206 1206 else if (!fIsBigPage) … … 1246 1246 ASMAtomicWriteSize(pPdeDst, 0); 1247 1247 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync)); 1248 PGM_INVL_ GUEST_TLBS(pVCpu);1248 PGM_INVL_VCPU_TLBS(pVCpu); 1249 1249 } 1250 1250 } … … 1920 1920 PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst); 1921 1921 # endif 1922 PGM_INVL_ GUEST_TLBS(pVCpu);1922 PGM_INVL_VCPU_TLBS(pVCpu); 1923 1923 return VINF_PGM_SYNCPAGE_MODIFIED_PDE; 1924 1924 -
trunk/src/VBox/VMM/VMMAll/PGMAllHandler.cpp
r19832 r19833 237 237 if (fFlushTLBs && rc == VINF_SUCCESS) 238 238 { 239 PGM_INVL_ GUEST_TLBS(VMMGetCpu(pVM));239 PGM_INVL_VCPU_TLBS(VMMGetCpu(pVM)); 240 240 Log(("pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs: flushing guest TLBs\n")); 241 241 } … … 415 415 # ifdef IN_RC 416 416 if (fFlushTLBs && rc != VINF_PGM_SYNC_CR3) 417 PGM_INVL_ GUEST_TLBS(VMMGetCpu0(pVM));417 PGM_INVL_VCPU_TLBS(VMMGetCpu0(pVM)); 418 418 # else 419 419 HWACCMFlushAllTLBs(pVM); -
trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp
r19808 r19833 370 370 { 371 371 if (fFlushTLBs) 372 PGM_INVL_ GUEST_TLBS(pVCpu);372 PGM_INVL_VCPU_TLBS(pVCpu); 373 373 Assert(rc2 == VERR_EM_NO_MEMORY); 374 374 return rc2; … … 425 425 if ( fFlushTLBs 426 426 && rc != VINF_PGM_GCPHYS_ALIASED) 427 PGM_INVL_ GUEST_TLBS(pVCpu);427 PGM_INVL_VCPU_TLBS(pVCpu); 428 428 return rc; 429 429 } -
trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp
r19808 r19833 938 938 939 939 /* See use in pgmPoolAccessHandlerSimple(). */ 940 PGM_INVL_ GUEST_TLBS(pVCpu);940 PGM_INVL_VCPU_TLBS(pVCpu); 941 941 942 942 LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc)); … … 1003 1003 #ifdef IN_RC 1004 1004 /* See use in pgmPoolAccessHandlerSimple(). */ 1005 PGM_INVL_ GUEST_TLBS(pVCpu);1005 PGM_INVL_VCPU_TLBS(pVCpu); 1006 1006 #endif 1007 1007 … … 1074 1074 * because we need the stale TLBs in some cases (XP boot). This MUST be fixed properly! 1075 1075 */ 1076 PGM_INVL_ GUEST_TLBS(pVCpu);1076 PGM_INVL_VCPU_TLBS(pVCpu); 1077 1077 #endif 1078 1078 … … 1298 1298 int rc = pgmPoolFlushPage(pPool, pPage); 1299 1299 if (rc == VINF_SUCCESS) 1300 PGM_INVL_ GUEST_TLBS(VMMGetCpu(pVM)); /* see PT handler. */1300 PGM_INVL_VCPU_TLBS(VMMGetCpu(pVM)); /* see PT handler. */ 1301 1301 return rc; 1302 1302 } … … 1467 1467 STAM_COUNTER_INC(&pPool->StatCacheKindMismatches); 1468 1468 pgmPoolFlushPage(pPool, pPage); 1469 PGM_INVL_ GUEST_TLBS(VMMGetCpu(pVM)); /* see PT handler. */1469 PGM_INVL_VCPU_TLBS(VMMGetCpu(pVM)); /* see PT handler. */ 1470 1470 break; 1471 1471 } … … 2064 2064 pPool->cPresent = 0; 2065 2065 pgmUnlock(pVM); 2066 PGM_INVL_ GUEST_TLBS(VMMGetCpu(pVM));2066 PGM_INVL_VCPU_TLBS(VMMGetCpu(pVM)); 2067 2067 STAM_PROFILE_STOP(&pPool->StatClearAll, c); 2068 2068 return VINF_SUCCESS;
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