Index: trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp	(revision 20515)
+++ trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp	(revision 20516)
@@ -945,4 +945,77 @@
     }
 
+    /* When external interrupts are pending, we should exit the VM when IF is set. */
+    /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
+    rc = SVMR0CheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);
+    if (RT_FAILURE(rc))
+    {
+        STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
+        goto end;
+    }
+
+    /* TPR caching using CR8 is only available in 64 bits mode or with 32 bits guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is supported. */
+    /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! */
+    if (pVM->hwaccm.s.fHasIoApic)
+    {
+        bool fPending;
+
+        /* TPR caching in CR8 */
+        int rc = PDMApicGetTPR(pVCpu, &u8LastVTPR, &fPending);
+        AssertRC(rc);
+        pVMCB->ctrl.IntCtrl.n.u8VTPR = u8LastVTPR;
+
+        if (fPending)
+        {
+            /* A TPR change could activate a pending interrupt, so catch cr8 writes. */
+            pVMCB->ctrl.u16InterceptWrCRx |= RT_BIT(8);
+        }
+        else
+            /* No interrupts are pending, so we don't need to be explicitely notified.
+             * There are enough world switches for detecting pending interrupts.
+             */
+            pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
+
+        fSyncTPR = !fPending;
+    }
+
+    /* All done! Let's start VM execution. */
+    STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, x);
+
+    /* Enable nested paging if necessary (disabled each time after #VMEXIT). */
+    pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
+
+#ifdef LOG_ENABLED
+    pCpu = HWACCMR0GetCurrentCpu();
+    if (    pVCpu->hwaccm.s.idLastCpu   != pCpu->idCpu
+        ||  pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
+    {
+        if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
+            Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
+        else
+            Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
+    }
+    if (pCpu->fFlushTLB)
+        Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
+#endif
+
+    /*
+     * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
+     *       (until the actual world switch)
+     */
+#ifdef VBOX_STRICT
+    idCpuCheck = RTMpCpuId();
+#endif
+#ifdef LOG_ENABLED
+    VMMR0LogFlushDisable(pVCpu);
+#endif
+
+    /* Load the guest state; *must* be here as it sets up the shadow cr0 for lazy fpu syncing! */
+    rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);
+    if (rc != VINF_SUCCESS)
+    {
+        STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
+        goto end;
+    }
+
 #ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
     /*
@@ -950,6 +1023,5 @@
      *
      * Interrupts are disabled before the call to make sure we don't miss any interrupt
-     * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
-     * further down, but SVMR0CheckPendingInterrupt makes that hard.)
+     * that would flag preemption (IPI, timer tick, ++). 
      *
      * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
@@ -964,80 +1036,5 @@
     }
     VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
-#endif
-
-    /* When external interrupts are pending, we should exit the VM when IF is set. */
-    /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
-    rc = SVMR0CheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);
-    if (RT_FAILURE(rc))
-    {
-        STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
-        goto end;
-    }
-
-    /* TPR caching using CR8 is only available in 64 bits mode or with 32 bits guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is supported. */
-    /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! */
-    if (pVM->hwaccm.s.fHasIoApic)
-    {
-        bool fPending;
-
-        /* TPR caching in CR8 */
-        int rc = PDMApicGetTPR(pVCpu, &u8LastVTPR, &fPending);
-        AssertRC(rc);
-        pVMCB->ctrl.IntCtrl.n.u8VTPR = u8LastVTPR;
-
-        if (fPending)
-        {
-            /* A TPR change could activate a pending interrupt, so catch cr8 writes. */
-            pVMCB->ctrl.u16InterceptWrCRx |= RT_BIT(8);
-        }
-        else
-            /* No interrupts are pending, so we don't need to be explicitely notified.
-             * There are enough world switches for detecting pending interrupts.
-             */
-            pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
-
-        fSyncTPR = !fPending;
-    }
-
-    /* All done! Let's start VM execution. */
-    STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, x);
-
-    /* Enable nested paging if necessary (disabled each time after #VMEXIT). */
-    pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
-
-#ifdef LOG_ENABLED
-    pCpu = HWACCMR0GetCurrentCpu();
-    if (    pVCpu->hwaccm.s.idLastCpu   != pCpu->idCpu
-        ||  pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
-    {
-        if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
-            Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
-        else
-            Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
-    }
-    if (pCpu->fFlushTLB)
-        Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
-#endif
-
-    /*
-     * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
-     *       (until the actual world switch)
-     */
-#ifdef VBOX_STRICT
-    idCpuCheck = RTMpCpuId();
-#endif
-#ifdef LOG_ENABLED
-    VMMR0LogFlushDisable(pVCpu);
-#endif
-
-    /* Load the guest state; *must* be here as it sets up the shadow cr0 for lazy fpu syncing! */
-    rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);
-    if (rc != VINF_SUCCESS)
-    {
-        STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
-        goto end;
-    }
-
-#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
+#else
     /* Disable interrupts to make sure a poke will interrupt execution.
      * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
Index: trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp	(revision 20515)
+++ trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp	(revision 20516)
@@ -2180,25 +2180,4 @@
     }
 
-#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
-    /*
-     * Exit to ring-3 preemption/work is pending.
-     *
-     * Interrupts are disabled before the call to make sure we don't miss any interrupt
-     * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
-     * further down, but VMXR0CheckPendingInterrupt makes that hard.)
-     *
-     * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
-     *       shootdowns rely on this.
-     */
-    uOldEFlags = ASMIntDisableFlags();
-    if (RTThreadPreemptIsPending(NIL_RTTHREAD))
-    {
-        STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
-        rc = VINF_EM_RAW_INTERRUPT;
-        goto end;
-    }
-    VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
-#endif
-
     /* When external interrupts are pending, we should exit the VM when IF is set. */
     /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
@@ -2285,5 +2264,23 @@
         goto end;
 
-#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
+#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
+    /*
+     * Exit to ring-3 preemption/work is pending.
+     *
+     * Interrupts are disabled before the call to make sure we don't miss any interrupt
+     * that would flag preemption (IPI, timer tick, ++). 
+     *
+     * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
+     *       shootdowns rely on this.
+     */
+    uOldEFlags = ASMIntDisableFlags();
+    if (RTThreadPreemptIsPending(NIL_RTTHREAD))
+    {
+        STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
+        rc = VINF_EM_RAW_INTERRUPT;
+        goto end;
+    }
+    VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
+#else
     /* Disable interrupts to make sure a poke will interrupt execution.
      * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
