Changeset 20530 in vbox for trunk/src/VBox
- Timestamp:
- Jun 13, 2009 8:53:44 PM (16 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 13 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/EMInternal.h ¶
r20426 r20530 347 347 } u; 348 348 349 /** For saving stack space, the disassembler state is allocated here instead of 350 * on the stack. 351 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */ 352 union 353 { 354 /** The disassembler scratch space. */ 355 DISCPUSTATE DisState; 356 /** Padding. */ 357 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE]; 358 }; 359 349 360 /** @name Execution profiling. 350 361 * @{ */ -
trunk/src/VBox/VMM/HWACCMInternal.h ¶
r20374 r20530 589 589 unsigned cPages; 590 590 } TlbShootdown; 591 592 /** For saving stack space, the disassembler state is allocated here instead of 593 * on the stack. 594 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */ 595 union 596 { 597 /** The disassembler scratch space. */ 598 DISCPUSTATE DisState; 599 /** Padding. */ 600 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE]; 601 }; 591 602 592 603 RTUINT padding2[1]; -
trunk/src/VBox/VMM/IOMInternal.h ¶
r20374 r20530 402 402 403 403 404 /** 405 * IOM per virtual CPU instance data. 406 */ 407 typedef struct IOMCPU 408 { 409 /** For saving stack space, the disassembler state is allocated here instead of 410 * on the stack. 411 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */ 412 union 413 { 414 /** The disassembler scratch space. */ 415 DISCPUSTATE DisState; 416 /** Padding. */ 417 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE]; 418 }; 419 uint8_t Dummy[16]; 420 } IOMCPU; 421 /** Pointer to IOM per virtual CPU instance data. */ 422 typedef IOMCPU *PIOMCPU; 423 424 404 425 RT_C_DECLS_BEGIN 405 426 -
trunk/src/VBox/VMM/PGMInternal.h ¶
r20374 r20530 2702 2702 /** @} */ 2703 2703 2704 /** For saving stack space, the disassembler state is allocated here instead of 2705 * on the stack. 2706 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */ 2707 union 2708 { 2709 /** The disassembler scratch space. */ 2710 DISCPUSTATE DisState; 2711 /** Padding. */ 2712 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE]; 2713 }; 2714 2704 2715 /** @name Release Statistics 2705 2716 * @{ */ -
trunk/src/VBox/VMM/VMMAll/EMAll.cpp ¶
r20461 r20530 77 77 * Internal Functions * 78 78 *******************************************************************************/ 79 DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);79 DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize); 80 80 81 81 … … 114 114 * @param pDest HC destination pointer 115 115 * @param cb Number of bytes to read 116 * @param dwUserdata Callback specific user data (pD ISState)116 * @param dwUserdata Callback specific user data (pDis) 117 117 * 118 118 */ 119 119 DECLCALLBACK(int) EMReadBytes(RTUINTPTR pSrc, uint8_t *pDest, unsigned cb, void *pvUserdata) 120 120 { 121 DISCPUSTATE *pDISState = (DISCPUSTATE *)pvUserdata;122 PEMDISSTATE pState = (PEMDISSTATE)pDISState->apvUserData[0];123 PVM pVM 124 PVMCPU pVCpu 121 PDISCPUSTATE pDis = (PDISCPUSTATE)pvUserdata; 122 PEMDISSTATE pState = (PEMDISSTATE)pDis->apvUserData[0]; 123 PVM pVM = pState->pVM; 124 PVMCPU pVCpu = pState->pVCpu; 125 125 126 126 # ifdef IN_RING0 … … 147 147 } 148 148 149 DECLINLINE(int) emDisCoreOne(PVM pVM, PVMCPU pVCpu, DISCPUSTATE *pDISState, RTGCUINTPTR InstrGC, uint32_t *pOpsize)149 DECLINLINE(int) emDisCoreOne(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, RTGCUINTPTR InstrGC, uint32_t *pOpsize) 150 150 { 151 151 EMDISSTATE State; … … 154 154 State.pVCpu = pVCpu; 155 155 156 return DISCoreOneEx(InstrGC, pD ISState->mode, EMReadBytes, &State, pDISState, pOpsize);156 return DISCoreOneEx(InstrGC, pDis->mode, EMReadBytes, &State, pDis, pOpsize); 157 157 } 158 158 159 159 #else /* IN_RC */ 160 160 161 DECLINLINE(int) emDisCoreOne(PVM pVM, PVMCPU pVCpu, DISCPUSTATE *pDISState, RTGCUINTPTR InstrGC, uint32_t *pOpsize)161 DECLINLINE(int) emDisCoreOne(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, RTGCUINTPTR InstrGC, uint32_t *pOpsize) 162 162 { 163 163 NOREF(pVCpu); 164 164 NOREF(pVM); 165 return DISCoreOne(pD ISState, InstrGC, pOpsize);165 return DISCoreOne(pDis, InstrGC, pOpsize); 166 166 } 167 167 … … 179 179 * @param pVCpu The VMCPU handle. 180 180 * @param pCtxCore The context core (used for both the mode and instruction). 181 * @param pD ISStateWhere to return the parsed instruction info.181 * @param pDis Where to return the parsed instruction info. 182 182 * @param pcbInstr Where to return the instruction size. (optional) 183 183 */ 184 VMMDECL(int) EMInterpretDisasOne(PVM pVM, PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pD ISState, unsigned *pcbInstr)184 VMMDECL(int) EMInterpretDisasOne(PVM pVM, PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pDis, unsigned *pcbInstr) 185 185 { 186 186 RTGCPTR GCPtrInstr; … … 192 192 return rc; 193 193 } 194 return EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pD ISState, pcbInstr);194 return EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pDis, pcbInstr); 195 195 } 196 196 … … 208 208 * @param GCPtrInstr The flat address of the instruction. 209 209 * @param pCtxCore The context core (used to determine the cpu mode). 210 * @param pD ISStateWhere to return the parsed instruction info.210 * @param pDis Where to return the parsed instruction info. 211 211 * @param pcbInstr Where to return the instruction size. (optional) 212 212 */ 213 VMMDECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pD ISState, unsigned *pcbInstr)213 VMMDECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pDis, unsigned *pcbInstr) 214 214 { 215 215 #ifndef IN_RC … … 226 226 EMReadBytes, &State, 227 227 #endif 228 pD ISState, pcbInstr);228 pDis, pcbInstr); 229 229 if (RT_SUCCESS(rc)) 230 230 return VINF_SUCCESS; … … 261 261 if (RT_SUCCESS(rc)) 262 262 { 263 uint32_t cbOp;264 DISCPUSTATE Cpu;265 Cpu.mode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);266 rc = emDisCoreOne(pVM, pVCpu, &Cpu, (RTGCUINTPTR)pbCode, &cbOp);263 uint32_t cbOp; 264 PDISCPUSTATE pDis = &pVCpu->em.s.DisState; 265 pDis->mode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid); 266 rc = emDisCoreOne(pVM, pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp); 267 267 if (RT_SUCCESS(rc)) 268 268 { 269 Assert(cbOp == Cpu.opsize);270 rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, pRegFrame, pvFault, pcbSize);269 Assert(cbOp == pDis->opsize); 270 rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); 271 271 if (RT_SUCCESS(rc)) 272 272 pRegFrame->rip += cbOp; /* Move on to the next instruction. */ … … 293 293 * @param pVM The VM handle. 294 294 * @param pVCpu The VMCPU handle. 295 * @param pDISState The disassembler cpu state for the instruction to be interpreted. 295 * @param pDis The disassembler cpu state for the instruction to be 296 * interpreted. 296 297 * @param pRegFrame The register frame. EIP is *NOT* changed! 297 298 * @param pvFault The fault address (CR2). … … 305 306 * Make sure this can't happen!! (will add some assertions/checks later) 306 307 */ 307 VMMDECL(int) EMInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)308 VMMDECL(int) EMInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 308 309 { 309 310 STAM_PROFILE_START(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a); 310 int rc = emInterpretInstructionCPU(pVM, pVCpu, pD ISState, pRegFrame, pvFault, pcbSize);311 int rc = emInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); 311 312 STAM_PROFILE_STOP(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a); 312 313 if (RT_SUCCESS(rc)) … … 325 326 * @param pVCpu The VMCPU handle. 326 327 * @param pCtxCore The context core. This will be updated on successful return. 327 * @param pD ISStateThe instruction to interpret.328 * @param pDis The instruction to interpret. 328 329 * @param cbOp The size of the instruction. 329 330 * @remark This may raise exceptions. 330 331 */ 331 VMMDECL(int) EMInterpretPortIO(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pD ISState, uint32_t cbOp)332 VMMDECL(int) EMInterpretPortIO(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pDis, uint32_t cbOp) 332 333 { 333 334 /* … … 335 336 */ 336 337 #ifdef IN_RC 337 int rc = IOMGCIOPortHandler(pVM, pCtxCore, pD ISState);338 int rc = IOMGCIOPortHandler(pVM, pCtxCore, pDis); 338 339 if (IOM_SUCCESS(rc)) 339 340 pCtxCore->rip += cbOp; … … 381 382 382 383 /** Convert sel:addr to a flat GC address. */ 383 DECLINLINE(RTGCPTR) emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pD ISState, POP_PARAMETER pParam, RTGCPTR pvAddr)384 { 385 DIS_SELREG enmPrefixSeg = DISDetectSegReg(pD ISState, pParam);384 DECLINLINE(RTGCPTR) emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, POP_PARAMETER pParam, RTGCPTR pvAddr) 385 { 386 DIS_SELREG enmPrefixSeg = DISDetectSegReg(pDis, pParam); 386 387 return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr); 387 388 } … … 395 396 * of limited space. 396 397 */ 397 static const char *emGetMnemonic(PDISCPUSTATE pD ISState)398 { 399 switch (pD ISState->pCurInstr->opcode)398 static const char *emGetMnemonic(PDISCPUSTATE pDis) 399 { 400 switch (pDis->pCurInstr->opcode) 400 401 { 401 402 case OP_XCHG: return "Xchg"; … … 437 438 case OP_LMSW: return "Lmsw"; 438 439 case OP_SMSW: return "Smsw"; 439 case OP_CMPXCHG: return pD ISState->prefix & PREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg";440 case OP_CMPXCHG8B: return pD ISState->prefix & PREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b";440 case OP_CMPXCHG: return pDis->prefix & PREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg"; 441 case OP_CMPXCHG8B: return pDis->prefix & PREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b"; 441 442 442 443 default: 443 Log(("Unknown opcode %d\n", pD ISState->pCurInstr->opcode));444 Log(("Unknown opcode %d\n", pDis->pCurInstr->opcode)); 444 445 return "???"; 445 446 } … … 451 452 * XCHG instruction emulation. 452 453 */ 453 static int emInterpretXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)454 static int emInterpretXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 454 455 { 455 456 OP_PARAMVAL param1, param2; 456 457 457 458 /* Source to make DISQueryParamVal read the register value - ugly hack */ 458 int rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param1, ¶m1, PARAM_SOURCE);459 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, ¶m1, PARAM_SOURCE); 459 460 if(RT_FAILURE(rc)) 460 461 return VERR_EM_INTERPRETER; 461 462 462 rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param2, ¶m2, PARAM_SOURCE);463 rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, ¶m2, PARAM_SOURCE); 463 464 if(RT_FAILURE(rc)) 464 465 return VERR_EM_INTERPRETER; … … 473 474 uint64_t valpar1, valpar2; 474 475 475 AssertReturn(pD ISState->param1.size == pDISState->param2.size, VERR_EM_INTERPRETER);476 AssertReturn(pDis->param1.size == pDis->param2.size, VERR_EM_INTERPRETER); 476 477 switch(param1.type) 477 478 { … … 482 483 case PARMTYPE_ADDRESS: 483 484 pParam1 = (RTGCPTR)param1.val.val64; 484 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pD ISState, &pDISState->param1, pParam1);485 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1); 485 486 EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER); 486 487 rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size); … … 501 502 case PARMTYPE_ADDRESS: 502 503 pParam2 = (RTGCPTR)param2.val.val64; 503 pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pD ISState, &pDISState->param2, pParam2);504 pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param2, pParam2); 504 505 EM_ASSERT_FAULT_RETURN(pParam2 == pvFault, VERR_EM_INTERPRETER); 505 506 rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar2, pParam2, param2.size); … … 526 527 { 527 528 case 1: //special case for AH etc 528 rc = DISWriteReg8(pRegFrame, pD ISState->param1.base.reg_gen, (uint8_t )valpar2); break;529 case 2: rc = DISWriteReg16(pRegFrame, pD ISState->param1.base.reg_gen, (uint16_t)valpar2); break;530 case 4: rc = DISWriteReg32(pRegFrame, pD ISState->param1.base.reg_gen, (uint32_t)valpar2); break;531 case 8: rc = DISWriteReg64(pRegFrame, pD ISState->param1.base.reg_gen, valpar2); break;529 rc = DISWriteReg8(pRegFrame, pDis->param1.base.reg_gen, (uint8_t )valpar2); break; 530 case 2: rc = DISWriteReg16(pRegFrame, pDis->param1.base.reg_gen, (uint16_t)valpar2); break; 531 case 4: rc = DISWriteReg32(pRegFrame, pDis->param1.base.reg_gen, (uint32_t)valpar2); break; 532 case 8: rc = DISWriteReg64(pRegFrame, pDis->param1.base.reg_gen, valpar2); break; 532 533 default: AssertFailedReturn(VERR_EM_INTERPRETER); 533 534 } … … 552 553 { 553 554 case 1: //special case for AH etc 554 rc = DISWriteReg8(pRegFrame, pD ISState->param2.base.reg_gen, (uint8_t )valpar1); break;555 case 2: rc = DISWriteReg16(pRegFrame, pD ISState->param2.base.reg_gen, (uint16_t)valpar1); break;556 case 4: rc = DISWriteReg32(pRegFrame, pD ISState->param2.base.reg_gen, (uint32_t)valpar1); break;557 case 8: rc = DISWriteReg64(pRegFrame, pD ISState->param2.base.reg_gen, valpar1); break;555 rc = DISWriteReg8(pRegFrame, pDis->param2.base.reg_gen, (uint8_t )valpar1); break; 556 case 2: rc = DISWriteReg16(pRegFrame, pDis->param2.base.reg_gen, (uint16_t)valpar1); break; 557 case 4: rc = DISWriteReg32(pRegFrame, pDis->param2.base.reg_gen, (uint32_t)valpar1); break; 558 case 8: rc = DISWriteReg64(pRegFrame, pDis->param2.base.reg_gen, valpar1); break; 558 559 default: AssertFailedReturn(VERR_EM_INTERPRETER); 559 560 } … … 584 585 * INC and DEC emulation. 585 586 */ 586 static int emInterpretIncDec(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,587 static int emInterpretIncDec(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize, 587 588 PFNEMULATEPARAM2 pfnEmulate) 588 589 { 589 590 OP_PARAMVAL param1; 590 591 591 int rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param1, ¶m1, PARAM_DEST);592 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, ¶m1, PARAM_DEST); 592 593 if(RT_FAILURE(rc)) 593 594 return VERR_EM_INTERPRETER; … … 605 606 { 606 607 pParam1 = (RTGCPTR)param1.val.val64; 607 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pD ISState, &pDISState->param1, pParam1);608 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1); 608 609 #ifdef IN_RC 609 610 /* Safety check (in theory it could cross a page boundary and fault there though) */ … … 653 654 * POP Emulation. 654 655 */ 655 static int emInterpretPop(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)656 { 657 Assert(pD ISState->mode != CPUMODE_64BIT); /** @todo check */656 static int emInterpretPop(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 657 { 658 Assert(pDis->mode != CPUMODE_64BIT); /** @todo check */ 658 659 OP_PARAMVAL param1; 659 int rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param1, ¶m1, PARAM_DEST);660 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, ¶m1, PARAM_DEST); 660 661 if(RT_FAILURE(rc)) 661 662 return VERR_EM_INTERPRETER; … … 693 694 /* pop [esp+xx] uses esp after the actual pop! */ 694 695 AssertCompile(USE_REG_ESP == USE_REG_SP); 695 if ( (pD ISState->param1.flags & USE_BASE)696 && (pD ISState->param1.flags & (USE_REG_GEN16|USE_REG_GEN32))697 && pD ISState->param1.base.reg_gen == USE_REG_ESP696 if ( (pDis->param1.flags & USE_BASE) 697 && (pDis->param1.flags & (USE_REG_GEN16|USE_REG_GEN32)) 698 && pDis->param1.base.reg_gen == USE_REG_ESP 698 699 ) 699 700 pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size); 700 701 701 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pD ISState, &pDISState->param1, pParam1);702 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1); 702 703 EM_ASSERT_FAULT_RETURN(pParam1 == pvFault || (RTGCPTR)pRegFrame->esp == pvFault, VERR_EM_INTERPRETER); 703 704 rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size); … … 733 734 * XOR/OR/AND Emulation. 734 735 */ 735 static int emInterpretOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,736 static int emInterpretOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize, 736 737 PFNEMULATEPARAM3 pfnEmulate) 737 738 { 738 739 OP_PARAMVAL param1, param2; 739 740 740 int rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param1, ¶m1, PARAM_DEST);741 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, ¶m1, PARAM_DEST); 741 742 if(RT_FAILURE(rc)) 742 743 return VERR_EM_INTERPRETER; 743 744 744 rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param2, ¶m2, PARAM_SOURCE);745 rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, ¶m2, PARAM_SOURCE); 745 746 if(RT_FAILURE(rc)) 746 747 return VERR_EM_INTERPRETER; … … 755 756 uint64_t valpar1, valpar2; 756 757 757 if (pD ISState->param1.size != pDISState->param2.size)758 { 759 if (pD ISState->param1.size < pDISState->param2.size)758 if (pDis->param1.size != pDis->param2.size) 759 { 760 if (pDis->param1.size < pDis->param2.size) 760 761 { 761 AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pD ISState), (RTGCPTR)pRegFrame->rip, pDISState->param1.size, pDISState->param2.size)); /* should never happen! */762 AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->param1.size, pDis->param2.size)); /* should never happen! */ 762 763 return VERR_EM_INTERPRETER; 763 764 } 764 765 /* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */ 765 pD ISState->param2.size = pDISState->param1.size;766 pDis->param2.size = pDis->param1.size; 766 767 param2.size = param1.size; 767 768 } … … 771 772 { 772 773 pParam1 = (RTGCPTR)param1.val.val64; 773 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pD ISState, &pDISState->param1, pParam1);774 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1); 774 775 EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER); 775 776 rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size); … … 798 799 } 799 800 800 LogFlow(("emInterpretOrXorAnd %s %RGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pD ISState), pParam1, valpar1, valpar2, param2.size, param1.size));801 LogFlow(("emInterpretOrXorAnd %s %RGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pDis), pParam1, valpar1, valpar2, param2.size, param1.size)); 801 802 802 803 /* Data read, emulate instruction. */ 803 804 uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size); 804 805 805 LogFlow(("emInterpretOrXorAnd %s result %RX64\n", emGetMnemonic(pD ISState), valpar1));806 LogFlow(("emInterpretOrXorAnd %s result %RX64\n", emGetMnemonic(pDis), valpar1)); 806 807 807 808 /* Update guest's eflags and finish. */ … … 828 829 * LOCK XOR/OR/AND Emulation. 829 830 */ 830 static int emInterpretLockOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,831 static int emInterpretLockOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, 831 832 uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate) 832 833 { … … 835 836 836 837 #if HC_ARCH_BITS == 32 837 Assert(pD ISState->param1.size <= 4);838 #endif 839 840 int rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param1, ¶m1, PARAM_DEST);838 Assert(pDis->param1.size <= 4); 839 #endif 840 841 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, ¶m1, PARAM_DEST); 841 842 if(RT_FAILURE(rc)) 842 843 return VERR_EM_INTERPRETER; 843 844 844 rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param2, ¶m2, PARAM_SOURCE);845 rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, ¶m2, PARAM_SOURCE); 845 846 if(RT_FAILURE(rc)) 846 847 return VERR_EM_INTERPRETER; 847 848 848 if (pD ISState->param1.size != pDISState->param2.size)849 { 850 AssertMsgReturn(pD ISState->param1.size >= pDISState->param2.size, /* should never happen! */851 ("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pD ISState), (RTGCPTR)pRegFrame->rip, pDISState->param1.size, pDISState->param2.size),849 if (pDis->param1.size != pDis->param2.size) 850 { 851 AssertMsgReturn(pDis->param1.size >= pDis->param2.size, /* should never happen! */ 852 ("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->param1.size, pDis->param2.size), 852 853 VERR_EM_INTERPRETER); 853 854 854 855 /* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */ 855 pD ISState->param2.size = pDISState->param1.size;856 pDis->param2.size = pDis->param1.size; 856 857 param2.size = param1.size; 857 858 } … … 872 873 873 874 RTGCPTR GCPtrPar1 = param1.val.val64; 874 GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pD ISState, &pDISState->param1, GCPtrPar1);875 GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, GCPtrPar1); 875 876 #ifdef IN_RC 876 877 pvParam1 = (void *)GCPtrPar1; … … 882 883 883 884 /* Try emulate it with a one-shot #PF handler in place. (RC) */ 884 Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pD ISState), GCPtrPar1, pDISState->param2.size*8, ValPar2));885 Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pDis), GCPtrPar1, pDis->param2.size*8, ValPar2)); 885 886 886 887 RTGCUINTREG32 eflags = 0; … … 888 889 MMGCRamRegisterTrapHandler(pVM); 889 890 #endif 890 rc = pfnEmulate(pvParam1, ValPar2, pD ISState->param2.size, &eflags);891 rc = pfnEmulate(pvParam1, ValPar2, pDis->param2.size, &eflags); 891 892 #ifdef IN_RC 892 893 MMGCRamDeregisterTrapHandler(pVM); … … 896 897 if (RT_FAILURE(rc)) 897 898 { 898 Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pD ISState), GCPtrPar1, pDISState->param2.size*8, ValPar2));899 Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pDis), GCPtrPar1, pDis->param2.size*8, ValPar2)); 899 900 return VERR_EM_INTERPRETER; 900 901 } … … 912 913 * ADD, ADC & SUB Emulation. 913 914 */ 914 static int emInterpretAddSub(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,915 static int emInterpretAddSub(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize, 915 916 PFNEMULATEPARAM3 pfnEmulate) 916 917 { 917 918 OP_PARAMVAL param1, param2; 918 int rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param1, ¶m1, PARAM_DEST);919 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, ¶m1, PARAM_DEST); 919 920 if(RT_FAILURE(rc)) 920 921 return VERR_EM_INTERPRETER; 921 922 922 rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param2, ¶m2, PARAM_SOURCE);923 rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, ¶m2, PARAM_SOURCE); 923 924 if(RT_FAILURE(rc)) 924 925 return VERR_EM_INTERPRETER; … … 933 934 uint64_t valpar1, valpar2; 934 935 935 if (pD ISState->param1.size != pDISState->param2.size)936 { 937 if (pD ISState->param1.size < pDISState->param2.size)936 if (pDis->param1.size != pDis->param2.size) 937 { 938 if (pDis->param1.size < pDis->param2.size) 938 939 { 939 AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pD ISState), (RTGCPTR)pRegFrame->rip, pDISState->param1.size, pDISState->param2.size)); /* should never happen! */940 AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->param1.size, pDis->param2.size)); /* should never happen! */ 940 941 return VERR_EM_INTERPRETER; 941 942 } 942 943 /* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */ 943 pD ISState->param2.size = pDISState->param1.size;944 pDis->param2.size = pDis->param1.size; 944 945 param2.size = param1.size; 945 946 } … … 949 950 { 950 951 pParam1 = (RTGCPTR)param1.val.val64; 951 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pD ISState, &pDISState->param1, pParam1);952 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1); 952 953 EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER); 953 954 rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size); … … 1004 1005 * ADC Emulation. 1005 1006 */ 1006 static int emInterpretAdc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)1007 static int emInterpretAdc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 1007 1008 { 1008 1009 if (pRegFrame->eflags.Bits.u1CF) 1009 return emInterpretAddSub(pVM, pVCpu, pD ISState, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);1010 return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet); 1010 1011 else 1011 return emInterpretAddSub(pVM, pVCpu, pD ISState, pRegFrame, pvFault, pcbSize, EMEmulateAdd);1012 return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdd); 1012 1013 } 1013 1014 … … 1016 1017 * BTR/C/S Emulation. 1017 1018 */ 1018 static int emInterpretBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,1019 static int emInterpretBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize, 1019 1020 PFNEMULATEPARAM2UINT32 pfnEmulate) 1020 1021 { 1021 1022 OP_PARAMVAL param1, param2; 1022 int rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param1, ¶m1, PARAM_DEST);1023 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, ¶m1, PARAM_DEST); 1023 1024 if(RT_FAILURE(rc)) 1024 1025 return VERR_EM_INTERPRETER; 1025 1026 1026 rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param2, ¶m2, PARAM_SOURCE);1027 rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, ¶m2, PARAM_SOURCE); 1027 1028 if(RT_FAILURE(rc)) 1028 1029 return VERR_EM_INTERPRETER; … … 1043 1044 1044 1045 pParam1 = (RTGCPTR)param1.val.val64; 1045 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pD ISState, &pDISState->param1, pParam1);1046 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1); 1046 1047 1047 1048 /* Register or immediate data */ … … 1057 1058 } 1058 1059 1059 Log2(("emInterpret%s: pvFault=%RGv pParam1=%RGv val2=%x\n", emGetMnemonic(pD ISState), pvFault, pParam1, valpar2));1060 Log2(("emInterpret%s: pvFault=%RGv pParam1=%RGv val2=%x\n", emGetMnemonic(pDis), pvFault, pParam1, valpar2)); 1060 1061 pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8); 1061 1062 EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, VERR_EM_INTERPRETER); … … 1096 1097 * LOCK BTR/C/S Emulation. 1097 1098 */ 1098 static int emInterpretLockBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,1099 static int emInterpretLockBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, 1099 1100 uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate) 1100 1101 { … … 1102 1103 1103 1104 OP_PARAMVAL param1, param2; 1104 int rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param1, ¶m1, PARAM_DEST);1105 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, ¶m1, PARAM_DEST); 1105 1106 if(RT_FAILURE(rc)) 1106 1107 return VERR_EM_INTERPRETER; 1107 1108 1108 rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param2, ¶m2, PARAM_SOURCE);1109 rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, ¶m2, PARAM_SOURCE); 1109 1110 if(RT_FAILURE(rc)) 1110 1111 return VERR_EM_INTERPRETER; … … 1123 1124 ValPar2 &= 7; 1124 1125 1125 GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pD ISState, &pDISState->param1, GCPtrPar1);1126 GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, GCPtrPar1); 1126 1127 #ifdef IN_RC 1127 1128 Assert(TRPMHasTrap(pVCpu)); … … 1137 1138 #endif 1138 1139 1139 Log2(("emInterpretLockBitTest %s: pvFault=%RGv GCPtrPar1=%RGv imm=%RX64\n", emGetMnemonic(pD ISState), pvFault, GCPtrPar1, ValPar2));1140 Log2(("emInterpretLockBitTest %s: pvFault=%RGv GCPtrPar1=%RGv imm=%RX64\n", emGetMnemonic(pDis), pvFault, GCPtrPar1, ValPar2)); 1140 1141 1141 1142 /* Try emulate it with a one-shot #PF handler in place. (RC) */ … … 1153 1154 { 1154 1155 Log(("emInterpretLockBitTest %s: %RGv imm%d=%RX64 -> emulation failed due to page fault!\n", 1155 emGetMnemonic(pD ISState), GCPtrPar1, pDISState->param2.size*8, ValPar2));1156 return VERR_EM_INTERPRETER; 1157 } 1158 1159 Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%RX64 CF=%d\n", emGetMnemonic(pD ISState), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));1156 emGetMnemonic(pDis), GCPtrPar1, pDis->param2.size*8, ValPar2)); 1157 return VERR_EM_INTERPRETER; 1158 } 1159 1160 Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%RX64 CF=%d\n", emGetMnemonic(pDis), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF))); 1160 1161 1161 1162 /* Update guest's eflags and finish. */ … … 1171 1172 * MOV emulation. 1172 1173 */ 1173 static int emInterpretMov(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)1174 static int emInterpretMov(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 1174 1175 { 1175 1176 OP_PARAMVAL param1, param2; 1176 int rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param1, ¶m1, PARAM_DEST);1177 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, ¶m1, PARAM_DEST); 1177 1178 if(RT_FAILURE(rc)) 1178 1179 return VERR_EM_INTERPRETER; 1179 1180 1180 rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param2, ¶m2, PARAM_SOURCE);1181 rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, ¶m2, PARAM_SOURCE); 1181 1182 if(RT_FAILURE(rc)) 1182 1183 return VERR_EM_INTERPRETER; … … 1204 1205 case PARMTYPE_ADDRESS: 1205 1206 pDest = (RTGCPTR)param1.val.val64; 1206 pDest = emConvertToFlatAddr(pVM, pRegFrame, pD ISState, &pDISState->param1, pDest);1207 pDest = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pDest); 1207 1208 break; 1208 1209 … … 1223 1224 } 1224 1225 #ifdef LOG_ENABLED 1225 if (pD ISState->mode == CPUMODE_64BIT)1226 if (pDis->mode == CPUMODE_64BIT) 1226 1227 LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64)); 1227 1228 else … … 1252 1253 case PARMTYPE_ADDRESS: 1253 1254 pSrc = (RTGCPTR)param2.val.val64; 1254 pSrc = emConvertToFlatAddr(pVM, pRegFrame, pD ISState, &pDISState->param2, pSrc);1255 pSrc = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param2, pSrc); 1255 1256 break; 1256 1257 … … 1271 1272 switch(param1.size) 1272 1273 { 1273 case 1: rc = DISWriteReg8(pRegFrame, pD ISState->param1.base.reg_gen, (uint8_t) val64); break;1274 case 2: rc = DISWriteReg16(pRegFrame, pD ISState->param1.base.reg_gen, (uint16_t)val64); break;1275 case 4: rc = DISWriteReg32(pRegFrame, pD ISState->param1.base.reg_gen, (uint32_t)val64); break;1276 case 8: rc = DISWriteReg64(pRegFrame, pD ISState->param1.base.reg_gen, val64); break;1274 case 1: rc = DISWriteReg8(pRegFrame, pDis->param1.base.reg_gen, (uint8_t) val64); break; 1275 case 2: rc = DISWriteReg16(pRegFrame, pDis->param1.base.reg_gen, (uint16_t)val64); break; 1276 case 4: rc = DISWriteReg32(pRegFrame, pDis->param1.base.reg_gen, (uint32_t)val64); break; 1277 case 8: rc = DISWriteReg64(pRegFrame, pDis->param1.base.reg_gen, val64); break; 1277 1278 default: 1278 1279 return VERR_EM_INTERPRETER; … … 1286 1287 } 1287 1288 #ifdef LOG_ENABLED 1288 if (pD ISState->mode == CPUMODE_64BIT)1289 if (pDis->mode == CPUMODE_64BIT) 1289 1290 LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size)); 1290 1291 else … … 1304 1305 * [REP] STOSWD emulation 1305 1306 */ 1306 static int emInterpretStosWD(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)1307 static int emInterpretStosWD(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 1307 1308 { 1308 1309 int rc; … … 1313 1314 1314 1315 /* Don't support any but these three prefix bytes. */ 1315 if ((pD ISState->prefix & ~(PREFIX_ADDRSIZE|PREFIX_OPSIZE|PREFIX_REP|PREFIX_REX)))1316 return VERR_EM_INTERPRETER; 1317 1318 switch (pD ISState->addrmode)1316 if ((pDis->prefix & ~(PREFIX_ADDRSIZE|PREFIX_OPSIZE|PREFIX_REP|PREFIX_REX))) 1317 return VERR_EM_INTERPRETER; 1318 1319 switch (pDis->addrmode) 1319 1320 { 1320 1321 case CPUMODE_16BIT: … … 1336 1337 1337 1338 GCDest = SELMToFlat(pVM, DIS_SELREG_ES, pRegFrame, GCOffset); 1338 switch (pD ISState->opmode)1339 switch (pDis->opmode) 1339 1340 { 1340 1341 case CPUMODE_16BIT: … … 1354 1355 offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize; 1355 1356 1356 if (!(pD ISState->prefix & PREFIX_REP))1357 if (!(pDis->prefix & PREFIX_REP)) 1357 1358 { 1358 1359 LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize)); … … 1364 1365 1365 1366 /* Update (e/r)di. */ 1366 switch (pD ISState->addrmode)1367 switch (pDis->addrmode) 1367 1368 { 1368 1369 case CPUMODE_16BIT: … … 1429 1430 1430 1431 /* Update the registers. */ 1431 switch (pD ISState->addrmode)1432 switch (pDis->addrmode) 1432 1433 { 1433 1434 case CPUMODE_16BIT: … … 1459 1460 * [LOCK] CMPXCHG emulation. 1460 1461 */ 1461 static int emInterpretCmpXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)1462 static int emInterpretCmpXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 1462 1463 { 1463 1464 OP_PARAMVAL param1, param2; 1464 1465 1465 1466 #if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0) 1466 Assert(pD ISState->param1.size <= 4);1467 Assert(pDis->param1.size <= 4); 1467 1468 #endif 1468 1469 1469 1470 /* Source to make DISQueryParamVal read the register value - ugly hack */ 1470 int rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param1, ¶m1, PARAM_SOURCE);1471 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, ¶m1, PARAM_SOURCE); 1471 1472 if(RT_FAILURE(rc)) 1472 1473 return VERR_EM_INTERPRETER; 1473 1474 1474 rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param2, ¶m2, PARAM_SOURCE);1475 rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, ¶m2, PARAM_SOURCE); 1475 1476 if(RT_FAILURE(rc)) 1476 1477 return VERR_EM_INTERPRETER; … … 1492 1493 uint64_t eflags; 1493 1494 1494 AssertReturn(pD ISState->param1.size == pDISState->param2.size, VERR_EM_INTERPRETER);1495 AssertReturn(pDis->param1.size == pDis->param2.size, VERR_EM_INTERPRETER); 1495 1496 switch(param1.type) 1496 1497 { 1497 1498 case PARMTYPE_ADDRESS: 1498 1499 GCPtrPar1 = param1.val.val64; 1499 GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pD ISState, &pDISState->param1, GCPtrPar1);1500 GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, GCPtrPar1); 1500 1501 1501 1502 rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock); … … 1507 1508 } 1508 1509 1509 LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pD ISState), GCPtrPar1, pRegFrame->rax, valpar));1510 1511 if (pD ISState->prefix & PREFIX_LOCK)1512 eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pD ISState->param2.size);1510 LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar)); 1511 1512 if (pDis->prefix & PREFIX_LOCK) 1513 eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->param2.size); 1513 1514 else 1514 eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pD ISState->param2.size);1515 1516 LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pD ISState), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));1515 eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->param2.size); 1516 1517 LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF))); 1517 1518 1518 1519 /* Update guest's eflags and finish. */ … … 1529 1530 * [LOCK] CMPXCHG8B emulation. 1530 1531 */ 1531 static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)1532 { 1533 Assert(pD ISState->mode != CPUMODE_64BIT); /** @todo check */1532 static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 1533 { 1534 Assert(pDis->mode != CPUMODE_64BIT); /** @todo check */ 1534 1535 OP_PARAMVAL param1; 1535 1536 1536 1537 /* Source to make DISQueryParamVal read the register value - ugly hack */ 1537 int rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param1, ¶m1, PARAM_SOURCE);1538 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, ¶m1, PARAM_SOURCE); 1538 1539 if(RT_FAILURE(rc)) 1539 1540 return VERR_EM_INTERPRETER; … … 1544 1545 PGMPAGEMAPLOCK Lock; 1545 1546 1546 AssertReturn(pD ISState->param1.size == 8, VERR_EM_INTERPRETER);1547 AssertReturn(pDis->param1.size == 8, VERR_EM_INTERPRETER); 1547 1548 switch(param1.type) 1548 1549 { 1549 1550 case PARMTYPE_ADDRESS: 1550 1551 GCPtrPar1 = param1.val.val64; 1551 GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pD ISState, &pDISState->param1, GCPtrPar1);1552 GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, GCPtrPar1); 1552 1553 1553 1554 rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock); … … 1559 1560 } 1560 1561 1561 LogFlow(("%s %RGv=%08x eax=%08x\n", emGetMnemonic(pD ISState), pvParam1, pRegFrame->eax));1562 1563 if (pD ISState->prefix & PREFIX_LOCK)1562 LogFlow(("%s %RGv=%08x eax=%08x\n", emGetMnemonic(pDis), pvParam1, pRegFrame->eax)); 1563 1564 if (pDis->prefix & PREFIX_LOCK) 1564 1565 eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx); 1565 1566 else 1566 1567 eflags = EMEmulateCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx); 1567 1568 1568 LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pD ISState), pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));1569 LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pDis), pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF))); 1569 1570 1570 1571 /* Update guest's eflags and finish; note that *only* ZF is affected. */ … … 1582 1583 * [LOCK] CMPXCHG emulation. 1583 1584 */ 1584 static int emInterpretCmpXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)1585 { 1586 Assert(pD ISState->mode != CPUMODE_64BIT); /** @todo check */1585 static int emInterpretCmpXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 1586 { 1587 Assert(pDis->mode != CPUMODE_64BIT); /** @todo check */ 1587 1588 OP_PARAMVAL param1, param2; 1588 1589 1589 1590 /* Source to make DISQueryParamVal read the register value - ugly hack */ 1590 int rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param1, ¶m1, PARAM_SOURCE);1591 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, ¶m1, PARAM_SOURCE); 1591 1592 if(RT_FAILURE(rc)) 1592 1593 return VERR_EM_INTERPRETER; 1593 1594 1594 rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param2, ¶m2, PARAM_SOURCE);1595 rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, ¶m2, PARAM_SOURCE); 1595 1596 if(RT_FAILURE(rc)) 1596 1597 return VERR_EM_INTERPRETER; … … 1603 1604 uint32_t valpar, eflags; 1604 1605 1605 AssertReturn(pD ISState->param1.size == pDISState->param2.size, VERR_EM_INTERPRETER);1606 AssertReturn(pDis->param1.size == pDis->param2.size, VERR_EM_INTERPRETER); 1606 1607 switch(param1.type) 1607 1608 { 1608 1609 case PARMTYPE_ADDRESS: 1609 1610 pParam1 = (RTRCPTR)param1.val.val64; 1610 pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pD ISState, &pDISState->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);1611 pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, (RTGCPTR)(RTRCUINTPTR)pParam1); 1611 1612 EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER); 1612 1613 break; … … 1626 1627 } 1627 1628 1628 LogFlow(("%s %RRv eax=%08x %08x\n", emGetMnemonic(pD ISState), pParam1, pRegFrame->eax, valpar));1629 LogFlow(("%s %RRv eax=%08x %08x\n", emGetMnemonic(pDis), pParam1, pRegFrame->eax, valpar)); 1629 1630 1630 1631 MMGCRamRegisterTrapHandler(pVM); 1631 if (pD ISState->prefix & PREFIX_LOCK)1632 rc = EMGCEmulateLockCmpXchg(pParam1, &pRegFrame->eax, valpar, pD ISState->param2.size, &eflags);1632 if (pDis->prefix & PREFIX_LOCK) 1633 rc = EMGCEmulateLockCmpXchg(pParam1, &pRegFrame->eax, valpar, pDis->param2.size, &eflags); 1633 1634 else 1634 rc = EMGCEmulateCmpXchg(pParam1, &pRegFrame->eax, valpar, pD ISState->param2.size, &eflags);1635 rc = EMGCEmulateCmpXchg(pParam1, &pRegFrame->eax, valpar, pDis->param2.size, &eflags); 1635 1636 MMGCRamDeregisterTrapHandler(pVM); 1636 1637 1637 1638 if (RT_FAILURE(rc)) 1638 1639 { 1639 Log(("%s %RGv eax=%08x %08x -> emulation failed due to page fault!\n", emGetMnemonic(pD ISState), pParam1, pRegFrame->eax, valpar));1640 Log(("%s %RGv eax=%08x %08x -> emulation failed due to page fault!\n", emGetMnemonic(pDis), pParam1, pRegFrame->eax, valpar)); 1640 1641 return VERR_EM_INTERPRETER; 1641 1642 } 1642 1643 1643 LogFlow(("%s %RRv eax=%08x %08x ZF=%d\n", emGetMnemonic(pD ISState), pParam1, pRegFrame->eax, valpar, !!(eflags & X86_EFL_ZF)));1644 LogFlow(("%s %RRv eax=%08x %08x ZF=%d\n", emGetMnemonic(pDis), pParam1, pRegFrame->eax, valpar, !!(eflags & X86_EFL_ZF))); 1644 1645 1645 1646 /* Update guest's eflags and finish. */ … … 1658 1659 * [LOCK] CMPXCHG8B emulation. 1659 1660 */ 1660 static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)1661 { 1662 Assert(pD ISState->mode != CPUMODE_64BIT); /** @todo check */1661 static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 1662 { 1663 Assert(pDis->mode != CPUMODE_64BIT); /** @todo check */ 1663 1664 OP_PARAMVAL param1; 1664 1665 1665 1666 /* Source to make DISQueryParamVal read the register value - ugly hack */ 1666 int rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param1, ¶m1, PARAM_SOURCE);1667 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, ¶m1, PARAM_SOURCE); 1667 1668 if(RT_FAILURE(rc)) 1668 1669 return VERR_EM_INTERPRETER; … … 1675 1676 uint32_t eflags; 1676 1677 1677 AssertReturn(pD ISState->param1.size == 8, VERR_EM_INTERPRETER);1678 AssertReturn(pDis->param1.size == 8, VERR_EM_INTERPRETER); 1678 1679 switch(param1.type) 1679 1680 { 1680 1681 case PARMTYPE_ADDRESS: 1681 1682 pParam1 = (RTRCPTR)param1.val.val64; 1682 pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pD ISState, &pDISState->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);1683 pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, (RTGCPTR)(RTRCUINTPTR)pParam1); 1683 1684 EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER); 1684 1685 break; … … 1688 1689 } 1689 1690 1690 LogFlow(("%s %RRv=%08x eax=%08x\n", emGetMnemonic(pD ISState), pParam1, pRegFrame->eax));1691 LogFlow(("%s %RRv=%08x eax=%08x\n", emGetMnemonic(pDis), pParam1, pRegFrame->eax)); 1691 1692 1692 1693 MMGCRamRegisterTrapHandler(pVM); 1693 if (pD ISState->prefix & PREFIX_LOCK)1694 if (pDis->prefix & PREFIX_LOCK) 1694 1695 rc = EMGCEmulateLockCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags); 1695 1696 else … … 1699 1700 if (RT_FAILURE(rc)) 1700 1701 { 1701 Log(("%s %RGv=%08x eax=%08x -> emulation failed due to page fault!\n", emGetMnemonic(pD ISState), pParam1, pRegFrame->eax));1702 Log(("%s %RGv=%08x eax=%08x -> emulation failed due to page fault!\n", emGetMnemonic(pDis), pParam1, pRegFrame->eax)); 1702 1703 return VERR_EM_INTERPRETER; 1703 1704 } 1704 1705 1705 LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pD ISState), pParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));1706 LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pDis), pParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF))); 1706 1707 1707 1708 /* Update guest's eflags and finish; note that *only* ZF is affected. */ … … 1722 1723 * [LOCK] XADD emulation. 1723 1724 */ 1724 static int emInterpretXAdd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)1725 { 1726 Assert(pD ISState->mode != CPUMODE_64BIT); /** @todo check */1725 static int emInterpretXAdd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 1726 { 1727 Assert(pDis->mode != CPUMODE_64BIT); /** @todo check */ 1727 1728 OP_PARAMVAL param1; 1728 1729 uint32_t *pParamReg2; … … 1730 1731 1731 1732 /* Source to make DISQueryParamVal read the register value - ugly hack */ 1732 int rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param1, ¶m1, PARAM_SOURCE);1733 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, ¶m1, PARAM_SOURCE); 1733 1734 if(RT_FAILURE(rc)) 1734 1735 return VERR_EM_INTERPRETER; 1735 1736 1736 rc = DISQueryParamRegPtr(pRegFrame, pD ISState, &pDISState->param2, (void **)&pParamReg2, &cbSizeParamReg2);1737 rc = DISQueryParamRegPtr(pRegFrame, pDis, &pDis->param2, (void **)&pParamReg2, &cbSizeParamReg2); 1737 1738 Assert(cbSizeParamReg2 <= 4); 1738 1739 if(RT_FAILURE(rc)) … … 1746 1747 uint32_t eflags; 1747 1748 1748 AssertReturn(pD ISState->param1.size == pDISState->param2.size, VERR_EM_INTERPRETER);1749 AssertReturn(pDis->param1.size == pDis->param2.size, VERR_EM_INTERPRETER); 1749 1750 switch(param1.type) 1750 1751 { 1751 1752 case PARMTYPE_ADDRESS: 1752 1753 pParam1 = (RTRCPTR)param1.val.val64; 1753 pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pD ISState, &pDISState->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);1754 pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, (RTGCPTR)(RTRCUINTPTR)pParam1); 1754 1755 EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER); 1755 1756 break; … … 1762 1763 1763 1764 MMGCRamRegisterTrapHandler(pVM); 1764 if (pD ISState->prefix & PREFIX_LOCK)1765 if (pDis->prefix & PREFIX_LOCK) 1765 1766 rc = EMGCEmulateLockXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags); 1766 1767 else … … 1848 1849 * IRET Emulation. 1849 1850 */ 1850 static int emInterpretIret(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)1851 static int emInterpretIret(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 1851 1852 { 1852 1853 /* only allow direct calls to EMInterpretIret for now */ … … 1857 1858 * WBINVD Emulation. 1858 1859 */ 1859 static int emInterpretWbInvd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)1860 static int emInterpretWbInvd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 1860 1861 { 1861 1862 /* Nothing to do. */ … … 1898 1899 * INVLPG Emulation. 1899 1900 */ 1900 static int emInterpretInvlPg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)1901 static int emInterpretInvlPg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 1901 1902 { 1902 1903 OP_PARAMVAL param1; 1903 1904 RTGCPTR addr; 1904 1905 1905 int rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param1, ¶m1, PARAM_SOURCE);1906 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, ¶m1, PARAM_SOURCE); 1906 1907 if(RT_FAILURE(rc)) 1907 1908 return VERR_EM_INTERPRETER; … … 1966 1967 * CPUID Emulation. 1967 1968 */ 1968 static int emInterpretCpuId(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)1969 static int emInterpretCpuId(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 1969 1970 { 1970 1971 int rc = EMInterpretCpuId(pVM, pVCpu, pRegFrame); … … 2035 2036 * CLTS Emulation. 2036 2037 */ 2037 static int emInterpretClts(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)2038 static int emInterpretClts(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 2038 2039 { 2039 2040 return EMInterpretCLTS(pVM, pVCpu); … … 2236 2237 * LMSW Emulation. 2237 2238 */ 2238 static int emInterpretLmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)2239 static int emInterpretLmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 2239 2240 { 2240 2241 OP_PARAMVAL param1; 2241 2242 uint32_t val; 2242 2243 2243 int rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param1, ¶m1, PARAM_SOURCE);2244 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, ¶m1, PARAM_SOURCE); 2244 2245 if(RT_FAILURE(rc)) 2245 2246 return VERR_EM_INTERPRETER; … … 2266 2267 * SMSW Emulation. 2267 2268 */ 2268 static int emInterpretSmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)2269 static int emInterpretSmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 2269 2270 { 2270 2271 OP_PARAMVAL param1; 2271 2272 uint64_t cr0 = CPUMGetGuestCR0(pVCpu); 2272 2273 2273 int rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param1, ¶m1, PARAM_SOURCE);2274 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, ¶m1, PARAM_SOURCE); 2274 2275 if(RT_FAILURE(rc)) 2275 2276 return VERR_EM_INTERPRETER; … … 2280 2281 if(param1.size != sizeof(uint16_t)) 2281 2282 return VERR_EM_INTERPRETER; 2282 LogFlow(("emInterpretSmsw %d <- cr0 (%x)\n", pD ISState->param1.base.reg_gen, cr0));2283 rc = DISWriteReg16(pRegFrame, pD ISState->param1.base.reg_gen, cr0);2283 LogFlow(("emInterpretSmsw %d <- cr0 (%x)\n", pDis->param1.base.reg_gen, cr0)); 2284 rc = DISWriteReg16(pRegFrame, pDis->param1.base.reg_gen, cr0); 2284 2285 break; 2285 2286 … … 2293 2294 2294 2295 pParam1 = (RTGCPTR)param1.val.val64; 2295 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pD ISState, &pDISState->param1, pParam1);2296 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1); 2296 2297 LogFlow(("emInterpretSmsw %VGv <- cr0 (%x)\n", pParam1, cr0)); 2297 2298 … … 2317 2318 * MOV CRx 2318 2319 */ 2319 static int emInterpretMovCRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)2320 { 2321 if ((pD ISState->param1.flags == USE_REG_GEN32 || pDISState->param1.flags == USE_REG_GEN64) && pDISState->param2.flags == USE_REG_CR)2322 return EMInterpretCRxRead(pVM, pVCpu, pRegFrame, pD ISState->param1.base.reg_gen, pDISState->param2.base.reg_ctrl);2323 2324 if (pD ISState->param1.flags == USE_REG_CR && (pDISState->param2.flags == USE_REG_GEN32 || pDISState->param2.flags == USE_REG_GEN64))2325 return EMInterpretCRxWrite(pVM, pVCpu, pRegFrame, pD ISState->param1.base.reg_ctrl, pDISState->param2.base.reg_gen);2320 static int emInterpretMovCRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 2321 { 2322 if ((pDis->param1.flags == USE_REG_GEN32 || pDis->param1.flags == USE_REG_GEN64) && pDis->param2.flags == USE_REG_CR) 2323 return EMInterpretCRxRead(pVM, pVCpu, pRegFrame, pDis->param1.base.reg_gen, pDis->param2.base.reg_ctrl); 2324 2325 if (pDis->param1.flags == USE_REG_CR && (pDis->param2.flags == USE_REG_GEN32 || pDis->param2.flags == USE_REG_GEN64)) 2326 return EMInterpretCRxWrite(pVM, pVCpu, pRegFrame, pDis->param1.base.reg_ctrl, pDis->param2.base.reg_gen); 2326 2327 2327 2328 AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER); … … 2403 2404 * MOV DRx 2404 2405 */ 2405 static int emInterpretMovDRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)2406 static int emInterpretMovDRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 2406 2407 { 2407 2408 int rc = VERR_EM_INTERPRETER; 2408 2409 2409 if((pD ISState->param1.flags == USE_REG_GEN32 || pDISState->param1.flags == USE_REG_GEN64) && pDISState->param2.flags == USE_REG_DBG)2410 { 2411 rc = EMInterpretDRxRead(pVM, pVCpu, pRegFrame, pD ISState->param1.base.reg_gen, pDISState->param2.base.reg_dbg);2410 if((pDis->param1.flags == USE_REG_GEN32 || pDis->param1.flags == USE_REG_GEN64) && pDis->param2.flags == USE_REG_DBG) 2411 { 2412 rc = EMInterpretDRxRead(pVM, pVCpu, pRegFrame, pDis->param1.base.reg_gen, pDis->param2.base.reg_dbg); 2412 2413 } 2413 2414 else 2414 if(pD ISState->param1.flags == USE_REG_DBG && (pDISState->param2.flags == USE_REG_GEN32 || pDISState->param2.flags == USE_REG_GEN64))2415 { 2416 rc = EMInterpretDRxWrite(pVM, pVCpu, pRegFrame, pD ISState->param1.base.reg_dbg, pDISState->param2.base.reg_gen);2415 if(pDis->param1.flags == USE_REG_DBG && (pDis->param2.flags == USE_REG_GEN32 || pDis->param2.flags == USE_REG_GEN64)) 2416 { 2417 rc = EMInterpretDRxWrite(pVM, pVCpu, pRegFrame, pDis->param1.base.reg_dbg, pDis->param2.base.reg_gen); 2417 2418 } 2418 2419 else … … 2426 2427 * LLDT Emulation. 2427 2428 */ 2428 static int emInterpretLLdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)2429 static int emInterpretLLdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 2429 2430 { 2430 2431 OP_PARAMVAL param1; 2431 2432 RTSEL sel; 2432 2433 2433 int rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param1, ¶m1, PARAM_SOURCE);2434 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, ¶m1, PARAM_SOURCE); 2434 2435 if(RT_FAILURE(rc)) 2435 2436 return VERR_EM_INTERPRETER; … … 2473 2474 * LIDT/LGDT Emulation. 2474 2475 */ 2475 static int emInterpretLIGdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)2476 static int emInterpretLIGdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 2476 2477 { 2477 2478 OP_PARAMVAL param1; … … 2479 2480 X86XDTR32 dtr32; 2480 2481 2481 Log(("Emulate %s at %RGv\n", emGetMnemonic(pD ISState), (RTGCPTR)pRegFrame->rip));2482 Log(("Emulate %s at %RGv\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip)); 2482 2483 2483 2484 /* Only for the VT-x real-mode emulation case. */ 2484 2485 AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER); 2485 2486 2486 int rc = DISQueryParamVal(pRegFrame, pD ISState, &pDISState->param1, ¶m1, PARAM_SOURCE);2487 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, ¶m1, PARAM_SOURCE); 2487 2488 if(RT_FAILURE(rc)) 2488 2489 return VERR_EM_INTERPRETER; … … 2491 2492 { 2492 2493 case PARMTYPE_ADDRESS: 2493 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pD ISState, &pDISState->param1, param1.val.val16);2494 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, param1.val.val16); 2494 2495 break; 2495 2496 … … 2501 2502 AssertRCReturn(rc, VERR_EM_INTERPRETER); 2502 2503 2503 if (!(pD ISState->prefix & PREFIX_OPSIZE))2504 if (!(pDis->prefix & PREFIX_OPSIZE)) 2504 2505 dtr32.uAddr &= 0xffffff; /* 16 bits operand size */ 2505 2506 2506 if (pD ISState->pCurInstr->opcode == OP_LIDT)2507 if (pDis->pCurInstr->opcode == OP_LIDT) 2507 2508 CPUMSetGuestIDTR(pVCpu, dtr32.uAddr, dtr32.cb); 2508 2509 else … … 2520 2521 * @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched 2521 2522 */ 2522 static int emInterpretSti(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)2523 static int emInterpretSti(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 2523 2524 { 2524 2525 PPATMGCSTATE pGCState = PATMQueryGCState(pVM); … … 2534 2535 Assert(pvFault == SELMToFlat(pVM, DIS_SELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip)); 2535 2536 2536 pVCpu->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pD ISState->opsize;2537 pVCpu->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pDis->opsize; 2537 2538 VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS); 2538 2539 … … 2545 2546 * HLT Emulation. 2546 2547 */ 2547 static int emInterpretHlt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)2548 static int emInterpretHlt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 2548 2549 { 2549 2550 return VINF_EM_HALT; … … 2612 2613 * RDTSC Emulation. 2613 2614 */ 2614 static int emInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)2615 static int emInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 2615 2616 { 2616 2617 return EMInterpretRdtsc(pVM, pVCpu, pRegFrame); … … 2648 2649 * RDPMC Emulation 2649 2650 */ 2650 static int emInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)2651 static int emInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 2651 2652 { 2652 2653 return EMInterpretRdpmc(pVM, pVCpu, pRegFrame); … … 2656 2657 * MONITOR Emulation. 2657 2658 */ 2658 static int emInterpretMonitor(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)2659 static int emInterpretMonitor(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 2659 2660 { 2660 2661 uint32_t u32Dummy, u32ExtFeatures, cpl; 2661 2662 2662 Assert(pD ISState->mode != CPUMODE_64BIT); /** @todo check */2663 Assert(pDis->mode != CPUMODE_64BIT); /** @todo check */ 2663 2664 if (pRegFrame->ecx != 0) 2664 2665 return VERR_EM_INTERPRETER; /* illegal value. */ … … 2684 2685 uint32_t u32Dummy, u32ExtFeatures, cpl; 2685 2686 2686 /* @todo bit 1 is supposed to tell the cpu to wake us up on interrupts even if IF is cleared. 2687 /* @todo bit 1 is supposed to tell the cpu to wake us up on interrupts even if IF is cleared. 2687 2688 * Not sure which models. Intel docs say ecx and eax must be zero for Pentium 4 CPUs 2688 2689 * CPUID.05H.ECX[0] defines support for power management extensions (eax) … … 2704 2705 } 2705 2706 2706 static int emInterpretMWait(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)2707 { 2708 Assert(pD ISState->mode != CPUMODE_64BIT); /** @todo check */2707 static int emInterpretMWait(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 2708 { 2709 Assert(pDis->mode != CPUMODE_64BIT); /** @todo check */ 2709 2710 2710 2711 return EMInterpretMWait(pVM, pVCpu, pRegFrame); … … 2926 2927 * RDMSR Emulation. 2927 2928 */ 2928 static int emInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)2929 static int emInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 2929 2930 { 2930 2931 /* Note: the Intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */ 2931 Assert(!(pD ISState->prefix & PREFIX_REX));2932 Assert(!(pDis->prefix & PREFIX_REX)); 2932 2933 return EMInterpretRdmsr(pVM, pVCpu, pRegFrame); 2933 2934 } … … 3069 3070 * WRMSR Emulation. 3070 3071 */ 3071 static int emInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)3072 static int emInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 3072 3073 { 3073 3074 return EMInterpretWrmsr(pVM, pVCpu, pRegFrame); … … 3079 3080 * @copydoc EMInterpretInstructionCPU 3080 3081 */ 3081 DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pD ISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)3082 DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize) 3082 3083 { 3083 3084 Assert(pcbSize); … … 3091 3092 uint32_t cpl = CPUMGetGuestCPL(pVCpu, pRegFrame); 3092 3093 if ( cpl != 0 3093 && pD ISState->pCurInstr->opcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */3094 && pDis->pCurInstr->opcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */ 3094 3095 { 3095 3096 Log(("WARNING: refusing instruction emulation for user-mode code!!\n")); … … 3099 3100 3100 3101 #ifdef IN_RC 3101 if ( (pD ISState->prefix & (PREFIX_REPNE | PREFIX_REP))3102 || ( (pD ISState->prefix & PREFIX_LOCK)3103 && pD ISState->pCurInstr->opcode != OP_CMPXCHG3104 && pD ISState->pCurInstr->opcode != OP_CMPXCHG8B3105 && pD ISState->pCurInstr->opcode != OP_XADD3106 && pD ISState->pCurInstr->opcode != OP_OR3107 && pD ISState->pCurInstr->opcode != OP_BTR3102 if ( (pDis->prefix & (PREFIX_REPNE | PREFIX_REP)) 3103 || ( (pDis->prefix & PREFIX_LOCK) 3104 && pDis->pCurInstr->opcode != OP_CMPXCHG 3105 && pDis->pCurInstr->opcode != OP_CMPXCHG8B 3106 && pDis->pCurInstr->opcode != OP_XADD 3107 && pDis->pCurInstr->opcode != OP_OR 3108 && pDis->pCurInstr->opcode != OP_BTR 3108 3109 ) 3109 3110 ) 3110 3111 #else 3111 if ( (pD ISState->prefix & PREFIX_REPNE)3112 || ( (pD ISState->prefix & PREFIX_REP)3113 && pD ISState->pCurInstr->opcode != OP_STOSWD3112 if ( (pDis->prefix & PREFIX_REPNE) 3113 || ( (pDis->prefix & PREFIX_REP) 3114 && pDis->pCurInstr->opcode != OP_STOSWD 3114 3115 ) 3115 || ( (pD ISState->prefix & PREFIX_LOCK)3116 && pD ISState->pCurInstr->opcode != OP_OR3117 && pD ISState->pCurInstr->opcode != OP_BTR3118 && pD ISState->pCurInstr->opcode != OP_CMPXCHG3119 && pD ISState->pCurInstr->opcode != OP_CMPXCHG8B3116 || ( (pDis->prefix & PREFIX_LOCK) 3117 && pDis->pCurInstr->opcode != OP_OR 3118 && pDis->pCurInstr->opcode != OP_BTR 3119 && pDis->pCurInstr->opcode != OP_CMPXCHG 3120 && pDis->pCurInstr->opcode != OP_CMPXCHG8B 3120 3121 ) 3121 3122 ) … … 3132 3133 * Whitelisted instructions are safe. 3133 3134 */ 3134 if ( pD ISState->param1.size > 43135 if ( pDis->param1.size > 4 3135 3136 && CPUMIsGuestIn64BitCode(pVCpu, pRegFrame)) 3136 3137 { 3137 uint32_t uOpCode = pD ISState->pCurInstr->opcode;3138 uint32_t uOpCode = pDis->pCurInstr->opcode; 3138 3139 if ( uOpCode != OP_STOSWD 3139 3140 && uOpCode != OP_MOV … … 3156 3157 { 3157 3158 # ifdef VBOX_WITH_STATISTICS 3158 switch (pD ISState->pCurInstr->opcode)3159 switch (pDis->pCurInstr->opcode) 3159 3160 { 3160 3161 # define INTERPRET_FAILED_CASE(opcode, Instr) \ … … 3210 3211 int rc; 3211 3212 #if (defined(VBOX_STRICT) || defined(LOG_ENABLED)) 3212 LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pD ISState)));3213 #endif 3214 switch (pD ISState->pCurInstr->opcode)3213 LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pDis))); 3214 #endif 3215 switch (pDis->pCurInstr->opcode) 3215 3216 { 3216 3217 /* … … 3219 3220 # define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \ 3220 3221 case opcode:\ 3221 if (pD ISState->prefix & PREFIX_LOCK) \3222 rc = emInterpretLock##InstrFn(pVM, pVCpu, pD ISState, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \3222 if (pDis->prefix & PREFIX_LOCK) \ 3223 rc = emInterpretLock##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \ 3223 3224 else \ 3224 rc = emInterpret##InstrFn(pVM, pVCpu, pD ISState, pRegFrame, pvFault, pcbSize, pfnEmulate); \3225 rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \ 3225 3226 if (RT_SUCCESS(rc)) \ 3226 3227 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \ … … 3230 3231 #define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \ 3231 3232 case opcode:\ 3232 rc = emInterpret##InstrFn(pVM, pVCpu, pD ISState, pRegFrame, pvFault, pcbSize, pfnEmulate); \3233 rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \ 3233 3234 if (RT_SUCCESS(rc)) \ 3234 3235 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \ … … 3244 3245 #define INTERPRET_CASE(opcode, Instr) \ 3245 3246 case opcode:\ 3246 rc = emInterpret##Instr(pVM, pVCpu, pD ISState, pRegFrame, pvFault, pcbSize); \3247 rc = emInterpret##Instr(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \ 3247 3248 if (RT_SUCCESS(rc)) \ 3248 3249 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \ … … 3253 3254 #define INTERPRET_CASE_EX_DUAL_PARAM2(opcode, Instr, InstrFn) \ 3254 3255 case opcode:\ 3255 rc = emInterpret##InstrFn(pVM, pVCpu, pD ISState, pRegFrame, pvFault, pcbSize); \3256 rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \ 3256 3257 if (RT_SUCCESS(rc)) \ 3257 3258 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \ … … 3320 3321 3321 3322 default: 3322 Log3(("emInterpretInstructionCPU: opcode=%d\n", pD ISState->pCurInstr->opcode));3323 Log3(("emInterpretInstructionCPU: opcode=%d\n", pDis->pCurInstr->opcode)); 3323 3324 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc)); 3324 3325 return VERR_EM_INTERPRETER; -
trunk/src/VBox/VMM/VMMAll/IOMAllMMIO.cpp ¶
r20014 r20530 1108 1108 * Disassemble the instruction and interpret it. 1109 1109 */ 1110 DISCPUSTATE Cpu; 1111 unsigned cbOp; 1112 rc = EMInterpretDisasOne(pVM, VMMGetCpu(pVM), pCtxCore, &Cpu, &cbOp); 1110 PVMCPU pVCpu = VMMGetCpu(pVM); 1111 PDISCPUSTATE pDis = &pVCpu->iom.s.DisState; 1112 unsigned cbOp; 1113 rc = EMInterpretDisasOne(pVM, pVCpu, pCtxCore, pDis, &cbOp); 1113 1114 AssertRC(rc); 1114 1115 if (RT_FAILURE(rc)) … … 1117 1118 return rc; 1118 1119 } 1119 switch ( Cpu.pCurInstr->opcode)1120 switch (pDis->pCurInstr->opcode) 1120 1121 { 1121 1122 case OP_MOV: … … 1125 1126 STAM_PROFILE_START(&pVM->iom.s.StatRZInstMov, b); 1126 1127 if (uErrorCode & X86_TRAP_PF_RW) 1127 rc = iomInterpretMOVxXWrite(pVM, pCtxCore, &Cpu, pRange, GCPhysFault);1128 rc = iomInterpretMOVxXWrite(pVM, pCtxCore, pDis, pRange, GCPhysFault); 1128 1129 else 1129 rc = iomInterpretMOVxXRead(pVM, pCtxCore, &Cpu, pRange, GCPhysFault);1130 rc = iomInterpretMOVxXRead(pVM, pCtxCore, pDis, pRange, GCPhysFault); 1130 1131 STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstMov, b); 1131 1132 break; … … 1139 1140 STAM_PROFILE_ADV_START(&pVM->iom.s.StatRZInstMovs, c); 1140 1141 PSTAMPROFILE pStat = NULL; 1141 rc = iomInterpretMOVS(pVM, uErrorCode, pCtxCore, GCPhysFault, &Cpu, pRange, &pStat);1142 rc = iomInterpretMOVS(pVM, uErrorCode, pCtxCore, GCPhysFault, pDis, pRange, &pStat); 1142 1143 STAM_PROFILE_ADV_STOP_EX(&pVM->iom.s.StatRZInstMovs, pStat, c); 1143 1144 break; … … 1149 1150 Assert(uErrorCode & X86_TRAP_PF_RW); 1150 1151 STAM_PROFILE_START(&pVM->iom.s.StatRZInstStos, d); 1151 rc = iomInterpretSTOS(pVM, pCtxCore, GCPhysFault, &Cpu, pRange);1152 rc = iomInterpretSTOS(pVM, pCtxCore, GCPhysFault, pDis, pRange); 1152 1153 STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstStos, d); 1153 1154 break; … … 1157 1158 Assert(!(uErrorCode & X86_TRAP_PF_RW)); 1158 1159 STAM_PROFILE_START(&pVM->iom.s.StatRZInstLods, e); 1159 rc = iomInterpretLODS(pVM, pCtxCore, GCPhysFault, &Cpu, pRange);1160 rc = iomInterpretLODS(pVM, pCtxCore, GCPhysFault, pDis, pRange); 1160 1161 STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstLods, e); 1161 1162 break; … … 1164 1165 Assert(!(uErrorCode & X86_TRAP_PF_RW)); 1165 1166 STAM_PROFILE_START(&pVM->iom.s.StatRZInstCmp, f); 1166 rc = iomInterpretCMP(pVM, pCtxCore, GCPhysFault, &Cpu, pRange);1167 rc = iomInterpretCMP(pVM, pCtxCore, GCPhysFault, pDis, pRange); 1167 1168 STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstCmp, f); 1168 1169 break; … … 1170 1171 case OP_AND: 1171 1172 STAM_PROFILE_START(&pVM->iom.s.StatRZInstAnd, g); 1172 rc = iomInterpretOrXorAnd(pVM, pCtxCore, GCPhysFault, &Cpu, pRange, EMEmulateAnd);1173 rc = iomInterpretOrXorAnd(pVM, pCtxCore, GCPhysFault, pDis, pRange, EMEmulateAnd); 1173 1174 STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstAnd, g); 1174 1175 break; … … 1176 1177 case OP_OR: 1177 1178 STAM_PROFILE_START(&pVM->iom.s.StatRZInstOr, k); 1178 rc = iomInterpretOrXorAnd(pVM, pCtxCore, GCPhysFault, &Cpu, pRange, EMEmulateOr);1179 rc = iomInterpretOrXorAnd(pVM, pCtxCore, GCPhysFault, pDis, pRange, EMEmulateOr); 1179 1180 STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstOr, k); 1180 1181 break; … … 1182 1183 case OP_XOR: 1183 1184 STAM_PROFILE_START(&pVM->iom.s.StatRZInstXor, m); 1184 rc = iomInterpretOrXorAnd(pVM, pCtxCore, GCPhysFault, &Cpu, pRange, EMEmulateXor);1185 rc = iomInterpretOrXorAnd(pVM, pCtxCore, GCPhysFault, pDis, pRange, EMEmulateXor); 1185 1186 STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstXor, m); 1186 1187 break; … … 1189 1190 Assert(!(uErrorCode & X86_TRAP_PF_RW)); 1190 1191 STAM_PROFILE_START(&pVM->iom.s.StatRZInstTest, h); 1191 rc = iomInterpretTEST(pVM, pCtxCore, GCPhysFault, &Cpu, pRange);1192 rc = iomInterpretTEST(pVM, pCtxCore, GCPhysFault, pDis, pRange); 1192 1193 STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstTest, h); 1193 1194 break; … … 1196 1197 Assert(!(uErrorCode & X86_TRAP_PF_RW)); 1197 1198 STAM_PROFILE_START(&pVM->iom.s.StatRZInstBt, l); 1198 rc = iomInterpretBT(pVM, pCtxCore, GCPhysFault, &Cpu, pRange);1199 rc = iomInterpretBT(pVM, pCtxCore, GCPhysFault, pDis, pRange); 1199 1200 STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstBt, l); 1200 1201 break; … … 1202 1203 case OP_XCHG: 1203 1204 STAM_PROFILE_START(&pVM->iom.s.StatRZInstXchg, i); 1204 rc = iomInterpretXCHG(pVM, pCtxCore, GCPhysFault, &Cpu, pRange);1205 rc = iomInterpretXCHG(pVM, pCtxCore, GCPhysFault, pDis, pRange); 1205 1206 STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstXchg, i); 1206 1207 break; -
trunk/src/VBox/VMM/VMMAll/PGMAllBth.h ¶
r20519 r20530 727 727 if (rc == VINF_SUCCESS) 728 728 { 729 DISCPUSTATE Cpu;730 uint32_t cbOp;731 rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, &Cpu, &cbOp);729 PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState; 730 uint32_t cbOp; 731 rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, pDis, &cbOp); 732 732 733 733 /* For now we'll restrict this to rep movsw/d instructions */ 734 734 if ( rc == VINF_SUCCESS 735 && Cpu.pCurInstr->opcode == OP_MOVSWD736 && ( Cpu.prefix & PREFIX_REP))735 && pDis->pCurInstr->opcode == OP_MOVSWD 736 && (pDis->prefix & PREFIX_REP)) 737 737 { 738 738 CSAMMarkPossibleCodePage(pVM, pvFault); -
trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp ¶
r20059 r20530 75 75 * we will simply skip it. Otherwise we'll have to defer it to REM. 76 76 */ 77 uint32_t cbOp;78 DISCPUSTATE Cpu;79 rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, &Cpu, &cbOp);77 uint32_t cbOp; 78 PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState; 79 rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, pDis, &cbOp); 80 80 if ( RT_SUCCESS(rc) 81 && Cpu.mode == CPUMODE_32BIT /** @todo why does this matter? */82 && !( Cpu.prefix & (PREFIX_REPNE | PREFIX_REP | PREFIX_SEG)))81 && pDis->mode == CPUMODE_32BIT /** @todo why does this matter? */ 82 && !(pDis->prefix & (PREFIX_REPNE | PREFIX_REP | PREFIX_SEG))) 83 83 { 84 switch ( Cpu.opcode)84 switch (pDis->opcode) 85 85 { 86 86 /** @todo Find other instructions we can safely skip, possibly -
trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp ¶
r20489 r20530 243 243 * @param uAddress In R0 and GC this is the guest context fault address (flat). 244 244 * In R3 this is the host context 'fault' address. 245 * @param p CpuThe disassembler state for figuring out the write size.245 * @param pDis The disassembler state for figuring out the write size. 246 246 * This need not be specified if the caller knows we won't do cross entry accesses. 247 247 */ 248 void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE p Cpu)248 void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pDis) 249 249 { 250 250 Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX); 251 251 const unsigned off = GCPhysFault & PAGE_OFFSET_MASK; 252 const unsigned cbWrite = (pCpu) ? pgmPoolDisasWriteSize(pCpu) : 0;252 const unsigned cbWrite = pDis ? pgmPoolDisasWriteSize(pDis) : 0; 253 253 PVM pVM = pPool->CTX_SUFF(pVM); 254 254 … … 354 354 355 355 /* paranoia / a bit assumptive. */ 356 if ( p Cpu356 if ( pDis 357 357 && (off & 3) 358 358 && (off & 3) + cbWrite > 4) … … 407 407 408 408 /* paranoia / a bit assumptive. */ 409 if ( p Cpu409 if ( pDis 410 410 && (off & 7) 411 411 && (off & 7) + cbWrite > sizeof(X86PTEPAE)) … … 466 466 } 467 467 /* paranoia / a bit assumptive. */ 468 if ( p Cpu468 if ( pDis 469 469 && (off & 3) 470 470 && (off & 3) + cbWrite > sizeof(X86PTE)) … … 549 549 } 550 550 /* paranoia / a bit assumptive. */ 551 if ( p Cpu551 if ( pDis 552 552 && (off & 7) 553 553 && (off & 7) + cbWrite > sizeof(X86PDEPAE)) … … 621 621 622 622 /* paranoia / a bit assumptive. */ 623 if ( p Cpu623 if ( pDis 624 624 && (offPdpt & 7) 625 625 && (offPdpt & 7) + cbWrite > sizeof(X86PDPE)) … … 673 673 } 674 674 /* paranoia / a bit assumptive. */ 675 if ( p Cpu675 if ( pDis 676 676 && (off & 7) 677 677 && (off & 7) + cbWrite > sizeof(X86PDEPAE)) … … 711 711 } 712 712 /* paranoia / a bit assumptive. */ 713 if ( p Cpu713 if ( pDis 714 714 && (off & 7) 715 715 && (off & 7) + cbWrite > sizeof(X86PDPE)) … … 744 744 } 745 745 /* paranoia / a bit assumptive. */ 746 if ( p Cpu746 if ( pDis 747 747 && (off & 7) 748 748 && (off & 7) + cbWrite > sizeof(X86PDPE)) … … 781 781 * @returns true if it's likly that we're forking, otherwise false. 782 782 * @param pPool The pool. 783 * @param p CpuThe disassembled instruction.783 * @param pDis The disassembled instruction. 784 784 * @param offFault The access offset. 785 785 */ 786 DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE p Cpu, unsigned offFault)786 DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pDis, unsigned offFault) 787 787 { 788 788 /* … … 802 802 * do_fork 803 803 */ 804 if ( p Cpu->pCurInstr->opcode == OP_BTR804 if ( pDis->pCurInstr->opcode == OP_BTR 805 805 && !(offFault & 4) 806 806 /** @todo Validate that the bit index is X86_PTE_RW. */ … … 821 821 * @param pVM VM Handle. 822 822 * @param pRegFrame Trap register frame. 823 * @param p CpuThe disassembly info for the faulting instruction.823 * @param pDis The disassembly info for the faulting instruction. 824 824 * @param pvFault The fault address. 825 825 * 826 826 * @remark The REP prefix check is left to the caller because of STOSD/W. 827 827 */ 828 DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE p Cpu, RTGCPTR pvFault)828 DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, RTGCPTR pvFault) 829 829 { 830 830 #ifndef IN_RC … … 841 841 #endif 842 842 843 switch (p Cpu->pCurInstr->opcode)843 switch (pDis->pCurInstr->opcode) 844 844 { 845 845 /* call implies the actual push of the return address faulted */ … … 867 867 case OP_MOVSWD: 868 868 case OP_STOSWD: 869 if ( p Cpu->prefix == (PREFIX_REP|PREFIX_REX)869 if ( pDis->prefix == (PREFIX_REP|PREFIX_REX) 870 870 && pRegFrame->rcx >= 0x40 871 871 ) 872 872 { 873 Assert(p Cpu->mode == CPUMODE_64BIT);873 Assert(pDis->mode == CPUMODE_64BIT); 874 874 875 875 Log(("pgmPoolMonitorIsReused: OP_STOSQ\n")); … … 878 878 return false; 879 879 } 880 if ( (p Cpu->param1.flags & USE_REG_GEN32)881 && (p Cpu->param1.base.reg_gen == USE_REG_ESP))880 if ( (pDis->param1.flags & USE_REG_GEN32) 881 && (pDis->param1.base.reg_gen == USE_REG_ESP)) 882 882 { 883 883 Log4(("pgmPoolMonitorIsReused: ESP\n")); … … 897 897 * @param pPool The pool. 898 898 * @param pPage The pool page (head). 899 * @param p CpuThe disassembly of the write instruction.899 * @param pDis The disassembly of the write instruction. 900 900 * @param pRegFrame The trap register frame. 901 901 * @param GCPhysFault The fault address as guest physical address. 902 902 * @param pvFault The fault address. 903 903 */ 904 static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE p Cpu,904 static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis, 905 905 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault) 906 906 { … … 914 914 */ 915 915 uint32_t cbWritten; 916 int rc2 = EMInterpretInstructionCPU(pVM, pVCpu, p Cpu, pRegFrame, pvFault, &cbWritten);916 int rc2 = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, &cbWritten); 917 917 if (RT_SUCCESS(rc2)) 918 pRegFrame->rip += p Cpu->opsize;918 pRegFrame->rip += pDis->opsize; 919 919 else if (rc2 == VERR_EM_INTERPRETER) 920 920 { … … 953 953 * @param pPool The pool. 954 954 * @param pPage The pool page (head). 955 * @param p CpuThe disassembly of the write instruction.955 * @param pDis The disassembly of the write instruction. 956 956 * @param pRegFrame The trap register frame. 957 957 * @param GCPhysFault The fault address as guest physical address. 958 958 * @param pvFault The fault address. 959 959 */ 960 DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE p Cpu,960 DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis, 961 961 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault) 962 962 { 963 Assert(p Cpu->mode == CPUMODE_32BIT);963 Assert(pDis->mode == CPUMODE_32BIT); 964 964 965 965 Log3(("pgmPoolAccessHandlerSTOSD\n")); … … 999 999 pRegFrame->ecx--; 1000 1000 } 1001 pRegFrame->rip += p Cpu->opsize;1001 pRegFrame->rip += pDis->opsize; 1002 1002 1003 1003 #ifdef IN_RC … … 1019 1019 * @param pPool The pool. 1020 1020 * @param pPage The pool page (head). 1021 * @param p CpuThe disassembly of the write instruction.1021 * @param pDis The disassembly of the write instruction. 1022 1022 * @param pRegFrame The trap register frame. 1023 1023 * @param GCPhysFault The fault address as guest physical address. 1024 1024 * @param pvFault The fault address. 1025 1025 */ 1026 DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE p Cpu,1026 DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis, 1027 1027 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault) 1028 1028 { … … 1040 1040 #ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 1041 1041 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu); 1042 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, p Cpu);1042 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pDis); 1043 1043 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset); 1044 1044 #else 1045 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, p Cpu);1045 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pDis); 1046 1046 #endif 1047 1047 … … 1050 1050 */ 1051 1051 uint32_t cb; 1052 int rc = EMInterpretInstructionCPU(pVM, pVCpu, p Cpu, pRegFrame, pvFault, &cb);1052 int rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, &cb); 1053 1053 if (RT_SUCCESS(rc)) 1054 pRegFrame->rip += p Cpu->opsize;1054 pRegFrame->rip += pDis->opsize; 1055 1055 else if (rc == VERR_EM_INTERPRETER) 1056 1056 { 1057 1057 LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n", 1058 pRegFrame->cs, (RTGCPTR)pRegFrame->rip, p Cpu->pCurInstr->opcode));1058 pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode)); 1059 1059 rc = VINF_EM_RAW_EMULATE_INSTR; 1060 1060 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr)); … … 1111 1111 * Disassemble the faulting instruction. 1112 1112 */ 1113 DISCPUSTATE Cpu;1114 int rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, &Cpu, NULL);1113 PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState; 1114 int rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, pDis, NULL); 1115 1115 AssertRCReturn(rc, rc); 1116 1116 … … 1132 1132 || pgmPoolIsPageLocked(&pVM->pgm.s, pPage) 1133 1133 ) 1134 && !(fReused = pgmPoolMonitorIsReused(pVM, pRegFrame, &Cpu, pvFault))1135 && !pgmPoolMonitorIsForking(pPool, &Cpu, GCPhysFault & PAGE_OFFSET_MASK))1134 && !(fReused = pgmPoolMonitorIsReused(pVM, pRegFrame, pDis, pvFault)) 1135 && !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK)) 1136 1136 { 1137 1137 /* 1138 1138 * Simple instructions, no REP prefix. 1139 1139 */ 1140 if (!( Cpu.prefix & (PREFIX_REP | PREFIX_REPNE)))1141 { 1142 rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);1140 if (!(pDis->prefix & (PREFIX_REP | PREFIX_REPNE))) 1141 { 1142 rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault); 1143 1143 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a); 1144 1144 pgmUnlock(pVM); … … 1150 1150 * We have to deal with these or we'll kill the cache and performance. 1151 1151 */ 1152 if ( Cpu.pCurInstr->opcode == OP_STOSWD1152 if ( pDis->pCurInstr->opcode == OP_STOSWD 1153 1153 && CPUMGetGuestCPL(pVCpu, pRegFrame) == 0 1154 1154 && pRegFrame->ecx <= 0x20 … … 1156 1156 && !((uintptr_t)pvFault & 3) 1157 1157 && (pRegFrame->eax == 0 || pRegFrame->eax == 0x80) /* the two values observed. */ 1158 && Cpu.mode == CPUMODE_32BIT1159 && Cpu.opmode == CPUMODE_32BIT1160 && Cpu.addrmode == CPUMODE_32BIT1161 && Cpu.prefix == PREFIX_REP1158 && pDis->mode == CPUMODE_32BIT 1159 && pDis->opmode == CPUMODE_32BIT 1160 && pDis->addrmode == CPUMODE_32BIT 1161 && pDis->prefix == PREFIX_REP 1162 1162 && !pRegFrame->eflags.Bits.u1DF 1163 1163 ) 1164 1164 { 1165 rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);1165 rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault); 1166 1166 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a); 1167 1167 pgmUnlock(pVM); … … 1172 1172 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix)); 1173 1173 Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n", 1174 pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, Cpu.pCurInstr->opcode, Cpu.prefix));1174 pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode, pDis->prefix)); 1175 1175 } 1176 1176 … … 1183 1183 * the reuse detection must be fixed. 1184 1184 */ 1185 rc = pgmPoolAccessHandlerFlush(pVM, pVCpu, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);1185 rc = pgmPoolAccessHandlerFlush(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault); 1186 1186 if (rc == VINF_EM_RAW_EMULATE_INSTR && fReused) 1187 1187 rc = VINF_SUCCESS; -
trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp ¶
r20516 r20530 1023 1023 * 1024 1024 * Interrupts are disabled before the call to make sure we don't miss any interrupt 1025 * that would flag preemption (IPI, timer tick, ++). 1025 * that would flag preemption (IPI, timer tick, ++). 1026 1026 * 1027 1027 * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB … … 2062 2062 { 2063 2063 /* ins/outs */ 2064 DISCPUSTATE Cpu;2064 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState; 2065 2065 2066 2066 /* Disassemble manually to deal with segment prefixes. */ 2067 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, NULL);2067 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL); 2068 2068 if (rc == VINF_SUCCESS) 2069 2069 { … … 2072 2072 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize)); 2073 2073 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite); 2074 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, Cpu.prefix, uIOSize);2074 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize); 2075 2075 } 2076 2076 else … … 2078 2078 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize)); 2079 2079 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead); 2080 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, Cpu.prefix, uIOSize);2080 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize); 2081 2081 } 2082 2082 } … … 2337 2337 * @returns VBox status code. 2338 2338 * @param pVCpu The VM CPU to operate on. 2339 * @param pDis StateDisassembly state2339 * @param pDis Disassembly state 2340 2340 * @param pCtx CPU context 2341 2341 * @param cbOp Opcode size 2342 2342 */ 2343 static int svmR0EmulateTprMov(PVMCPU pVCpu, DISCPUSTATE *pDisState, PCPUMCTX pCtx, unsigned cbOp)2343 static int svmR0EmulateTprMov(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTX pCtx, unsigned cbOp) 2344 2344 { 2345 2345 int rc; 2346 2346 2347 if (pDis State->param1.flags == USE_DISPLACEMENT32)2347 if (pDis->param1.flags == USE_DISPLACEMENT32) 2348 2348 { 2349 2349 /* write */ … … 2351 2351 2352 2352 /* Fetch the new TPR value */ 2353 if (pDis State->param2.flags == USE_REG_GEN32)2353 if (pDis->param2.flags == USE_REG_GEN32) 2354 2354 { 2355 2355 uint32_t val; 2356 2356 2357 rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pDis State->param2.base.reg_gen, &val);2357 rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pDis->param2.base.reg_gen, &val); 2358 2358 AssertRC(rc); 2359 2359 u8Tpr = val >> 4; 2360 2360 } 2361 2361 else 2362 if (pDis State->param2.flags == USE_IMMEDIATE32)2363 { 2364 u8Tpr = (uint8_t)pDis State->param2.parval >> 4;2362 if (pDis->param2.flags == USE_IMMEDIATE32) 2363 { 2364 u8Tpr = (uint8_t)pDis->param2.parval >> 4; 2365 2365 } 2366 2366 else … … 2375 2375 } 2376 2376 else 2377 if (pDis State->param2.flags == USE_DISPLACEMENT32)2377 if (pDis->param2.flags == USE_DISPLACEMENT32) 2378 2378 { 2379 2379 /* read */ … … 2385 2385 AssertRC(rc); 2386 2386 2387 rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pDis State->param1.base.reg_gen, u8Tpr << 4);2387 rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pDis->param1.base.reg_gen, u8Tpr << 4); 2388 2388 AssertRC(rc); 2389 2389 … … 2405 2405 static int svmR0ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) 2406 2406 { 2407 RTGCPTR oldrip = pCtx->rip;2408 DISCPUSTATE Cpu;2409 unsigned cbOp;2407 RTGCPTR oldrip = pCtx->rip; 2408 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState; 2409 unsigned cbOp; 2410 2410 2411 2411 Log(("Replace TPR access at %RGv\n", pCtx->rip)); 2412 2412 2413 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);2413 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp); 2414 2414 AssertRC(rc); 2415 2415 if ( rc == VINF_SUCCESS 2416 && Cpu.pCurInstr->opcode == OP_MOV)2416 && pDis->pCurInstr->opcode == OP_MOV) 2417 2417 { 2418 2418 #if 0 2419 2419 uint8_t szInstr[15]; 2420 2420 if ( cbOp == 10 2421 && Cpu.param1.flags == USE_DISPLACEMENT322422 && Cpu.param2.flags == USE_IMMEDIATE32)2421 && pDis->param1.flags == USE_DISPLACEMENT32 2422 && pDis->param2.flags == USE_IMMEDIATE32) 2423 2423 { 2424 2424 /* Found: … … 2431 2431 * 2432 2432 */ 2433 uint32_t u32tpr = (uint32_t) Cpu.param2.parval;2433 uint32_t u32tpr = (uint32_t)pDis->param2.parval; 2434 2434 2435 2435 u32tpr = (u32tpr >> 4) & 0xf; 2436 2436 2437 /* Check if the next instruction overwrites a general purpose register. If 2437 /* Check if the next instruction overwrites a general purpose register. If 2438 2438 * it does, then we can safely use it ourselves. 2439 2439 */ 2440 2440 pCtx->rip += cbOp; 2441 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);2441 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp); 2442 2442 pCtx->rip = oldrip; 2443 2443 if ( rc == VINF_SUCCESS 2444 && Cpu.pCurInstr->opcode == OP_MOV2445 && Cpu.param1.flags == USE_REG_GEN32)2444 && pDis->pCurInstr->opcode == OP_MOV 2445 && pDis->param1.flags == USE_REG_GEN32) 2446 2446 { 2447 2447 /* 0xB8, dword immediate = mov eax, dword immediate */ 2448 szInstr[0] = 0xB8 + Cpu.param1.base.reg_gen;2448 szInstr[0] = 0xB8 + pDis->param1.base.reg_gen; 2449 2449 szInstr[1] = (uint8_t)u32tpr; 2450 2450 szInstr[2] = 0; … … 2456 2456 szInstr[6] = 0x0F; 2457 2457 szInstr[7] = 0x22; 2458 szInstr[8] = 0xC0 | Cpu.param1.base.reg_gen;2458 szInstr[8] = 0xC0 | pDis->param1.base.reg_gen; 2459 2459 szInstr[9] = 0x90; /* nop */ 2460 2460 … … 2468 2468 else 2469 2469 { 2470 if ( Cpu.param2.flags == USE_REG_GEN322470 if ( pDis->param2.flags == USE_REG_GEN32 2471 2471 && cbOp == 6) 2472 2472 { 2473 RTGCPTR GCPtrTpr = (uint32_t) Cpu.param1.disp32;2474 uint32_t uMmioReg = Cpu.param2.base.reg_gen;2473 RTGCPTR GCPtrTpr = (uint32_t)pDis->param1.disp32; 2474 uint32_t uMmioReg = pDis->param2.base.reg_gen; 2475 2475 2476 2476 /* Found: … … 2480 2480 */ 2481 2481 pCtx->rip += cbOp; 2482 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);2482 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp); 2483 2483 pCtx->rip = oldrip; 2484 2484 if ( rc == VINF_SUCCESS 2485 && Cpu.pCurInstr->opcode == OP_MOV2486 && Cpu.param1.flags == USE_REG_GEN322487 && Cpu.param2.flags == USE_DISPLACEMENT322488 && Cpu.param2.disp32 == (uint32_t)GCPtrTpr2485 && pDis->pCurInstr->opcode == OP_MOV 2486 && pDis->param1.flags == USE_REG_GEN32 2487 && pDis->param2.flags == USE_DISPLACEMENT32 2488 && pDis->param2.disp32 == (uint32_t)GCPtrTpr 2489 2489 && cbOp == 5) 2490 2490 { 2491 2491 /* mov new_reg, uMmioReg */ 2492 2492 szInstr[0] = 0x89; 2493 szInstr[1] = MAKE_MODRM(3, uMmioReg, Cpu.param1.base.reg_gen);2493 szInstr[1] = MAKE_MODRM(3, uMmioReg, pDis->param1.base.reg_gen); 2494 2494 2495 2495 /* Let's hope the guest won't mind us trashing the source register... … … 2518 2518 } 2519 2519 else 2520 if ( Cpu.param1.flags == USE_REG_GEN322520 if ( pDis->param1.flags == USE_REG_GEN32 2521 2521 && cbOp == 5) 2522 2522 { 2523 uint32_t uMmioReg = Cpu.param1.base.reg_gen;2523 uint32_t uMmioReg = pDis->param1.base.reg_gen; 2524 2524 2525 2525 /* Found: … … 2529 2529 */ 2530 2530 pCtx->rip += cbOp; 2531 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);2531 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp); 2532 2532 pCtx->rip = oldrip; 2533 2533 if ( rc == VINF_SUCCESS 2534 && Cpu.pCurInstr->opcode == OP_SHR2535 && Cpu.param1.flags == USE_REG_GEN322536 && Cpu.param1.base.reg_gen == uMmioReg2537 && Cpu.param2.flags == USE_IMMEDIATE82538 && Cpu.param2.parval == 4)2534 && pDis->pCurInstr->opcode == OP_SHR 2535 && pDis->param1.flags == USE_REG_GEN32 2536 && pDis->param1.base.reg_gen == uMmioReg 2537 && pDis->param2.flags == USE_IMMEDIATE8 2538 && pDis->param2.parval == 4) 2539 2539 { 2540 2540 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */ … … 2542 2542 szInstr[1] = 0x0F; 2543 2543 szInstr[2] = 0x20; 2544 szInstr[3] = 0xC0 | Cpu.param1.base.reg_gen;2544 szInstr[3] = 0xC0 | pDis->param1.base.reg_gen; 2545 2545 for (unsigned i = 4; i < 5+cbOp; i++) 2546 2546 szInstr[i] = 0x90; /* nop */ … … 2555 2555 } 2556 2556 #endif 2557 rc = svmR0EmulateTprMov(pVCpu, &Cpu, pCtx, cbOp);2557 rc = svmR0EmulateTprMov(pVCpu, pDis, pCtx, cbOp); 2558 2558 if (rc != VINF_SUCCESS) 2559 2559 return rc; … … 2683 2683 if (RT_SUCCESS(rc)) 2684 2684 { 2685 uint32_t cbOp;2686 DISCPUSTATE Cpu;2687 2688 Cpu.mode = enmMode;2689 rc = EMInterpretDisasOneEx(pVM, pVCpu, pbCode, pRegFrame, &Cpu, &cbOp);2690 Assert(RT_FAILURE(rc) || Cpu.pCurInstr->opcode == OP_INVLPG);2691 if (RT_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)2685 uint32_t cbOp; 2686 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState; 2687 2688 pDis->mode = enmMode; 2689 rc = EMInterpretDisasOneEx(pVM, pVCpu, pbCode, pRegFrame, pDis, &cbOp); 2690 Assert(RT_FAILURE(rc) || pDis->pCurInstr->opcode == OP_INVLPG); 2691 if (RT_SUCCESS(rc) && pDis->pCurInstr->opcode == OP_INVLPG) 2692 2692 { 2693 Assert(cbOp == Cpu.opsize);2694 rc = svmR0InterpretInvlPg(pVCpu, &Cpu, pRegFrame, uASID);2693 Assert(cbOp == pDis->opsize); 2694 rc = svmR0InterpretInvlPg(pVCpu, pDis, pRegFrame, uASID); 2695 2695 if (RT_SUCCESS(rc)) 2696 2696 { -
trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp ¶
r20517 r20530 2315 2315 /* All done! Let's start VM execution. */ 2316 2316 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, z); 2317 #ifdef VBOX_STRICT2318 2317 Assert(idCpuCheck == RTMpCpuId()); 2319 #endif2320 2318 2321 2319 #ifdef VBOX_WITH_CRASHDUMP_MAGIC … … 2328 2326 TMNotifyEndOfExecution(pVCpu); 2329 2327 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED); 2328 Assert(!(ASMGetFlags() & X86_EFL_IF)); 2330 2329 ASMSetFlags(uOldEFlags); 2331 2330 #ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION … … 2676 2675 case X86_XCPT_GP: /* General protection failure exception.*/ 2677 2676 { 2678 uint32_t cbOp;2679 uint32_t cbSize;2680 DISCPUSTATE Cpu;2677 uint32_t cbOp; 2678 uint32_t cbSize; 2679 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState; 2681 2680 2682 2681 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP); … … 2695 2694 LogFlow(("Real mode X86_XCPT_GP instruction emulation at %RGv\n", (RTGCPTR)pCtx->rip)); 2696 2695 2697 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);2696 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp); 2698 2697 if (RT_SUCCESS(rc)) 2699 2698 { 2700 2699 bool fUpdateRIP = true; 2701 2700 2702 Assert(cbOp == Cpu.opsize);2703 switch ( Cpu.pCurInstr->opcode)2701 Assert(cbOp == pDis->opsize); 2702 switch (pDis->pCurInstr->opcode) 2704 2703 { 2705 2704 case OP_CLI: … … 2716 2715 fUpdateRIP = false; 2717 2716 rc = VINF_EM_HALT; 2718 pCtx->rip += Cpu.opsize;2717 pCtx->rip += pDis->opsize; 2719 2718 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt); 2720 2719 break; … … 2727 2726 X86EFLAGS eflags; 2728 2727 2729 if ( Cpu.prefix & PREFIX_OPSIZE)2728 if (pDis->prefix & PREFIX_OPSIZE) 2730 2729 { 2731 2730 cbParm = 4; … … 2769 2768 X86EFLAGS eflags; 2770 2769 2771 if ( Cpu.prefix & PREFIX_OPSIZE)2770 if (pDis->prefix & PREFIX_OPSIZE) 2772 2771 { 2773 2772 cbParm = 4; … … 2810 2809 uint16_t aIretFrame[3]; 2811 2810 2812 if ( Cpu.prefix & (PREFIX_OPSIZE | PREFIX_ADDRSIZE))2811 if (pDis->prefix & (PREFIX_OPSIZE | PREFIX_ADDRSIZE)) 2813 2812 { 2814 2813 rc = VERR_EM_INTERPRETER; … … 2844 2843 RTGCUINTPTR intInfo; 2845 2844 2846 LogFlow(("Realmode: INT %x\n", Cpu.param1.parval & 0xff));2847 intInfo = Cpu.param1.parval & 0xff;2845 LogFlow(("Realmode: INT %x\n", pDis->param1.parval & 0xff)); 2846 intInfo = pDis->param1.parval & 0xff; 2848 2847 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT); 2849 2848 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT); … … 2892 2891 2893 2892 default: 2894 rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, &cbSize);2893 rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, CPUMCTX2CORE(pCtx), 0, &cbSize); 2895 2894 break; 2896 2895 } … … 3341 3340 { 3342 3341 /* ins/outs */ 3343 DISCPUSTATE Cpu;3342 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState; 3344 3343 3345 3344 /* Disassemble manually to deal with segment prefixes. */ 3346 3345 /** @todo VMX_VMCS_EXIT_GUEST_LINEAR_ADDR contains the flat pointer operand of the instruction. */ 3347 3346 /** @todo VMX_VMCS32_RO_EXIT_INSTR_INFO also contains segment prefix info. */ 3348 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, NULL);3347 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL); 3349 3348 if (rc == VINF_SUCCESS) 3350 3349 { … … 3353 3352 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize)); 3354 3353 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite); 3355 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, Cpu.prefix, cbSize);3354 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->prefix, cbSize); 3356 3355 } 3357 3356 else … … 3359 3358 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize)); 3360 3359 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead); 3361 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, Cpu.prefix, cbSize);3360 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->prefix, cbSize); 3362 3361 } 3363 3362 } -
trunk/src/VBox/VMM/testcase/tstVMStructGC.cpp ¶
r20426 r20530 139 139 GEN_CHECK_OFF(EMCPU, fForceRAW); 140 140 GEN_CHECK_OFF(EMCPU, u.achPaddingFatalLongJump); 141 GEN_CHECK_OFF(EMCPU, DisState); 141 142 GEN_CHECK_OFF(EMCPU, StatForcedActions); 142 143 GEN_CHECK_OFF(EMCPU, StatTotalClis); … … 158 159 GEN_CHECK_OFF(IOM, pRangeLastReadR0); 159 160 GEN_CHECK_OFF(IOM, pRangeLastReadRC); 161 162 GEN_CHECK_SIZE(IOMCPU); 163 GEN_CHECK_OFF(IOMCPU, DisState); 164 GEN_CHECK_OFF(IOMCPU, Dummy[0]); 160 165 161 166 GEN_CHECK_SIZE(IOMMMIORANGE); … … 472 477 GEN_CHECK_OFF(PGMCPU, pfnRCBthVerifyAccessSyncPage); 473 478 GEN_CHECK_OFF(PGMCPU, pfnRCBthAssertCR3); 479 GEN_CHECK_OFF(PGMCPU, DisState); 480 GEN_CHECK_OFF(PGMCPU, cGuestModeChanges); 481 #ifdef VBOX_WITH_STATISTICS 482 GEN_CHECK_OFF(PGMCPU, pStatTrap0eAttributionR0); 483 GEN_CHECK_OFF(PGMCPU, pStatTrap0eAttributionRC); 484 #endif 474 485 GEN_CHECK_OFF(PGM, offVM); 475 486 GEN_CHECK_OFF(PGM, offVCpuPGM); … … 551 562 GEN_CHECK_OFF(PGM, cSharedPages); 552 563 GEN_CHECK_OFF(PGM, cZeroPages); 553 GEN_CHECK_OFF(PGMCPU, cGuestModeChanges);554 #ifdef VBOX_WITH_STATISTICS555 GEN_CHECK_OFF(PGMCPU, pStatTrap0eAttributionR0);556 GEN_CHECK_OFF(PGMCPU, pStatTrap0eAttributionRC);557 #endif558 564 559 565 GEN_CHECK_SIZE(PGMMAPPING); -
trunk/src/VBox/VMM/testcase/tstVMStructSize.cpp ¶
r19735 r20530 310 310 CHECK_MEMBER_ALIGNMENT(HWACCMCPU, Event.intInfo, 8); 311 311 312 /* The various disassembler state members. */ 313 CHECK_PADDING3(EMCPU, DisState, abDisStatePadding); 314 CHECK_PADDING3(HWACCMCPU, DisState, abDisStatePadding); 315 CHECK_PADDING3(IOMCPU, DisState, abDisStatePadding); 316 CHECK_PADDING3(PGMCPU, DisState, abDisStatePadding); 317 312 318 /* Make sure the set is large enough and has the correct size. */ 313 319 CHECK_SIZE(VMCPUSET, 32);
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