VirtualBox

Changeset 20530 in vbox for trunk/src/VBox


Ignore:
Timestamp:
Jun 13, 2009 8:53:44 PM (16 years ago)
Author:
vboxsync
Message:

VMM: remove DISCPUSTATE from the stack.

Location:
trunk/src/VBox/VMM
Files:
13 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/VMM/EMInternal.h

    r20426 r20530  
    347347    } u;
    348348
     349    /** For saving stack space, the disassembler state is allocated here instead of
     350     * on the stack.
     351     * @note The DISCPUSTATE structure is not R3/R0/RZ clean!  */
     352    union
     353    {
     354        /** The disassembler scratch space. */
     355        DISCPUSTATE         DisState;
     356        /** Padding. */
     357        uint8_t             abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
     358    };
     359
    349360    /** @name Execution profiling.
    350361     * @{ */
  • trunk/src/VBox/VMM/HWACCMInternal.h

    r20374 r20530  
    589589        unsigned            cPages;
    590590    } TlbShootdown;
     591
     592    /** For saving stack space, the disassembler state is allocated here instead of
     593     * on the stack.
     594     * @note The DISCPUSTATE structure is not R3/R0/RZ clean!  */
     595    union
     596    {
     597        /** The disassembler scratch space. */
     598        DISCPUSTATE         DisState;
     599        /** Padding. */
     600        uint8_t             abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
     601    };
    591602
    592603    RTUINT                  padding2[1];
  • trunk/src/VBox/VMM/IOMInternal.h

    r20374 r20530  
    402402
    403403
     404/**
     405 * IOM per virtual CPU instance data.
     406 */
     407typedef struct IOMCPU
     408{
     409    /** For saving stack space, the disassembler state is allocated here instead of
     410     * on the stack.
     411     * @note The DISCPUSTATE structure is not R3/R0/RZ clean!  */
     412    union
     413    {
     414        /** The disassembler scratch space. */
     415        DISCPUSTATE                 DisState;
     416        /** Padding. */
     417        uint8_t                     abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
     418    };
     419    uint8_t                         Dummy[16];
     420} IOMCPU;
     421/** Pointer to IOM per virtual CPU instance data. */
     422typedef IOMCPU *PIOMCPU;
     423
     424
    404425RT_C_DECLS_BEGIN
    405426
  • trunk/src/VBox/VMM/PGMInternal.h

    r20374 r20530  
    27022702    /** @} */
    27032703
     2704    /** For saving stack space, the disassembler state is allocated here instead of
     2705     * on the stack.
     2706     * @note The DISCPUSTATE structure is not R3/R0/RZ clean!  */
     2707    union
     2708    {
     2709        /** The disassembler scratch space. */
     2710        DISCPUSTATE                 DisState;
     2711        /** Padding. */
     2712        uint8_t                     abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
     2713    };
     2714
    27042715    /** @name Release Statistics
    27052716     * @{ */
  • trunk/src/VBox/VMM/VMMAll/EMAll.cpp

    r20461 r20530  
    7777*   Internal Functions                                                         *
    7878*******************************************************************************/
    79 DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
     79DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
    8080
    8181
     
    114114 * @param   pDest       HC destination pointer
    115115 * @param   cb          Number of bytes to read
    116  * @param   dwUserdata  Callback specific user data (pDISState)
     116 * @param   dwUserdata  Callback specific user data (pDis)
    117117 *
    118118 */
    119119DECLCALLBACK(int) EMReadBytes(RTUINTPTR pSrc, uint8_t *pDest, unsigned cb, void *pvUserdata)
    120120{
    121     DISCPUSTATE  *pDISState = (DISCPUSTATE *)pvUserdata;
    122     PEMDISSTATE   pState    = (PEMDISSTATE)pDISState->apvUserData[0];
    123     PVM           pVM       = pState->pVM;
    124     PVMCPU        pVCpu     = pState->pVCpu;
     121    PDISCPUSTATE  pDis   = (PDISCPUSTATE)pvUserdata;
     122    PEMDISSTATE   pState = (PEMDISSTATE)pDis->apvUserData[0];
     123    PVM           pVM    = pState->pVM;
     124    PVMCPU        pVCpu  = pState->pVCpu;
    125125
    126126# ifdef IN_RING0
     
    147147}
    148148
    149 DECLINLINE(int) emDisCoreOne(PVM pVM, PVMCPU pVCpu, DISCPUSTATE *pDISState, RTGCUINTPTR InstrGC, uint32_t *pOpsize)
     149DECLINLINE(int) emDisCoreOne(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, RTGCUINTPTR InstrGC, uint32_t *pOpsize)
    150150{
    151151    EMDISSTATE State;
     
    154154    State.pVCpu = pVCpu;
    155155
    156     return DISCoreOneEx(InstrGC, pDISState->mode, EMReadBytes, &State, pDISState, pOpsize);
     156    return DISCoreOneEx(InstrGC, pDis->mode, EMReadBytes, &State, pDis, pOpsize);
    157157}
    158158
    159159#else /* IN_RC */
    160160
    161 DECLINLINE(int) emDisCoreOne(PVM pVM, PVMCPU pVCpu, DISCPUSTATE *pDISState, RTGCUINTPTR InstrGC, uint32_t *pOpsize)
     161DECLINLINE(int) emDisCoreOne(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, RTGCUINTPTR InstrGC, uint32_t *pOpsize)
    162162{
    163163    NOREF(pVCpu);
    164164    NOREF(pVM);
    165     return DISCoreOne(pDISState, InstrGC, pOpsize);
     165    return DISCoreOne(pDis, InstrGC, pOpsize);
    166166}
    167167
     
    179179 * @param   pVCpu           The VMCPU handle.
    180180 * @param   pCtxCore        The context core (used for both the mode and instruction).
    181  * @param   pDISState       Where to return the parsed instruction info.
     181 * @param   pDis            Where to return the parsed instruction info.
    182182 * @param   pcbInstr        Where to return the instruction size. (optional)
    183183 */
    184 VMMDECL(int) EMInterpretDisasOne(PVM pVM, PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pDISState, unsigned *pcbInstr)
     184VMMDECL(int) EMInterpretDisasOne(PVM pVM, PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pDis, unsigned *pcbInstr)
    185185{
    186186    RTGCPTR GCPtrInstr;
     
    192192        return rc;
    193193    }
    194     return EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pDISState, pcbInstr);
     194    return EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pDis, pcbInstr);
    195195}
    196196
     
    208208 * @param   GCPtrInstr      The flat address of the instruction.
    209209 * @param   pCtxCore        The context core (used to determine the cpu mode).
    210  * @param   pDISState       Where to return the parsed instruction info.
     210 * @param   pDis            Where to return the parsed instruction info.
    211211 * @param   pcbInstr        Where to return the instruction size. (optional)
    212212 */
    213 VMMDECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pDISState, unsigned *pcbInstr)
     213VMMDECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pDis, unsigned *pcbInstr)
    214214{
    215215#ifndef IN_RC
     
    226226                          EMReadBytes, &State,
    227227#endif
    228                           pDISState, pcbInstr);
     228                          pDis, pcbInstr);
    229229    if (RT_SUCCESS(rc))
    230230        return VINF_SUCCESS;
     
    261261    if (RT_SUCCESS(rc))
    262262    {
    263         uint32_t    cbOp;
    264         DISCPUSTATE Cpu;
    265         Cpu.mode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
    266         rc = emDisCoreOne(pVM, pVCpu, &Cpu, (RTGCUINTPTR)pbCode, &cbOp);
     263        uint32_t     cbOp;
     264        PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
     265        pDis->mode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
     266        rc = emDisCoreOne(pVM, pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
    267267        if (RT_SUCCESS(rc))
    268268        {
    269             Assert(cbOp == Cpu.opsize);
    270             rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, pRegFrame, pvFault, pcbSize);
     269            Assert(cbOp == pDis->opsize);
     270            rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize);
    271271            if (RT_SUCCESS(rc))
    272272                pRegFrame->rip += cbOp; /* Move on to the next instruction. */
     
    293293 * @param   pVM         The VM handle.
    294294 * @param   pVCpu       The VMCPU handle.
    295  * @param   pDISState   The disassembler cpu state for the instruction to be interpreted.
     295 * @param   pDis        The disassembler cpu state for the instruction to be
     296 *                      interpreted.
    296297 * @param   pRegFrame   The register frame. EIP is *NOT* changed!
    297298 * @param   pvFault     The fault address (CR2).
     
    305306 *          Make sure this can't happen!! (will add some assertions/checks later)
    306307 */
    307 VMMDECL(int) EMInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     308VMMDECL(int) EMInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    308309{
    309310    STAM_PROFILE_START(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
    310     int rc = emInterpretInstructionCPU(pVM, pVCpu, pDISState, pRegFrame, pvFault, pcbSize);
     311    int rc = emInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize);
    311312    STAM_PROFILE_STOP(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
    312313    if (RT_SUCCESS(rc))
     
    325326 * @param   pVCpu       The VMCPU handle.
    326327 * @param   pCtxCore    The context core. This will be updated on successful return.
    327  * @param   pDISState   The instruction to interpret.
     328 * @param   pDis        The instruction to interpret.
    328329 * @param   cbOp        The size of the instruction.
    329330 * @remark  This may raise exceptions.
    330331 */
    331 VMMDECL(int) EMInterpretPortIO(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pDISState, uint32_t cbOp)
     332VMMDECL(int) EMInterpretPortIO(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pDis, uint32_t cbOp)
    332333{
    333334    /*
     
    335336     */
    336337#ifdef IN_RC
    337     int rc = IOMGCIOPortHandler(pVM, pCtxCore, pDISState);
     338    int rc = IOMGCIOPortHandler(pVM, pCtxCore, pDis);
    338339    if (IOM_SUCCESS(rc))
    339340        pCtxCore->rip += cbOp;
     
    381382
    382383/** Convert sel:addr to a flat GC address. */
    383 DECLINLINE(RTGCPTR) emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDISState, POP_PARAMETER pParam, RTGCPTR pvAddr)
    384 {
    385     DIS_SELREG enmPrefixSeg = DISDetectSegReg(pDISState, pParam);
     384DECLINLINE(RTGCPTR) emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, POP_PARAMETER pParam, RTGCPTR pvAddr)
     385{
     386    DIS_SELREG enmPrefixSeg = DISDetectSegReg(pDis, pParam);
    386387    return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
    387388}
     
    395396 * of limited space.
    396397 */
    397 static const char *emGetMnemonic(PDISCPUSTATE pDISState)
    398 {
    399     switch (pDISState->pCurInstr->opcode)
     398static const char *emGetMnemonic(PDISCPUSTATE pDis)
     399{
     400    switch (pDis->pCurInstr->opcode)
    400401    {
    401402        case OP_XCHG:       return "Xchg";
     
    437438        case OP_LMSW:       return "Lmsw";
    438439        case OP_SMSW:       return "Smsw";
    439         case OP_CMPXCHG:    return pDISState->prefix & PREFIX_LOCK ? "Lock CmpXchg"   : "CmpXchg";
    440         case OP_CMPXCHG8B:  return pDISState->prefix & PREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b";
     440        case OP_CMPXCHG:    return pDis->prefix & PREFIX_LOCK ? "Lock CmpXchg"   : "CmpXchg";
     441        case OP_CMPXCHG8B:  return pDis->prefix & PREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b";
    441442
    442443        default:
    443             Log(("Unknown opcode %d\n", pDISState->pCurInstr->opcode));
     444            Log(("Unknown opcode %d\n", pDis->pCurInstr->opcode));
    444445            return "???";
    445446    }
     
    451452 * XCHG instruction emulation.
    452453 */
    453 static int emInterpretXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     454static int emInterpretXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    454455{
    455456    OP_PARAMVAL param1, param2;
    456457
    457458    /* Source to make DISQueryParamVal read the register value - ugly hack */
    458     int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_SOURCE);
     459    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
    459460    if(RT_FAILURE(rc))
    460461        return VERR_EM_INTERPRETER;
    461462
    462     rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param2, &param2, PARAM_SOURCE);
     463    rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, PARAM_SOURCE);
    463464    if(RT_FAILURE(rc))
    464465        return VERR_EM_INTERPRETER;
     
    473474            uint64_t valpar1, valpar2;
    474475
    475             AssertReturn(pDISState->param1.size == pDISState->param2.size, VERR_EM_INTERPRETER);
     476            AssertReturn(pDis->param1.size == pDis->param2.size, VERR_EM_INTERPRETER);
    476477            switch(param1.type)
    477478            {
     
    482483            case PARMTYPE_ADDRESS:
    483484                pParam1 = (RTGCPTR)param1.val.val64;
    484                 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, pParam1);
     485                pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1);
    485486                EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
    486487                rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
     
    501502            case PARMTYPE_ADDRESS:
    502503                pParam2 = (RTGCPTR)param2.val.val64;
    503                 pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param2, pParam2);
     504                pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param2, pParam2);
    504505                EM_ASSERT_FAULT_RETURN(pParam2 == pvFault, VERR_EM_INTERPRETER);
    505506                rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar2, pParam2, param2.size);
     
    526527                {
    527528                case 1: //special case for AH etc
    528                         rc = DISWriteReg8(pRegFrame, pDISState->param1.base.reg_gen,  (uint8_t )valpar2); break;
    529                 case 2: rc = DISWriteReg16(pRegFrame, pDISState->param1.base.reg_gen, (uint16_t)valpar2); break;
    530                 case 4: rc = DISWriteReg32(pRegFrame, pDISState->param1.base.reg_gen, (uint32_t)valpar2); break;
    531                 case 8: rc = DISWriteReg64(pRegFrame, pDISState->param1.base.reg_gen, valpar2); break;
     529                        rc = DISWriteReg8(pRegFrame, pDis->param1.base.reg_gen,  (uint8_t )valpar2); break;
     530                case 2: rc = DISWriteReg16(pRegFrame, pDis->param1.base.reg_gen, (uint16_t)valpar2); break;
     531                case 4: rc = DISWriteReg32(pRegFrame, pDis->param1.base.reg_gen, (uint32_t)valpar2); break;
     532                case 8: rc = DISWriteReg64(pRegFrame, pDis->param1.base.reg_gen, valpar2); break;
    532533                default: AssertFailedReturn(VERR_EM_INTERPRETER);
    533534                }
     
    552553                {
    553554                case 1: //special case for AH etc
    554                         rc = DISWriteReg8(pRegFrame, pDISState->param2.base.reg_gen,  (uint8_t )valpar1);    break;
    555                 case 2: rc = DISWriteReg16(pRegFrame, pDISState->param2.base.reg_gen, (uint16_t)valpar1);    break;
    556                 case 4: rc = DISWriteReg32(pRegFrame, pDISState->param2.base.reg_gen, (uint32_t)valpar1);    break;
    557                 case 8: rc = DISWriteReg64(pRegFrame, pDISState->param2.base.reg_gen, valpar1);              break;
     555                        rc = DISWriteReg8(pRegFrame, pDis->param2.base.reg_gen,  (uint8_t )valpar1);    break;
     556                case 2: rc = DISWriteReg16(pRegFrame, pDis->param2.base.reg_gen, (uint16_t)valpar1);    break;
     557                case 4: rc = DISWriteReg32(pRegFrame, pDis->param2.base.reg_gen, (uint32_t)valpar1);    break;
     558                case 8: rc = DISWriteReg64(pRegFrame, pDis->param2.base.reg_gen, valpar1);              break;
    558559                default: AssertFailedReturn(VERR_EM_INTERPRETER);
    559560                }
     
    584585 * INC and DEC emulation.
    585586 */
    586 static int emInterpretIncDec(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
     587static int emInterpretIncDec(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
    587588                             PFNEMULATEPARAM2 pfnEmulate)
    588589{
    589590    OP_PARAMVAL param1;
    590591
    591     int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_DEST);
     592    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_DEST);
    592593    if(RT_FAILURE(rc))
    593594        return VERR_EM_INTERPRETER;
     
    605606            {
    606607                pParam1 = (RTGCPTR)param1.val.val64;
    607                 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, pParam1);
     608                pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1);
    608609#ifdef IN_RC
    609610                /* Safety check (in theory it could cross a page boundary and fault there though) */
     
    653654 * POP Emulation.
    654655 */
    655 static int emInterpretPop(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    656 {
    657     Assert(pDISState->mode != CPUMODE_64BIT);    /** @todo check */
     656static int emInterpretPop(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     657{
     658    Assert(pDis->mode != CPUMODE_64BIT);    /** @todo check */
    658659    OP_PARAMVAL param1;
    659     int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_DEST);
     660    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_DEST);
    660661    if(RT_FAILURE(rc))
    661662        return VERR_EM_INTERPRETER;
     
    693694                /* pop [esp+xx] uses esp after the actual pop! */
    694695                AssertCompile(USE_REG_ESP == USE_REG_SP);
    695                 if (    (pDISState->param1.flags & USE_BASE)
    696                     &&  (pDISState->param1.flags & (USE_REG_GEN16|USE_REG_GEN32))
    697                     &&  pDISState->param1.base.reg_gen == USE_REG_ESP
     696                if (    (pDis->param1.flags & USE_BASE)
     697                    &&  (pDis->param1.flags & (USE_REG_GEN16|USE_REG_GEN32))
     698                    &&  pDis->param1.base.reg_gen == USE_REG_ESP
    698699                   )
    699700                   pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
    700701
    701                 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, pParam1);
     702                pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1);
    702703                EM_ASSERT_FAULT_RETURN(pParam1 == pvFault || (RTGCPTR)pRegFrame->esp == pvFault, VERR_EM_INTERPRETER);
    703704                rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
     
    733734 * XOR/OR/AND Emulation.
    734735 */
    735 static int emInterpretOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
     736static int emInterpretOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
    736737                               PFNEMULATEPARAM3 pfnEmulate)
    737738{
    738739    OP_PARAMVAL param1, param2;
    739740
    740     int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_DEST);
     741    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_DEST);
    741742    if(RT_FAILURE(rc))
    742743        return VERR_EM_INTERPRETER;
    743744
    744     rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param2, &param2, PARAM_SOURCE);
     745    rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, PARAM_SOURCE);
    745746    if(RT_FAILURE(rc))
    746747        return VERR_EM_INTERPRETER;
     
    755756            uint64_t valpar1, valpar2;
    756757
    757             if (pDISState->param1.size != pDISState->param2.size)
    758             {
    759                 if (pDISState->param1.size < pDISState->param2.size)
     758            if (pDis->param1.size != pDis->param2.size)
     759            {
     760                if (pDis->param1.size < pDis->param2.size)
    760761                {
    761                     AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDISState), (RTGCPTR)pRegFrame->rip, pDISState->param1.size, pDISState->param2.size)); /* should never happen! */
     762                    AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->param1.size, pDis->param2.size)); /* should never happen! */
    762763                    return VERR_EM_INTERPRETER;
    763764                }
    764765                /* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
    765                 pDISState->param2.size = pDISState->param1.size;
     766                pDis->param2.size = pDis->param1.size;
    766767                param2.size     = param1.size;
    767768            }
     
    771772            {
    772773                pParam1 = (RTGCPTR)param1.val.val64;
    773                 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, pParam1);
     774                pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1);
    774775                EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
    775776                rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
     
    798799            }
    799800
    800             LogFlow(("emInterpretOrXorAnd %s %RGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pDISState), pParam1, valpar1, valpar2, param2.size, param1.size));
     801            LogFlow(("emInterpretOrXorAnd %s %RGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pDis), pParam1, valpar1, valpar2, param2.size, param1.size));
    801802
    802803            /* Data read, emulate instruction. */
    803804            uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
    804805
    805             LogFlow(("emInterpretOrXorAnd %s result %RX64\n", emGetMnemonic(pDISState), valpar1));
     806            LogFlow(("emInterpretOrXorAnd %s result %RX64\n", emGetMnemonic(pDis), valpar1));
    806807
    807808            /* Update guest's eflags and finish. */
     
    828829 * LOCK XOR/OR/AND Emulation.
    829830 */
    830 static int emInterpretLockOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
     831static int emInterpretLockOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
    831832                                   uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
    832833{
     
    835836
    836837#if HC_ARCH_BITS == 32
    837     Assert(pDISState->param1.size <= 4);
    838 #endif
    839 
    840     int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_DEST);
     838    Assert(pDis->param1.size <= 4);
     839#endif
     840
     841    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_DEST);
    841842    if(RT_FAILURE(rc))
    842843        return VERR_EM_INTERPRETER;
    843844
    844     rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param2, &param2, PARAM_SOURCE);
     845    rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, PARAM_SOURCE);
    845846    if(RT_FAILURE(rc))
    846847        return VERR_EM_INTERPRETER;
    847848
    848     if (pDISState->param1.size != pDISState->param2.size)
    849     {
    850         AssertMsgReturn(pDISState->param1.size >= pDISState->param2.size, /* should never happen! */
    851                         ("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDISState), (RTGCPTR)pRegFrame->rip, pDISState->param1.size, pDISState->param2.size),
     849    if (pDis->param1.size != pDis->param2.size)
     850    {
     851        AssertMsgReturn(pDis->param1.size >= pDis->param2.size, /* should never happen! */
     852                        ("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->param1.size, pDis->param2.size),
    852853                        VERR_EM_INTERPRETER);
    853854
    854855        /* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
    855         pDISState->param2.size = pDISState->param1.size;
     856        pDis->param2.size = pDis->param1.size;
    856857        param2.size       = param1.size;
    857858    }
     
    872873
    873874    RTGCPTR GCPtrPar1 = param1.val.val64;
    874     GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, GCPtrPar1);
     875    GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, GCPtrPar1);
    875876#ifdef IN_RC
    876877    pvParam1  = (void *)GCPtrPar1;
     
    882883
    883884    /* Try emulate it with a one-shot #PF handler in place. (RC) */
    884     Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pDISState), GCPtrPar1, pDISState->param2.size*8, ValPar2));
     885    Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pDis), GCPtrPar1, pDis->param2.size*8, ValPar2));
    885886
    886887    RTGCUINTREG32 eflags = 0;
     
    888889    MMGCRamRegisterTrapHandler(pVM);
    889890#endif
    890     rc = pfnEmulate(pvParam1, ValPar2, pDISState->param2.size, &eflags);
     891    rc = pfnEmulate(pvParam1, ValPar2, pDis->param2.size, &eflags);
    891892#ifdef IN_RC
    892893    MMGCRamDeregisterTrapHandler(pVM);
     
    896897    if (RT_FAILURE(rc))
    897898    {
    898         Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pDISState), GCPtrPar1, pDISState->param2.size*8, ValPar2));
     899        Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pDis), GCPtrPar1, pDis->param2.size*8, ValPar2));
    899900        return VERR_EM_INTERPRETER;
    900901    }
     
    912913 * ADD, ADC & SUB Emulation.
    913914 */
    914 static int emInterpretAddSub(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
     915static int emInterpretAddSub(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
    915916                             PFNEMULATEPARAM3 pfnEmulate)
    916917{
    917918    OP_PARAMVAL param1, param2;
    918     int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_DEST);
     919    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_DEST);
    919920    if(RT_FAILURE(rc))
    920921        return VERR_EM_INTERPRETER;
    921922
    922     rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param2, &param2, PARAM_SOURCE);
     923    rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, PARAM_SOURCE);
    923924    if(RT_FAILURE(rc))
    924925        return VERR_EM_INTERPRETER;
     
    933934            uint64_t valpar1, valpar2;
    934935
    935             if (pDISState->param1.size != pDISState->param2.size)
    936             {
    937                 if (pDISState->param1.size < pDISState->param2.size)
     936            if (pDis->param1.size != pDis->param2.size)
     937            {
     938                if (pDis->param1.size < pDis->param2.size)
    938939                {
    939                     AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDISState), (RTGCPTR)pRegFrame->rip, pDISState->param1.size, pDISState->param2.size)); /* should never happen! */
     940                    AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->param1.size, pDis->param2.size)); /* should never happen! */
    940941                    return VERR_EM_INTERPRETER;
    941942                }
    942943                /* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
    943                 pDISState->param2.size = pDISState->param1.size;
     944                pDis->param2.size = pDis->param1.size;
    944945                param2.size     = param1.size;
    945946            }
     
    949950            {
    950951                pParam1 = (RTGCPTR)param1.val.val64;
    951                 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, pParam1);
     952                pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1);
    952953                EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
    953954                rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
     
    10041005 * ADC Emulation.
    10051006 */
    1006 static int emInterpretAdc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     1007static int emInterpretAdc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    10071008{
    10081009    if (pRegFrame->eflags.Bits.u1CF)
    1009         return emInterpretAddSub(pVM, pVCpu, pDISState, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
     1010        return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
    10101011    else
    1011         return emInterpretAddSub(pVM, pVCpu, pDISState, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
     1012        return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
    10121013}
    10131014
     
    10161017 * BTR/C/S Emulation.
    10171018 */
    1018 static int emInterpretBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
     1019static int emInterpretBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
    10191020                              PFNEMULATEPARAM2UINT32 pfnEmulate)
    10201021{
    10211022    OP_PARAMVAL param1, param2;
    1022     int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_DEST);
     1023    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_DEST);
    10231024    if(RT_FAILURE(rc))
    10241025        return VERR_EM_INTERPRETER;
    10251026
    1026     rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param2, &param2, PARAM_SOURCE);
     1027    rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, PARAM_SOURCE);
    10271028    if(RT_FAILURE(rc))
    10281029        return VERR_EM_INTERPRETER;
     
    10431044
    10441045            pParam1 = (RTGCPTR)param1.val.val64;
    1045             pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, pParam1);
     1046            pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1);
    10461047
    10471048            /* Register or immediate data */
     
    10571058            }
    10581059
    1059             Log2(("emInterpret%s: pvFault=%RGv pParam1=%RGv val2=%x\n", emGetMnemonic(pDISState), pvFault, pParam1, valpar2));
     1060            Log2(("emInterpret%s: pvFault=%RGv pParam1=%RGv val2=%x\n", emGetMnemonic(pDis), pvFault, pParam1, valpar2));
    10601061            pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
    10611062            EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, VERR_EM_INTERPRETER);
     
    10961097 * LOCK BTR/C/S Emulation.
    10971098 */
    1098 static int emInterpretLockBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
     1099static int emInterpretLockBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
    10991100                                  uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
    11001101{
     
    11021103
    11031104    OP_PARAMVAL param1, param2;
    1104     int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_DEST);
     1105    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_DEST);
    11051106    if(RT_FAILURE(rc))
    11061107        return VERR_EM_INTERPRETER;
    11071108
    1108     rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param2, &param2, PARAM_SOURCE);
     1109    rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, PARAM_SOURCE);
    11091110    if(RT_FAILURE(rc))
    11101111        return VERR_EM_INTERPRETER;
     
    11231124    ValPar2 &= 7;
    11241125
    1125     GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, GCPtrPar1);
     1126    GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, GCPtrPar1);
    11261127#ifdef IN_RC
    11271128    Assert(TRPMHasTrap(pVCpu));
     
    11371138#endif
    11381139
    1139     Log2(("emInterpretLockBitTest %s: pvFault=%RGv GCPtrPar1=%RGv imm=%RX64\n", emGetMnemonic(pDISState), pvFault, GCPtrPar1, ValPar2));
     1140    Log2(("emInterpretLockBitTest %s: pvFault=%RGv GCPtrPar1=%RGv imm=%RX64\n", emGetMnemonic(pDis), pvFault, GCPtrPar1, ValPar2));
    11401141
    11411142    /* Try emulate it with a one-shot #PF handler in place. (RC) */
     
    11531154    {
    11541155        Log(("emInterpretLockBitTest %s: %RGv imm%d=%RX64 -> emulation failed due to page fault!\n",
    1155              emGetMnemonic(pDISState), GCPtrPar1, pDISState->param2.size*8, ValPar2));
    1156         return VERR_EM_INTERPRETER;
    1157     }
    1158 
    1159     Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%RX64 CF=%d\n", emGetMnemonic(pDISState), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
     1156             emGetMnemonic(pDis), GCPtrPar1, pDis->param2.size*8, ValPar2));
     1157        return VERR_EM_INTERPRETER;
     1158    }
     1159
     1160    Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%RX64 CF=%d\n", emGetMnemonic(pDis), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
    11601161
    11611162    /* Update guest's eflags and finish. */
     
    11711172 * MOV emulation.
    11721173 */
    1173 static int emInterpretMov(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     1174static int emInterpretMov(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    11741175{
    11751176    OP_PARAMVAL param1, param2;
    1176     int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_DEST);
     1177    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_DEST);
    11771178    if(RT_FAILURE(rc))
    11781179        return VERR_EM_INTERPRETER;
    11791180
    1180     rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param2, &param2, PARAM_SOURCE);
     1181    rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, PARAM_SOURCE);
    11811182    if(RT_FAILURE(rc))
    11821183        return VERR_EM_INTERPRETER;
     
    12041205            case PARMTYPE_ADDRESS:
    12051206                pDest = (RTGCPTR)param1.val.val64;
    1206                 pDest = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, pDest);
     1207                pDest = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pDest);
    12071208                break;
    12081209
     
    12231224            }
    12241225#ifdef LOG_ENABLED
    1225             if (pDISState->mode == CPUMODE_64BIT)
     1226            if (pDis->mode == CPUMODE_64BIT)
    12261227                LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64));
    12271228            else
     
    12521253            case PARMTYPE_ADDRESS:
    12531254                pSrc = (RTGCPTR)param2.val.val64;
    1254                 pSrc = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param2, pSrc);
     1255                pSrc = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param2, pSrc);
    12551256                break;
    12561257
     
    12711272                switch(param1.size)
    12721273                {
    1273                 case 1: rc = DISWriteReg8(pRegFrame, pDISState->param1.base.reg_gen,  (uint8_t) val64); break;
    1274                 case 2: rc = DISWriteReg16(pRegFrame, pDISState->param1.base.reg_gen, (uint16_t)val64); break;
    1275                 case 4: rc = DISWriteReg32(pRegFrame, pDISState->param1.base.reg_gen, (uint32_t)val64); break;
    1276                 case 8: rc = DISWriteReg64(pRegFrame, pDISState->param1.base.reg_gen, val64); break;
     1274                case 1: rc = DISWriteReg8(pRegFrame, pDis->param1.base.reg_gen,  (uint8_t) val64); break;
     1275                case 2: rc = DISWriteReg16(pRegFrame, pDis->param1.base.reg_gen, (uint16_t)val64); break;
     1276                case 4: rc = DISWriteReg32(pRegFrame, pDis->param1.base.reg_gen, (uint32_t)val64); break;
     1277                case 8: rc = DISWriteReg64(pRegFrame, pDis->param1.base.reg_gen, val64); break;
    12771278                default:
    12781279                    return VERR_EM_INTERPRETER;
     
    12861287            }
    12871288#ifdef LOG_ENABLED
    1288             if (pDISState->mode == CPUMODE_64BIT)
     1289            if (pDis->mode == CPUMODE_64BIT)
    12891290                LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
    12901291            else
     
    13041305 * [REP] STOSWD emulation
    13051306 */
    1306 static int emInterpretStosWD(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     1307static int emInterpretStosWD(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    13071308{
    13081309    int      rc;
     
    13131314
    13141315    /* Don't support any but these three prefix bytes. */
    1315     if ((pDISState->prefix & ~(PREFIX_ADDRSIZE|PREFIX_OPSIZE|PREFIX_REP|PREFIX_REX)))
    1316         return VERR_EM_INTERPRETER;
    1317 
    1318     switch (pDISState->addrmode)
     1316    if ((pDis->prefix & ~(PREFIX_ADDRSIZE|PREFIX_OPSIZE|PREFIX_REP|PREFIX_REX)))
     1317        return VERR_EM_INTERPRETER;
     1318
     1319    switch (pDis->addrmode)
    13191320    {
    13201321    case CPUMODE_16BIT:
     
    13361337
    13371338    GCDest = SELMToFlat(pVM, DIS_SELREG_ES, pRegFrame, GCOffset);
    1338     switch (pDISState->opmode)
     1339    switch (pDis->opmode)
    13391340    {
    13401341    case CPUMODE_16BIT:
     
    13541355    offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
    13551356
    1356     if (!(pDISState->prefix & PREFIX_REP))
     1357    if (!(pDis->prefix & PREFIX_REP))
    13571358    {
    13581359        LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize));
     
    13641365
    13651366        /* Update (e/r)di. */
    1366         switch (pDISState->addrmode)
     1367        switch (pDis->addrmode)
    13671368        {
    13681369        case CPUMODE_16BIT:
     
    14291430
    14301431        /* Update the registers. */
    1431         switch (pDISState->addrmode)
     1432        switch (pDis->addrmode)
    14321433        {
    14331434        case CPUMODE_16BIT:
     
    14591460 * [LOCK] CMPXCHG emulation.
    14601461 */
    1461 static int emInterpretCmpXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     1462static int emInterpretCmpXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    14621463{
    14631464    OP_PARAMVAL param1, param2;
    14641465
    14651466#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0)
    1466     Assert(pDISState->param1.size <= 4);
     1467    Assert(pDis->param1.size <= 4);
    14671468#endif
    14681469
    14691470    /* Source to make DISQueryParamVal read the register value - ugly hack */
    1470     int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_SOURCE);
     1471    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
    14711472    if(RT_FAILURE(rc))
    14721473        return VERR_EM_INTERPRETER;
    14731474
    1474     rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param2, &param2, PARAM_SOURCE);
     1475    rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, PARAM_SOURCE);
    14751476    if(RT_FAILURE(rc))
    14761477        return VERR_EM_INTERPRETER;
     
    14921493    uint64_t eflags;
    14931494
    1494     AssertReturn(pDISState->param1.size == pDISState->param2.size, VERR_EM_INTERPRETER);
     1495    AssertReturn(pDis->param1.size == pDis->param2.size, VERR_EM_INTERPRETER);
    14951496    switch(param1.type)
    14961497    {
    14971498    case PARMTYPE_ADDRESS:
    14981499        GCPtrPar1 = param1.val.val64;
    1499         GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, GCPtrPar1);
     1500        GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, GCPtrPar1);
    15001501
    15011502        rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
     
    15071508    }
    15081509
    1509     LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pDISState), GCPtrPar1, pRegFrame->rax, valpar));
    1510 
    1511     if (pDISState->prefix & PREFIX_LOCK)
    1512         eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDISState->param2.size);
     1510    LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar));
     1511
     1512    if (pDis->prefix & PREFIX_LOCK)
     1513        eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->param2.size);
    15131514    else
    1514         eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDISState->param2.size);
    1515 
    1516     LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pDISState), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
     1515        eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->param2.size);
     1516
     1517    LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
    15171518
    15181519    /* Update guest's eflags and finish. */
     
    15291530 * [LOCK] CMPXCHG8B emulation.
    15301531 */
    1531 static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    1532 {
    1533     Assert(pDISState->mode != CPUMODE_64BIT);    /** @todo check */
     1532static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     1533{
     1534    Assert(pDis->mode != CPUMODE_64BIT);    /** @todo check */
    15341535    OP_PARAMVAL param1;
    15351536
    15361537    /* Source to make DISQueryParamVal read the register value - ugly hack */
    1537     int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_SOURCE);
     1538    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
    15381539    if(RT_FAILURE(rc))
    15391540        return VERR_EM_INTERPRETER;
     
    15441545    PGMPAGEMAPLOCK Lock;
    15451546
    1546     AssertReturn(pDISState->param1.size == 8, VERR_EM_INTERPRETER);
     1547    AssertReturn(pDis->param1.size == 8, VERR_EM_INTERPRETER);
    15471548    switch(param1.type)
    15481549    {
    15491550    case PARMTYPE_ADDRESS:
    15501551        GCPtrPar1 = param1.val.val64;
    1551         GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, GCPtrPar1);
     1552        GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, GCPtrPar1);
    15521553
    15531554        rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
     
    15591560    }
    15601561
    1561     LogFlow(("%s %RGv=%08x eax=%08x\n", emGetMnemonic(pDISState), pvParam1, pRegFrame->eax));
    1562 
    1563     if (pDISState->prefix & PREFIX_LOCK)
     1562    LogFlow(("%s %RGv=%08x eax=%08x\n", emGetMnemonic(pDis), pvParam1, pRegFrame->eax));
     1563
     1564    if (pDis->prefix & PREFIX_LOCK)
    15641565        eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
    15651566    else
    15661567        eflags = EMEmulateCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
    15671568
    1568     LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pDISState), pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
     1569    LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pDis), pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
    15691570
    15701571    /* Update guest's eflags and finish; note that *only* ZF is affected. */
     
    15821583 * [LOCK] CMPXCHG emulation.
    15831584 */
    1584 static int emInterpretCmpXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    1585 {
    1586     Assert(pDISState->mode != CPUMODE_64BIT);    /** @todo check */
     1585static int emInterpretCmpXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     1586{
     1587    Assert(pDis->mode != CPUMODE_64BIT);    /** @todo check */
    15871588    OP_PARAMVAL param1, param2;
    15881589
    15891590    /* Source to make DISQueryParamVal read the register value - ugly hack */
    1590     int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_SOURCE);
     1591    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
    15911592    if(RT_FAILURE(rc))
    15921593        return VERR_EM_INTERPRETER;
    15931594
    1594     rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param2, &param2, PARAM_SOURCE);
     1595    rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, PARAM_SOURCE);
    15951596    if(RT_FAILURE(rc))
    15961597        return VERR_EM_INTERPRETER;
     
    16031604            uint32_t valpar, eflags;
    16041605
    1605             AssertReturn(pDISState->param1.size == pDISState->param2.size, VERR_EM_INTERPRETER);
     1606            AssertReturn(pDis->param1.size == pDis->param2.size, VERR_EM_INTERPRETER);
    16061607            switch(param1.type)
    16071608            {
    16081609            case PARMTYPE_ADDRESS:
    16091610                pParam1 = (RTRCPTR)param1.val.val64;
    1610                 pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
     1611                pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
    16111612                EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
    16121613                break;
     
    16261627            }
    16271628
    1628             LogFlow(("%s %RRv eax=%08x %08x\n", emGetMnemonic(pDISState), pParam1, pRegFrame->eax, valpar));
     1629            LogFlow(("%s %RRv eax=%08x %08x\n", emGetMnemonic(pDis), pParam1, pRegFrame->eax, valpar));
    16291630
    16301631            MMGCRamRegisterTrapHandler(pVM);
    1631             if (pDISState->prefix & PREFIX_LOCK)
    1632                 rc = EMGCEmulateLockCmpXchg(pParam1, &pRegFrame->eax, valpar, pDISState->param2.size, &eflags);
     1632            if (pDis->prefix & PREFIX_LOCK)
     1633                rc = EMGCEmulateLockCmpXchg(pParam1, &pRegFrame->eax, valpar, pDis->param2.size, &eflags);
    16331634            else
    1634                 rc = EMGCEmulateCmpXchg(pParam1, &pRegFrame->eax, valpar, pDISState->param2.size, &eflags);
     1635                rc = EMGCEmulateCmpXchg(pParam1, &pRegFrame->eax, valpar, pDis->param2.size, &eflags);
    16351636            MMGCRamDeregisterTrapHandler(pVM);
    16361637
    16371638            if (RT_FAILURE(rc))
    16381639            {
    1639                 Log(("%s %RGv eax=%08x %08x -> emulation failed due to page fault!\n", emGetMnemonic(pDISState), pParam1, pRegFrame->eax, valpar));
     1640                Log(("%s %RGv eax=%08x %08x -> emulation failed due to page fault!\n", emGetMnemonic(pDis), pParam1, pRegFrame->eax, valpar));
    16401641                return VERR_EM_INTERPRETER;
    16411642            }
    16421643
    1643             LogFlow(("%s %RRv eax=%08x %08x ZF=%d\n", emGetMnemonic(pDISState), pParam1, pRegFrame->eax, valpar, !!(eflags & X86_EFL_ZF)));
     1644            LogFlow(("%s %RRv eax=%08x %08x ZF=%d\n", emGetMnemonic(pDis), pParam1, pRegFrame->eax, valpar, !!(eflags & X86_EFL_ZF)));
    16441645
    16451646            /* Update guest's eflags and finish. */
     
    16581659 * [LOCK] CMPXCHG8B emulation.
    16591660 */
    1660 static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    1661 {
    1662     Assert(pDISState->mode != CPUMODE_64BIT);    /** @todo check */
     1661static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     1662{
     1663    Assert(pDis->mode != CPUMODE_64BIT);    /** @todo check */
    16631664    OP_PARAMVAL param1;
    16641665
    16651666    /* Source to make DISQueryParamVal read the register value - ugly hack */
    1666     int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_SOURCE);
     1667    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
    16671668    if(RT_FAILURE(rc))
    16681669        return VERR_EM_INTERPRETER;
     
    16751676            uint32_t eflags;
    16761677
    1677             AssertReturn(pDISState->param1.size == 8, VERR_EM_INTERPRETER);
     1678            AssertReturn(pDis->param1.size == 8, VERR_EM_INTERPRETER);
    16781679            switch(param1.type)
    16791680            {
    16801681            case PARMTYPE_ADDRESS:
    16811682                pParam1 = (RTRCPTR)param1.val.val64;
    1682                 pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
     1683                pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
    16831684                EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
    16841685                break;
     
    16881689            }
    16891690
    1690             LogFlow(("%s %RRv=%08x eax=%08x\n", emGetMnemonic(pDISState), pParam1, pRegFrame->eax));
     1691            LogFlow(("%s %RRv=%08x eax=%08x\n", emGetMnemonic(pDis), pParam1, pRegFrame->eax));
    16911692
    16921693            MMGCRamRegisterTrapHandler(pVM);
    1693             if (pDISState->prefix & PREFIX_LOCK)
     1694            if (pDis->prefix & PREFIX_LOCK)
    16941695                rc = EMGCEmulateLockCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
    16951696            else
     
    16991700            if (RT_FAILURE(rc))
    17001701            {
    1701                 Log(("%s %RGv=%08x eax=%08x -> emulation failed due to page fault!\n", emGetMnemonic(pDISState), pParam1, pRegFrame->eax));
     1702                Log(("%s %RGv=%08x eax=%08x -> emulation failed due to page fault!\n", emGetMnemonic(pDis), pParam1, pRegFrame->eax));
    17021703                return VERR_EM_INTERPRETER;
    17031704            }
    17041705
    1705             LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pDISState), pParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
     1706            LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pDis), pParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
    17061707
    17071708            /* Update guest's eflags and finish; note that *only* ZF is affected. */
     
    17221723 * [LOCK] XADD emulation.
    17231724 */
    1724 static int emInterpretXAdd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    1725 {
    1726     Assert(pDISState->mode != CPUMODE_64BIT);    /** @todo check */
     1725static int emInterpretXAdd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     1726{
     1727    Assert(pDis->mode != CPUMODE_64BIT);    /** @todo check */
    17271728    OP_PARAMVAL param1;
    17281729    uint32_t *pParamReg2;
     
    17301731
    17311732    /* Source to make DISQueryParamVal read the register value - ugly hack */
    1732     int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_SOURCE);
     1733    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
    17331734    if(RT_FAILURE(rc))
    17341735        return VERR_EM_INTERPRETER;
    17351736
    1736     rc = DISQueryParamRegPtr(pRegFrame, pDISState, &pDISState->param2, (void **)&pParamReg2, &cbSizeParamReg2);
     1737    rc = DISQueryParamRegPtr(pRegFrame, pDis, &pDis->param2, (void **)&pParamReg2, &cbSizeParamReg2);
    17371738    Assert(cbSizeParamReg2 <= 4);
    17381739    if(RT_FAILURE(rc))
     
    17461747            uint32_t eflags;
    17471748
    1748             AssertReturn(pDISState->param1.size == pDISState->param2.size, VERR_EM_INTERPRETER);
     1749            AssertReturn(pDis->param1.size == pDis->param2.size, VERR_EM_INTERPRETER);
    17491750            switch(param1.type)
    17501751            {
    17511752            case PARMTYPE_ADDRESS:
    17521753                pParam1 = (RTRCPTR)param1.val.val64;
    1753                 pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
     1754                pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
    17541755                EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
    17551756                break;
     
    17621763
    17631764            MMGCRamRegisterTrapHandler(pVM);
    1764             if (pDISState->prefix & PREFIX_LOCK)
     1765            if (pDis->prefix & PREFIX_LOCK)
    17651766                rc = EMGCEmulateLockXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
    17661767            else
     
    18481849 * IRET Emulation.
    18491850 */
    1850 static int emInterpretIret(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     1851static int emInterpretIret(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    18511852{
    18521853    /* only allow direct calls to EMInterpretIret for now */
     
    18571858 * WBINVD Emulation.
    18581859 */
    1859 static int emInterpretWbInvd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     1860static int emInterpretWbInvd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    18601861{
    18611862    /* Nothing to do. */
     
    18981899 * INVLPG Emulation.
    18991900 */
    1900 static int emInterpretInvlPg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     1901static int emInterpretInvlPg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    19011902{
    19021903    OP_PARAMVAL param1;
    19031904    RTGCPTR     addr;
    19041905
    1905     int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_SOURCE);
     1906    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
    19061907    if(RT_FAILURE(rc))
    19071908        return VERR_EM_INTERPRETER;
     
    19661967 * CPUID Emulation.
    19671968 */
    1968 static int emInterpretCpuId(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     1969static int emInterpretCpuId(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    19691970{
    19701971    int rc = EMInterpretCpuId(pVM, pVCpu, pRegFrame);
     
    20352036 * CLTS Emulation.
    20362037 */
    2037 static int emInterpretClts(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     2038static int emInterpretClts(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    20382039{
    20392040    return EMInterpretCLTS(pVM, pVCpu);
     
    22362237 * LMSW Emulation.
    22372238 */
    2238 static int emInterpretLmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     2239static int emInterpretLmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    22392240{
    22402241    OP_PARAMVAL param1;
    22412242    uint32_t    val;
    22422243
    2243     int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_SOURCE);
     2244    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
    22442245    if(RT_FAILURE(rc))
    22452246        return VERR_EM_INTERPRETER;
     
    22662267 * SMSW Emulation.
    22672268 */
    2268 static int emInterpretSmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     2269static int emInterpretSmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    22692270{
    22702271    OP_PARAMVAL param1;
    22712272    uint64_t    cr0 = CPUMGetGuestCR0(pVCpu);
    22722273
    2273     int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_SOURCE);
     2274    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
    22742275    if(RT_FAILURE(rc))
    22752276        return VERR_EM_INTERPRETER;
     
    22802281        if(param1.size != sizeof(uint16_t))
    22812282            return VERR_EM_INTERPRETER;
    2282         LogFlow(("emInterpretSmsw %d <- cr0 (%x)\n", pDISState->param1.base.reg_gen, cr0));
    2283         rc = DISWriteReg16(pRegFrame, pDISState->param1.base.reg_gen, cr0);
     2283        LogFlow(("emInterpretSmsw %d <- cr0 (%x)\n", pDis->param1.base.reg_gen, cr0));
     2284        rc = DISWriteReg16(pRegFrame, pDis->param1.base.reg_gen, cr0);
    22842285        break;
    22852286
     
    22932294
    22942295        pParam1 = (RTGCPTR)param1.val.val64;
    2295         pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, pParam1);
     2296        pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1);
    22962297        LogFlow(("emInterpretSmsw %VGv <- cr0 (%x)\n", pParam1, cr0));
    22972298
     
    23172318 * MOV CRx
    23182319 */
    2319 static int emInterpretMovCRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    2320 {
    2321     if ((pDISState->param1.flags == USE_REG_GEN32 || pDISState->param1.flags == USE_REG_GEN64) && pDISState->param2.flags == USE_REG_CR)
    2322         return EMInterpretCRxRead(pVM, pVCpu, pRegFrame, pDISState->param1.base.reg_gen, pDISState->param2.base.reg_ctrl);
    2323 
    2324     if (pDISState->param1.flags == USE_REG_CR && (pDISState->param2.flags == USE_REG_GEN32 || pDISState->param2.flags == USE_REG_GEN64))
    2325         return EMInterpretCRxWrite(pVM, pVCpu, pRegFrame, pDISState->param1.base.reg_ctrl, pDISState->param2.base.reg_gen);
     2320static int emInterpretMovCRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     2321{
     2322    if ((pDis->param1.flags == USE_REG_GEN32 || pDis->param1.flags == USE_REG_GEN64) && pDis->param2.flags == USE_REG_CR)
     2323        return EMInterpretCRxRead(pVM, pVCpu, pRegFrame, pDis->param1.base.reg_gen, pDis->param2.base.reg_ctrl);
     2324
     2325    if (pDis->param1.flags == USE_REG_CR && (pDis->param2.flags == USE_REG_GEN32 || pDis->param2.flags == USE_REG_GEN64))
     2326        return EMInterpretCRxWrite(pVM, pVCpu, pRegFrame, pDis->param1.base.reg_ctrl, pDis->param2.base.reg_gen);
    23262327
    23272328    AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
     
    24032404 * MOV DRx
    24042405 */
    2405 static int emInterpretMovDRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     2406static int emInterpretMovDRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    24062407{
    24072408    int rc = VERR_EM_INTERPRETER;
    24082409
    2409     if((pDISState->param1.flags == USE_REG_GEN32 || pDISState->param1.flags == USE_REG_GEN64) && pDISState->param2.flags == USE_REG_DBG)
    2410     {
    2411         rc = EMInterpretDRxRead(pVM, pVCpu, pRegFrame, pDISState->param1.base.reg_gen, pDISState->param2.base.reg_dbg);
     2410    if((pDis->param1.flags == USE_REG_GEN32 || pDis->param1.flags == USE_REG_GEN64) && pDis->param2.flags == USE_REG_DBG)
     2411    {
     2412        rc = EMInterpretDRxRead(pVM, pVCpu, pRegFrame, pDis->param1.base.reg_gen, pDis->param2.base.reg_dbg);
    24122413    }
    24132414    else
    2414     if(pDISState->param1.flags == USE_REG_DBG && (pDISState->param2.flags == USE_REG_GEN32 || pDISState->param2.flags == USE_REG_GEN64))
    2415     {
    2416         rc = EMInterpretDRxWrite(pVM, pVCpu, pRegFrame, pDISState->param1.base.reg_dbg, pDISState->param2.base.reg_gen);
     2415    if(pDis->param1.flags == USE_REG_DBG && (pDis->param2.flags == USE_REG_GEN32 || pDis->param2.flags == USE_REG_GEN64))
     2416    {
     2417        rc = EMInterpretDRxWrite(pVM, pVCpu, pRegFrame, pDis->param1.base.reg_dbg, pDis->param2.base.reg_gen);
    24172418    }
    24182419    else
     
    24262427 * LLDT Emulation.
    24272428 */
    2428 static int emInterpretLLdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     2429static int emInterpretLLdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    24292430{
    24302431    OP_PARAMVAL param1;
    24312432    RTSEL       sel;
    24322433
    2433     int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_SOURCE);
     2434    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
    24342435    if(RT_FAILURE(rc))
    24352436        return VERR_EM_INTERPRETER;
     
    24732474 * LIDT/LGDT Emulation.
    24742475 */
    2475 static int emInterpretLIGdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     2476static int emInterpretLIGdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    24762477{
    24772478    OP_PARAMVAL param1;
     
    24792480    X86XDTR32   dtr32;
    24802481
    2481     Log(("Emulate %s at %RGv\n", emGetMnemonic(pDISState), (RTGCPTR)pRegFrame->rip));
     2482    Log(("Emulate %s at %RGv\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip));
    24822483
    24832484    /* Only for the VT-x real-mode emulation case. */
    24842485    AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
    24852486
    2486     int rc = DISQueryParamVal(pRegFrame, pDISState, &pDISState->param1, &param1, PARAM_SOURCE);
     2487    int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
    24872488    if(RT_FAILURE(rc))
    24882489        return VERR_EM_INTERPRETER;
     
    24912492    {
    24922493    case PARMTYPE_ADDRESS:
    2493         pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDISState, &pDISState->param1, param1.val.val16);
     2494        pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, param1.val.val16);
    24942495        break;
    24952496
     
    25012502    AssertRCReturn(rc, VERR_EM_INTERPRETER);
    25022503
    2503     if (!(pDISState->prefix & PREFIX_OPSIZE))
     2504    if (!(pDis->prefix & PREFIX_OPSIZE))
    25042505        dtr32.uAddr &= 0xffffff; /* 16 bits operand size */
    25052506
    2506     if (pDISState->pCurInstr->opcode == OP_LIDT)
     2507    if (pDis->pCurInstr->opcode == OP_LIDT)
    25072508        CPUMSetGuestIDTR(pVCpu, dtr32.uAddr, dtr32.cb);
    25082509    else
     
    25202521 * @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
    25212522 */
    2522 static int emInterpretSti(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     2523static int emInterpretSti(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    25232524{
    25242525    PPATMGCSTATE pGCState = PATMQueryGCState(pVM);
     
    25342535    Assert(pvFault == SELMToFlat(pVM, DIS_SELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
    25352536
    2536     pVCpu->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pDISState->opsize;
     2537    pVCpu->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pDis->opsize;
    25372538    VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
    25382539
     
    25452546 * HLT Emulation.
    25462547 */
    2547 static int emInterpretHlt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     2548static int emInterpretHlt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    25482549{
    25492550    return VINF_EM_HALT;
     
    26122613 * RDTSC Emulation.
    26132614 */
    2614 static int emInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     2615static int emInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    26152616{
    26162617    return EMInterpretRdtsc(pVM, pVCpu, pRegFrame);
     
    26482649 * RDPMC Emulation
    26492650 */
    2650 static int emInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     2651static int emInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    26512652{
    26522653    return EMInterpretRdpmc(pVM, pVCpu, pRegFrame);
     
    26562657 * MONITOR Emulation.
    26572658 */
    2658 static int emInterpretMonitor(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     2659static int emInterpretMonitor(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    26592660{
    26602661    uint32_t u32Dummy, u32ExtFeatures, cpl;
    26612662
    2662     Assert(pDISState->mode != CPUMODE_64BIT);    /** @todo check */
     2663    Assert(pDis->mode != CPUMODE_64BIT);    /** @todo check */
    26632664    if (pRegFrame->ecx != 0)
    26642665        return VERR_EM_INTERPRETER; /* illegal value. */
     
    26842685    uint32_t u32Dummy, u32ExtFeatures, cpl;
    26852686
    2686     /* @todo bit 1 is supposed to tell the cpu to wake us up on interrupts even if IF is cleared. 
     2687    /* @todo bit 1 is supposed to tell the cpu to wake us up on interrupts even if IF is cleared.
    26872688     * Not sure which models. Intel docs say ecx and eax must be zero for Pentium 4 CPUs
    26882689     * CPUID.05H.ECX[0] defines support for power management extensions (eax)
     
    27042705}
    27052706
    2706 static int emInterpretMWait(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    2707 {
    2708     Assert(pDISState->mode != CPUMODE_64BIT);    /** @todo check */
     2707static int emInterpretMWait(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     2708{
     2709    Assert(pDis->mode != CPUMODE_64BIT);    /** @todo check */
    27092710
    27102711    return EMInterpretMWait(pVM, pVCpu, pRegFrame);
     
    29262927 * RDMSR Emulation.
    29272928 */
    2928 static int emInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     2929static int emInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    29292930{
    29302931    /* Note: the Intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
    2931     Assert(!(pDISState->prefix & PREFIX_REX));
     2932    Assert(!(pDis->prefix & PREFIX_REX));
    29322933    return EMInterpretRdmsr(pVM, pVCpu, pRegFrame);
    29332934}
     
    30693070 * WRMSR Emulation.
    30703071 */
    3071 static int emInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     3072static int emInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    30723073{
    30733074    return EMInterpretWrmsr(pVM, pVCpu, pRegFrame);
     
    30793080 * @copydoc EMInterpretInstructionCPU
    30803081 */
    3081 DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     3082DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
    30823083{
    30833084    Assert(pcbSize);
     
    30913092    uint32_t cpl = CPUMGetGuestCPL(pVCpu, pRegFrame);
    30923093    if (    cpl != 0
    3093         &&  pDISState->pCurInstr->opcode != OP_RDTSC)    /* rdtsc requires emulation in ring 3 as well */
     3094        &&  pDis->pCurInstr->opcode != OP_RDTSC)    /* rdtsc requires emulation in ring 3 as well */
    30943095    {
    30953096        Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
     
    30993100
    31003101#ifdef IN_RC
    3101     if (    (pDISState->prefix & (PREFIX_REPNE | PREFIX_REP))
    3102         ||  (   (pDISState->prefix & PREFIX_LOCK)
    3103              && pDISState->pCurInstr->opcode != OP_CMPXCHG
    3104              && pDISState->pCurInstr->opcode != OP_CMPXCHG8B
    3105              && pDISState->pCurInstr->opcode != OP_XADD
    3106              && pDISState->pCurInstr->opcode != OP_OR
    3107              && pDISState->pCurInstr->opcode != OP_BTR
     3102    if (    (pDis->prefix & (PREFIX_REPNE | PREFIX_REP))
     3103        ||  (   (pDis->prefix & PREFIX_LOCK)
     3104             && pDis->pCurInstr->opcode != OP_CMPXCHG
     3105             && pDis->pCurInstr->opcode != OP_CMPXCHG8B
     3106             && pDis->pCurInstr->opcode != OP_XADD
     3107             && pDis->pCurInstr->opcode != OP_OR
     3108             && pDis->pCurInstr->opcode != OP_BTR
    31083109            )
    31093110       )
    31103111#else
    3111     if (    (pDISState->prefix & PREFIX_REPNE)
    3112         ||  (   (pDISState->prefix & PREFIX_REP)
    3113              && pDISState->pCurInstr->opcode != OP_STOSWD
     3112    if (    (pDis->prefix & PREFIX_REPNE)
     3113        ||  (   (pDis->prefix & PREFIX_REP)
     3114             && pDis->pCurInstr->opcode != OP_STOSWD
    31143115            )
    3115         ||  (   (pDISState->prefix & PREFIX_LOCK)
    3116              && pDISState->pCurInstr->opcode != OP_OR
    3117              && pDISState->pCurInstr->opcode != OP_BTR
    3118              && pDISState->pCurInstr->opcode != OP_CMPXCHG
    3119              && pDISState->pCurInstr->opcode != OP_CMPXCHG8B
     3116        ||  (   (pDis->prefix & PREFIX_LOCK)
     3117             && pDis->pCurInstr->opcode != OP_OR
     3118             && pDis->pCurInstr->opcode != OP_BTR
     3119             && pDis->pCurInstr->opcode != OP_CMPXCHG
     3120             && pDis->pCurInstr->opcode != OP_CMPXCHG8B
    31203121            )
    31213122       )
     
    31323133     * Whitelisted instructions are safe.
    31333134     */
    3134     if (    pDISState->param1.size > 4
     3135    if (    pDis->param1.size > 4
    31353136        &&  CPUMIsGuestIn64BitCode(pVCpu, pRegFrame))
    31363137    {
    3137         uint32_t uOpCode = pDISState->pCurInstr->opcode;
     3138        uint32_t uOpCode = pDis->pCurInstr->opcode;
    31383139        if (    uOpCode != OP_STOSWD
    31393140            &&  uOpCode != OP_MOV
     
    31563157        {
    31573158# ifdef VBOX_WITH_STATISTICS
    3158             switch (pDISState->pCurInstr->opcode)
     3159            switch (pDis->pCurInstr->opcode)
    31593160            {
    31603161#  define INTERPRET_FAILED_CASE(opcode, Instr) \
     
    32103211    int rc;
    32113212#if (defined(VBOX_STRICT) || defined(LOG_ENABLED))
    3212     LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pDISState)));
    3213 #endif
    3214     switch (pDISState->pCurInstr->opcode)
     3213    LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pDis)));
     3214#endif
     3215    switch (pDis->pCurInstr->opcode)
    32153216    {
    32163217        /*
     
    32193220# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
    32203221        case opcode:\
    3221             if (pDISState->prefix & PREFIX_LOCK) \
    3222                 rc = emInterpretLock##InstrFn(pVM, pVCpu, pDISState, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
     3222            if (pDis->prefix & PREFIX_LOCK) \
     3223                rc = emInterpretLock##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
    32233224            else \
    3224                 rc = emInterpret##InstrFn(pVM, pVCpu, pDISState, pRegFrame, pvFault, pcbSize, pfnEmulate); \
     3225                rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
    32253226            if (RT_SUCCESS(rc)) \
    32263227                STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
     
    32303231#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
    32313232        case opcode:\
    3232             rc = emInterpret##InstrFn(pVM, pVCpu, pDISState, pRegFrame, pvFault, pcbSize, pfnEmulate); \
     3233            rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
    32333234            if (RT_SUCCESS(rc)) \
    32343235                STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
     
    32443245#define INTERPRET_CASE(opcode, Instr) \
    32453246        case opcode:\
    3246             rc = emInterpret##Instr(pVM, pVCpu, pDISState, pRegFrame, pvFault, pcbSize); \
     3247            rc = emInterpret##Instr(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \
    32473248            if (RT_SUCCESS(rc)) \
    32483249                STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
     
    32533254#define INTERPRET_CASE_EX_DUAL_PARAM2(opcode, Instr, InstrFn) \
    32543255        case opcode:\
    3255             rc = emInterpret##InstrFn(pVM, pVCpu, pDISState, pRegFrame, pvFault, pcbSize); \
     3256            rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \
    32563257            if (RT_SUCCESS(rc)) \
    32573258                STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
     
    33203321
    33213322        default:
    3322             Log3(("emInterpretInstructionCPU: opcode=%d\n", pDISState->pCurInstr->opcode));
     3323            Log3(("emInterpretInstructionCPU: opcode=%d\n", pDis->pCurInstr->opcode));
    33233324            STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
    33243325            return VERR_EM_INTERPRETER;
  • trunk/src/VBox/VMM/VMMAll/IOMAllMMIO.cpp

    r20014 r20530  
    11081108     * Disassemble the instruction and interpret it.
    11091109     */
    1110     DISCPUSTATE Cpu;
    1111     unsigned cbOp;
    1112     rc = EMInterpretDisasOne(pVM, VMMGetCpu(pVM), pCtxCore, &Cpu, &cbOp);
     1110    PVMCPU          pVCpu = VMMGetCpu(pVM);
     1111    PDISCPUSTATE    pDis  = &pVCpu->iom.s.DisState;
     1112    unsigned        cbOp;
     1113    rc = EMInterpretDisasOne(pVM, pVCpu, pCtxCore, pDis, &cbOp);
    11131114    AssertRC(rc);
    11141115    if (RT_FAILURE(rc))
     
    11171118        return rc;
    11181119    }
    1119     switch (Cpu.pCurInstr->opcode)
     1120    switch (pDis->pCurInstr->opcode)
    11201121    {
    11211122        case OP_MOV:
     
    11251126            STAM_PROFILE_START(&pVM->iom.s.StatRZInstMov, b);
    11261127            if (uErrorCode & X86_TRAP_PF_RW)
    1127                 rc = iomInterpretMOVxXWrite(pVM, pCtxCore, &Cpu, pRange, GCPhysFault);
     1128                rc = iomInterpretMOVxXWrite(pVM, pCtxCore, pDis, pRange, GCPhysFault);
    11281129            else
    1129                 rc = iomInterpretMOVxXRead(pVM, pCtxCore, &Cpu, pRange, GCPhysFault);
     1130                rc = iomInterpretMOVxXRead(pVM, pCtxCore, pDis, pRange, GCPhysFault);
    11301131            STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstMov, b);
    11311132            break;
     
    11391140            STAM_PROFILE_ADV_START(&pVM->iom.s.StatRZInstMovs, c);
    11401141            PSTAMPROFILE pStat = NULL;
    1141             rc = iomInterpretMOVS(pVM, uErrorCode, pCtxCore, GCPhysFault, &Cpu, pRange, &pStat);
     1142            rc = iomInterpretMOVS(pVM, uErrorCode, pCtxCore, GCPhysFault, pDis, pRange, &pStat);
    11421143            STAM_PROFILE_ADV_STOP_EX(&pVM->iom.s.StatRZInstMovs, pStat, c);
    11431144            break;
     
    11491150            Assert(uErrorCode & X86_TRAP_PF_RW);
    11501151            STAM_PROFILE_START(&pVM->iom.s.StatRZInstStos, d);
    1151             rc = iomInterpretSTOS(pVM, pCtxCore, GCPhysFault, &Cpu, pRange);
     1152            rc = iomInterpretSTOS(pVM, pCtxCore, GCPhysFault, pDis, pRange);
    11521153            STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstStos, d);
    11531154            break;
     
    11571158            Assert(!(uErrorCode & X86_TRAP_PF_RW));
    11581159            STAM_PROFILE_START(&pVM->iom.s.StatRZInstLods, e);
    1159             rc = iomInterpretLODS(pVM, pCtxCore, GCPhysFault, &Cpu, pRange);
     1160            rc = iomInterpretLODS(pVM, pCtxCore, GCPhysFault, pDis, pRange);
    11601161            STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstLods, e);
    11611162            break;
     
    11641165            Assert(!(uErrorCode & X86_TRAP_PF_RW));
    11651166            STAM_PROFILE_START(&pVM->iom.s.StatRZInstCmp, f);
    1166             rc = iomInterpretCMP(pVM, pCtxCore, GCPhysFault, &Cpu, pRange);
     1167            rc = iomInterpretCMP(pVM, pCtxCore, GCPhysFault, pDis, pRange);
    11671168            STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstCmp, f);
    11681169            break;
     
    11701171        case OP_AND:
    11711172            STAM_PROFILE_START(&pVM->iom.s.StatRZInstAnd, g);
    1172             rc = iomInterpretOrXorAnd(pVM, pCtxCore, GCPhysFault, &Cpu, pRange, EMEmulateAnd);
     1173            rc = iomInterpretOrXorAnd(pVM, pCtxCore, GCPhysFault, pDis, pRange, EMEmulateAnd);
    11731174            STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstAnd, g);
    11741175            break;
     
    11761177        case OP_OR:
    11771178            STAM_PROFILE_START(&pVM->iom.s.StatRZInstOr, k);
    1178             rc = iomInterpretOrXorAnd(pVM, pCtxCore, GCPhysFault, &Cpu, pRange, EMEmulateOr);
     1179            rc = iomInterpretOrXorAnd(pVM, pCtxCore, GCPhysFault, pDis, pRange, EMEmulateOr);
    11791180            STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstOr, k);
    11801181            break;
     
    11821183        case OP_XOR:
    11831184            STAM_PROFILE_START(&pVM->iom.s.StatRZInstXor, m);
    1184             rc = iomInterpretOrXorAnd(pVM, pCtxCore, GCPhysFault, &Cpu, pRange, EMEmulateXor);
     1185            rc = iomInterpretOrXorAnd(pVM, pCtxCore, GCPhysFault, pDis, pRange, EMEmulateXor);
    11851186            STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstXor, m);
    11861187            break;
     
    11891190            Assert(!(uErrorCode & X86_TRAP_PF_RW));
    11901191            STAM_PROFILE_START(&pVM->iom.s.StatRZInstTest, h);
    1191             rc = iomInterpretTEST(pVM, pCtxCore, GCPhysFault, &Cpu, pRange);
     1192            rc = iomInterpretTEST(pVM, pCtxCore, GCPhysFault, pDis, pRange);
    11921193            STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstTest, h);
    11931194            break;
     
    11961197            Assert(!(uErrorCode & X86_TRAP_PF_RW));
    11971198            STAM_PROFILE_START(&pVM->iom.s.StatRZInstBt, l);
    1198             rc = iomInterpretBT(pVM, pCtxCore, GCPhysFault, &Cpu, pRange);
     1199            rc = iomInterpretBT(pVM, pCtxCore, GCPhysFault, pDis, pRange);
    11991200            STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstBt, l);
    12001201            break;
     
    12021203        case OP_XCHG:
    12031204            STAM_PROFILE_START(&pVM->iom.s.StatRZInstXchg, i);
    1204             rc = iomInterpretXCHG(pVM, pCtxCore, GCPhysFault, &Cpu, pRange);
     1205            rc = iomInterpretXCHG(pVM, pCtxCore, GCPhysFault, pDis, pRange);
    12051206            STAM_PROFILE_STOP(&pVM->iom.s.StatRZInstXchg, i);
    12061207            break;
  • trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

    r20519 r20530  
    727727                            if (rc == VINF_SUCCESS)
    728728                            {
    729                                 DISCPUSTATE Cpu;
    730                                 uint32_t    cbOp;
    731                                 rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, &Cpu, &cbOp);
     729                                PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
     730                                uint32_t     cbOp;
     731                                rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, pDis, &cbOp);
    732732
    733733                                /* For now we'll restrict this to rep movsw/d instructions */
    734734                                if (    rc == VINF_SUCCESS
    735                                     &&  Cpu.pCurInstr->opcode == OP_MOVSWD
    736                                     &&  (Cpu.prefix & PREFIX_REP))
     735                                    &&  pDis->pCurInstr->opcode == OP_MOVSWD
     736                                    &&  (pDis->prefix & PREFIX_REP))
    737737                                {
    738738                                    CSAMMarkPossibleCodePage(pVM, pvFault);
  • trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp

    r20059 r20530  
    7575             * we will simply skip it. Otherwise we'll have to defer it to REM.
    7676             */
    77             uint32_t cbOp;
    78             DISCPUSTATE Cpu;
    79             rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, &Cpu, &cbOp);
     77            uint32_t     cbOp;
     78            PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
     79            rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, pDis, &cbOp);
    8080            if (     RT_SUCCESS(rc)
    81                 &&   Cpu.mode == CPUMODE_32BIT  /** @todo why does this matter? */
    82                 &&  !(Cpu.prefix & (PREFIX_REPNE | PREFIX_REP | PREFIX_SEG)))
     81                &&   pDis->mode == CPUMODE_32BIT  /** @todo why does this matter? */
     82                &&  !(pDis->prefix & (PREFIX_REPNE | PREFIX_REP | PREFIX_SEG)))
    8383            {
    84                 switch (Cpu.opcode)
     84                switch (pDis->opcode)
    8585                {
    8686                    /** @todo Find other instructions we can safely skip, possibly
  • trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp

    r20489 r20530  
    243243 * @param   uAddress    In R0 and GC this is the guest context fault address (flat).
    244244 *                      In R3 this is the host context 'fault' address.
    245  * @param   pCpu        The disassembler state for figuring out the write size.
     245 * @param   pDis        The disassembler state for figuring out the write size.
    246246 *                      This need not be specified if the caller knows we won't do cross entry accesses.
    247247 */
    248 void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu)
     248void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pDis)
    249249{
    250250    Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
    251251    const unsigned off     = GCPhysFault & PAGE_OFFSET_MASK;
    252     const unsigned cbWrite = (pCpu) ? pgmPoolDisasWriteSize(pCpu) : 0;
     252    const unsigned cbWrite = pDis ? pgmPoolDisasWriteSize(pDis) : 0;
    253253    PVM pVM = pPool->CTX_SUFF(pVM);
    254254
     
    354354
    355355                        /* paranoia / a bit assumptive. */
    356                         if (   pCpu
     356                        if (   pDis
    357357                            && (off & 3)
    358358                            && (off & 3) + cbWrite > 4)
     
    407407
    408408                /* paranoia / a bit assumptive. */
    409                 if (   pCpu
     409                if (   pDis
    410410                    && (off & 7)
    411411                    && (off & 7) + cbWrite > sizeof(X86PTEPAE))
     
    466466                }
    467467                /* paranoia / a bit assumptive. */
    468                 if (   pCpu
     468                if (   pDis
    469469                    && (off & 3)
    470470                    && (off & 3) + cbWrite > sizeof(X86PTE))
     
    549549                }
    550550                /* paranoia / a bit assumptive. */
    551                 if (   pCpu
     551                if (   pDis
    552552                    && (off & 7)
    553553                    && (off & 7) + cbWrite > sizeof(X86PDEPAE))
     
    621621
    622622                    /* paranoia / a bit assumptive. */
    623                     if (   pCpu
     623                    if (   pDis
    624624                        && (offPdpt & 7)
    625625                        && (offPdpt & 7) + cbWrite > sizeof(X86PDPE))
     
    673673                }
    674674                /* paranoia / a bit assumptive. */
    675                 if (   pCpu
     675                if (   pDis
    676676                    && (off & 7)
    677677                    && (off & 7) + cbWrite > sizeof(X86PDEPAE))
     
    711711                    }
    712712                    /* paranoia / a bit assumptive. */
    713                     if (   pCpu
     713                    if (   pDis
    714714                        && (off & 7)
    715715                        && (off & 7) + cbWrite > sizeof(X86PDPE))
     
    744744                    }
    745745                    /* paranoia / a bit assumptive. */
    746                     if (   pCpu
     746                    if (   pDis
    747747                        && (off & 7)
    748748                        && (off & 7) + cbWrite > sizeof(X86PDPE))
     
    781781 * @returns true if it's likly that we're forking, otherwise false.
    782782 * @param   pPool       The pool.
    783  * @param   pCpu        The disassembled instruction.
     783 * @param   pDis        The disassembled instruction.
    784784 * @param   offFault    The access offset.
    785785 */
    786 DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pCpu, unsigned offFault)
     786DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pDis, unsigned offFault)
    787787{
    788788    /*
     
    802802     *      do_fork
    803803     */
    804     if (    pCpu->pCurInstr->opcode == OP_BTR
     804    if (    pDis->pCurInstr->opcode == OP_BTR
    805805        &&  !(offFault & 4)
    806806        /** @todo Validate that the bit index is X86_PTE_RW. */
     
    821821 * @param   pVM         VM Handle.
    822822 * @param   pRegFrame   Trap register frame.
    823  * @param   pCpu        The disassembly info for the faulting instruction.
     823 * @param   pDis        The disassembly info for the faulting instruction.
    824824 * @param   pvFault     The fault address.
    825825 *
    826826 * @remark  The REP prefix check is left to the caller because of STOSD/W.
    827827 */
    828 DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR pvFault)
     828DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, RTGCPTR pvFault)
    829829{
    830830#ifndef IN_RC
     
    841841#endif
    842842
    843     switch (pCpu->pCurInstr->opcode)
     843    switch (pDis->pCurInstr->opcode)
    844844    {
    845845        /* call implies the actual push of the return address faulted */
     
    867867        case OP_MOVSWD:
    868868        case OP_STOSWD:
    869             if (    pCpu->prefix == (PREFIX_REP|PREFIX_REX)
     869            if (    pDis->prefix == (PREFIX_REP|PREFIX_REX)
    870870                &&  pRegFrame->rcx >= 0x40
    871871               )
    872872            {
    873                 Assert(pCpu->mode == CPUMODE_64BIT);
     873                Assert(pDis->mode == CPUMODE_64BIT);
    874874
    875875                Log(("pgmPoolMonitorIsReused: OP_STOSQ\n"));
     
    878878            return false;
    879879    }
    880     if (    (pCpu->param1.flags & USE_REG_GEN32)
    881         &&  (pCpu->param1.base.reg_gen == USE_REG_ESP))
     880    if (    (pDis->param1.flags & USE_REG_GEN32)
     881        &&  (pDis->param1.base.reg_gen == USE_REG_ESP))
    882882    {
    883883        Log4(("pgmPoolMonitorIsReused: ESP\n"));
     
    897897 * @param   pPool       The pool.
    898898 * @param   pPage       The pool page (head).
    899  * @param   pCpu        The disassembly of the write instruction.
     899 * @param   pDis        The disassembly of the write instruction.
    900900 * @param   pRegFrame   The trap register frame.
    901901 * @param   GCPhysFault The fault address as guest physical address.
    902902 * @param   pvFault     The fault address.
    903903 */
    904 static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
     904static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
    905905                                     PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
    906906{
     
    914914     */
    915915    uint32_t cbWritten;
    916     int rc2 = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, pvFault, &cbWritten);
     916    int rc2 = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, &cbWritten);
    917917    if (RT_SUCCESS(rc2))
    918         pRegFrame->rip += pCpu->opsize;
     918        pRegFrame->rip += pDis->opsize;
    919919    else if (rc2 == VERR_EM_INTERPRETER)
    920920    {
     
    953953 * @param   pPool       The pool.
    954954 * @param   pPage       The pool page (head).
    955  * @param   pCpu        The disassembly of the write instruction.
     955 * @param   pDis        The disassembly of the write instruction.
    956956 * @param   pRegFrame   The trap register frame.
    957957 * @param   GCPhysFault The fault address as guest physical address.
    958958 * @param   pvFault     The fault address.
    959959 */
    960 DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
     960DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
    961961                                          PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
    962962{
    963     Assert(pCpu->mode == CPUMODE_32BIT);
     963    Assert(pDis->mode == CPUMODE_32BIT);
    964964
    965965    Log3(("pgmPoolAccessHandlerSTOSD\n"));
     
    999999        pRegFrame->ecx--;
    10001000    }
    1001     pRegFrame->rip += pCpu->opsize;
     1001    pRegFrame->rip += pDis->opsize;
    10021002
    10031003#ifdef IN_RC
     
    10191019 * @param   pPool       The pool.
    10201020 * @param   pPage       The pool page (head).
    1021  * @param   pCpu        The disassembly of the write instruction.
     1021 * @param   pDis        The disassembly of the write instruction.
    10221022 * @param   pRegFrame   The trap register frame.
    10231023 * @param   GCPhysFault The fault address as guest physical address.
    10241024 * @param   pvFault     The fault address.
    10251025 */
    1026 DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
     1026DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
    10271027                                           PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
    10281028{
     
    10401040#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
    10411041    uint32_t    iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
    1042     pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pCpu);
     1042    pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pDis);
    10431043    PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
    10441044#else
    1045     pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pCpu);
     1045    pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pDis);
    10461046#endif
    10471047
     
    10501050     */
    10511051    uint32_t cb;
    1052     int rc = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, pvFault, &cb);
     1052    int rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, &cb);
    10531053    if (RT_SUCCESS(rc))
    1054         pRegFrame->rip += pCpu->opsize;
     1054        pRegFrame->rip += pDis->opsize;
    10551055    else if (rc == VERR_EM_INTERPRETER)
    10561056    {
    10571057        LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
    1058                   pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pCpu->pCurInstr->opcode));
     1058                  pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode));
    10591059        rc = VINF_EM_RAW_EMULATE_INSTR;
    10601060        STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
     
    11111111     * Disassemble the faulting instruction.
    11121112     */
    1113     DISCPUSTATE Cpu;
    1114     int rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, &Cpu, NULL);
     1113    PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
     1114    int rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, pDis, NULL);
    11151115    AssertRCReturn(rc, rc);
    11161116
     
    11321132             || pgmPoolIsPageLocked(&pVM->pgm.s, pPage)
    11331133            )
    1134         &&  !(fReused = pgmPoolMonitorIsReused(pVM, pRegFrame, &Cpu, pvFault))
    1135         &&  !pgmPoolMonitorIsForking(pPool, &Cpu, GCPhysFault & PAGE_OFFSET_MASK))
     1134        &&  !(fReused = pgmPoolMonitorIsReused(pVM, pRegFrame, pDis, pvFault))
     1135        &&  !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
    11361136    {
    11371137        /*
    11381138         * Simple instructions, no REP prefix.
    11391139         */
    1140         if (!(Cpu.prefix & (PREFIX_REP | PREFIX_REPNE)))
    1141         {
    1142              rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
     1140        if (!(pDis->prefix & (PREFIX_REP | PREFIX_REPNE)))
     1141        {
     1142             rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
    11431143             STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
    11441144             pgmUnlock(pVM);
     
    11501150         * We have to deal with these or we'll kill the cache and performance.
    11511151         */
    1152         if (    Cpu.pCurInstr->opcode == OP_STOSWD
     1152        if (    pDis->pCurInstr->opcode == OP_STOSWD
    11531153            &&  CPUMGetGuestCPL(pVCpu, pRegFrame) == 0
    11541154            &&  pRegFrame->ecx <= 0x20
     
    11561156            &&  !((uintptr_t)pvFault & 3)
    11571157            &&  (pRegFrame->eax == 0 || pRegFrame->eax == 0x80) /* the two values observed. */
    1158             &&  Cpu.mode == CPUMODE_32BIT
    1159             &&  Cpu.opmode == CPUMODE_32BIT
    1160             &&  Cpu.addrmode == CPUMODE_32BIT
    1161             &&  Cpu.prefix == PREFIX_REP
     1158            &&  pDis->mode == CPUMODE_32BIT
     1159            &&  pDis->opmode == CPUMODE_32BIT
     1160            &&  pDis->addrmode == CPUMODE_32BIT
     1161            &&  pDis->prefix == PREFIX_REP
    11621162            &&  !pRegFrame->eflags.Bits.u1DF
    11631163            )
    11641164        {
    1165              rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
     1165             rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
    11661166             STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a);
    11671167             pgmUnlock(pVM);
     
    11721172        STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix));
    11731173        Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
    1174               pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, Cpu.pCurInstr->opcode, Cpu.prefix));
     1174              pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode, pDis->prefix));
    11751175    }
    11761176
     
    11831183     * the reuse detection must be fixed.
    11841184     */
    1185     rc = pgmPoolAccessHandlerFlush(pVM, pVCpu, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
     1185    rc = pgmPoolAccessHandlerFlush(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
    11861186    if (rc == VINF_EM_RAW_EMULATE_INSTR && fReused)
    11871187        rc = VINF_SUCCESS;
  • trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

    r20516 r20530  
    10231023     *
    10241024     * Interrupts are disabled before the call to make sure we don't miss any interrupt
    1025      * that would flag preemption (IPI, timer tick, ++). 
     1025     * that would flag preemption (IPI, timer tick, ++).
    10261026     *
    10271027     * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
     
    20622062        {
    20632063            /* ins/outs */
    2064             DISCPUSTATE Cpu;
     2064            PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
    20652065
    20662066            /* Disassemble manually to deal with segment prefixes. */
    2067             rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, NULL);
     2067            rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
    20682068            if (rc == VINF_SUCCESS)
    20692069            {
     
    20722072                    Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
    20732073                    STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
    2074                     rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, Cpu.prefix, uIOSize);
     2074                    rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize);
    20752075                }
    20762076                else
     
    20782078                    Log2(("IOMInterpretINSEx  %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
    20792079                    STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
    2080                     rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, Cpu.prefix, uIOSize);
     2080                    rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize);
    20812081                }
    20822082            }
     
    23372337 * @returns VBox status code.
    23382338 * @param   pVCpu       The VM CPU to operate on.
    2339  * @param   pDisState   Disassembly state
     2339 * @param   pDis        Disassembly state
    23402340 * @param   pCtx        CPU context
    23412341 * @param   cbOp        Opcode size
    23422342 */
    2343 static int svmR0EmulateTprMov(PVMCPU pVCpu, DISCPUSTATE *pDisState, PCPUMCTX pCtx, unsigned cbOp)
     2343static int svmR0EmulateTprMov(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTX pCtx, unsigned cbOp)
    23442344{
    23452345    int rc;
    23462346
    2347     if (pDisState->param1.flags == USE_DISPLACEMENT32)
     2347    if (pDis->param1.flags == USE_DISPLACEMENT32)
    23482348    {
    23492349        /* write */
     
    23512351
    23522352        /* Fetch the new TPR value */
    2353         if (pDisState->param2.flags == USE_REG_GEN32)
     2353        if (pDis->param2.flags == USE_REG_GEN32)
    23542354        {
    23552355            uint32_t val;
    23562356
    2357             rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pDisState->param2.base.reg_gen, &val);
     2357            rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pDis->param2.base.reg_gen, &val);
    23582358            AssertRC(rc);
    23592359            u8Tpr = val >> 4;
    23602360        }
    23612361        else
    2362         if (pDisState->param2.flags == USE_IMMEDIATE32)
    2363         {
    2364             u8Tpr = (uint8_t)pDisState->param2.parval >> 4;
     2362        if (pDis->param2.flags == USE_IMMEDIATE32)
     2363        {
     2364            u8Tpr = (uint8_t)pDis->param2.parval >> 4;
    23652365        }
    23662366        else
     
    23752375    }
    23762376    else
    2377     if (pDisState->param2.flags == USE_DISPLACEMENT32)
     2377    if (pDis->param2.flags == USE_DISPLACEMENT32)
    23782378    {
    23792379        /* read */
     
    23852385        AssertRC(rc);
    23862386
    2387         rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pDisState->param1.base.reg_gen, u8Tpr << 4);
     2387        rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pDis->param1.base.reg_gen, u8Tpr << 4);
    23882388        AssertRC(rc);
    23892389
     
    24052405static int svmR0ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
    24062406{
    2407     RTGCPTR     oldrip = pCtx->rip;
    2408     DISCPUSTATE Cpu;
    2409     unsigned    cbOp;
     2407    RTGCPTR      oldrip = pCtx->rip;
     2408    PDISCPUSTATE pDis   = &pVCpu->hwaccm.s.DisState;
     2409    unsigned     cbOp;
    24102410
    24112411    Log(("Replace TPR access at %RGv\n", pCtx->rip));
    24122412
    2413     int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
     2413    int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
    24142414    AssertRC(rc);
    24152415    if (    rc == VINF_SUCCESS
    2416         &&  Cpu.pCurInstr->opcode == OP_MOV)
     2416        &&  pDis->pCurInstr->opcode == OP_MOV)
    24172417    {
    24182418#if 0
    24192419        uint8_t szInstr[15];
    24202420        if (    cbOp == 10
    2421             &&  Cpu.param1.flags == USE_DISPLACEMENT32
    2422             &&  Cpu.param2.flags == USE_IMMEDIATE32)
     2421            &&  pDis->param1.flags == USE_DISPLACEMENT32
     2422            &&  pDis->param2.flags == USE_IMMEDIATE32)
    24232423        {
    24242424            /* Found:
     
    24312431             *
    24322432             */
    2433             uint32_t    u32tpr = (uint32_t)Cpu.param2.parval;
     2433            uint32_t    u32tpr = (uint32_t)pDis->param2.parval;
    24342434
    24352435            u32tpr = (u32tpr >> 4) & 0xf;
    24362436
    2437             /* Check if the next instruction overwrites a general purpose register. If 
     2437            /* Check if the next instruction overwrites a general purpose register. If
    24382438             * it does, then we can safely use it ourselves.
    24392439             */
    24402440            pCtx->rip += cbOp;
    2441             rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
     2441            rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
    24422442            pCtx->rip = oldrip;
    24432443            if (    rc == VINF_SUCCESS
    2444                 &&  Cpu.pCurInstr->opcode == OP_MOV
    2445                 &&  Cpu.param1.flags == USE_REG_GEN32)
     2444                &&  pDis->pCurInstr->opcode == OP_MOV
     2445                &&  pDis->param1.flags == USE_REG_GEN32)
    24462446            {
    24472447                /* 0xB8, dword immediate  = mov eax, dword immediate */
    2448                 szInstr[0] = 0xB8 + Cpu.param1.base.reg_gen;
     2448                szInstr[0] = 0xB8 + pDis->param1.base.reg_gen;
    24492449                szInstr[1] = (uint8_t)u32tpr;
    24502450                szInstr[2] = 0;
     
    24562456                szInstr[6] = 0x0F;
    24572457                szInstr[7] = 0x22;
    2458                 szInstr[8] = 0xC0 | Cpu.param1.base.reg_gen;
     2458                szInstr[8] = 0xC0 | pDis->param1.base.reg_gen;
    24592459                szInstr[9] = 0x90; /* nop */
    24602460
     
    24682468        else
    24692469        {
    2470             if (    Cpu.param2.flags == USE_REG_GEN32
     2470            if (    pDis->param2.flags == USE_REG_GEN32
    24712471                &&  cbOp == 6)
    24722472            {
    2473                 RTGCPTR  GCPtrTpr = (uint32_t)Cpu.param1.disp32;
    2474                 uint32_t uMmioReg = Cpu.param2.base.reg_gen;
     2473                RTGCPTR  GCPtrTpr = (uint32_t)pDis->param1.disp32;
     2474                uint32_t uMmioReg = pDis->param2.base.reg_gen;
    24752475
    24762476                /* Found:
     
    24802480                 */
    24812481                pCtx->rip += cbOp;
    2482                 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
     2482                rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
    24832483                pCtx->rip = oldrip;
    24842484                if (    rc == VINF_SUCCESS
    2485                     &&  Cpu.pCurInstr->opcode == OP_MOV
    2486                     &&  Cpu.param1.flags == USE_REG_GEN32
    2487                     &&  Cpu.param2.flags == USE_DISPLACEMENT32
    2488                     &&  Cpu.param2.disp32 == (uint32_t)GCPtrTpr
     2485                    &&  pDis->pCurInstr->opcode == OP_MOV
     2486                    &&  pDis->param1.flags == USE_REG_GEN32
     2487                    &&  pDis->param2.flags == USE_DISPLACEMENT32
     2488                    &&  pDis->param2.disp32 == (uint32_t)GCPtrTpr
    24892489                    &&  cbOp == 5)
    24902490                {
    24912491                    /* mov new_reg, uMmioReg */
    24922492                    szInstr[0] = 0x89;
    2493                     szInstr[1] = MAKE_MODRM(3, uMmioReg, Cpu.param1.base.reg_gen);
     2493                    szInstr[1] = MAKE_MODRM(3, uMmioReg, pDis->param1.base.reg_gen);
    24942494
    24952495                    /* Let's hope the guest won't mind us trashing the source register...
     
    25182518            }
    25192519            else
    2520             if (    Cpu.param1.flags == USE_REG_GEN32
     2520            if (    pDis->param1.flags == USE_REG_GEN32
    25212521                &&  cbOp == 5)
    25222522            {
    2523                 uint32_t uMmioReg = Cpu.param1.base.reg_gen;
     2523                uint32_t uMmioReg = pDis->param1.base.reg_gen;
    25242524
    25252525                /* Found:
     
    25292529                 */
    25302530                pCtx->rip += cbOp;
    2531                 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
     2531                rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
    25322532                pCtx->rip = oldrip;
    25332533                if (    rc == VINF_SUCCESS
    2534                     &&  Cpu.pCurInstr->opcode == OP_SHR
    2535                     &&  Cpu.param1.flags == USE_REG_GEN32
    2536                     &&  Cpu.param1.base.reg_gen == uMmioReg
    2537                     &&  Cpu.param2.flags == USE_IMMEDIATE8
    2538                     &&  Cpu.param2.parval == 4)
     2534                    &&  pDis->pCurInstr->opcode == OP_SHR
     2535                    &&  pDis->param1.flags == USE_REG_GEN32
     2536                    &&  pDis->param1.base.reg_gen == uMmioReg
     2537                    &&  pDis->param2.flags == USE_IMMEDIATE8
     2538                    &&  pDis->param2.parval == 4)
    25392539                {
    25402540                    /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
     
    25422542                    szInstr[1] = 0x0F;
    25432543                    szInstr[2] = 0x20;
    2544                     szInstr[3] = 0xC0 | Cpu.param1.base.reg_gen;
     2544                    szInstr[3] = 0xC0 | pDis->param1.base.reg_gen;
    25452545                    for (unsigned i = 4; i < 5+cbOp; i++)
    25462546                        szInstr[i] = 0x90;  /* nop */
     
    25552555        }
    25562556#endif
    2557         rc = svmR0EmulateTprMov(pVCpu, &Cpu, pCtx, cbOp);
     2557        rc = svmR0EmulateTprMov(pVCpu, pDis, pCtx, cbOp);
    25582558        if (rc != VINF_SUCCESS)
    25592559            return rc;
     
    26832683        if (RT_SUCCESS(rc))
    26842684        {
    2685             uint32_t    cbOp;
    2686             DISCPUSTATE Cpu;
    2687 
    2688             Cpu.mode = enmMode;
    2689             rc = EMInterpretDisasOneEx(pVM, pVCpu, pbCode, pRegFrame, &Cpu, &cbOp);
    2690             Assert(RT_FAILURE(rc) || Cpu.pCurInstr->opcode == OP_INVLPG);
    2691             if (RT_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
     2685            uint32_t     cbOp;
     2686            PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
     2687
     2688            pDis->mode = enmMode;
     2689            rc = EMInterpretDisasOneEx(pVM, pVCpu, pbCode, pRegFrame, pDis, &cbOp);
     2690            Assert(RT_FAILURE(rc) || pDis->pCurInstr->opcode == OP_INVLPG);
     2691            if (RT_SUCCESS(rc) && pDis->pCurInstr->opcode == OP_INVLPG)
    26922692            {
    2693                 Assert(cbOp == Cpu.opsize);
    2694                 rc = svmR0InterpretInvlPg(pVCpu, &Cpu, pRegFrame, uASID);
     2693                Assert(cbOp == pDis->opsize);
     2694                rc = svmR0InterpretInvlPg(pVCpu, pDis, pRegFrame, uASID);
    26952695                if (RT_SUCCESS(rc))
    26962696                {
  • trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

    r20517 r20530  
    23152315    /* All done! Let's start VM execution. */
    23162316    STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, z);
    2317 #ifdef VBOX_STRICT
    23182317    Assert(idCpuCheck == RTMpCpuId());
    2319 #endif
    23202318
    23212319#ifdef VBOX_WITH_CRASHDUMP_MAGIC
     
    23282326    TMNotifyEndOfExecution(pVCpu);
    23292327    VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
     2328    Assert(!(ASMGetFlags() & X86_EFL_IF));
    23302329    ASMSetFlags(uOldEFlags);
    23312330#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
     
    26762675            case X86_XCPT_GP:   /* General protection failure exception.*/
    26772676            {
    2678                 uint32_t    cbOp;
    2679                 uint32_t    cbSize;
    2680                 DISCPUSTATE Cpu;
     2677                uint32_t     cbOp;
     2678                uint32_t     cbSize;
     2679                PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
    26812680
    26822681                STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
     
    26952694                LogFlow(("Real mode X86_XCPT_GP instruction emulation at %RGv\n", (RTGCPTR)pCtx->rip));
    26962695
    2697                 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
     2696                rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
    26982697                if (RT_SUCCESS(rc))
    26992698                {
    27002699                    bool fUpdateRIP = true;
    27012700
    2702                     Assert(cbOp == Cpu.opsize);
    2703                     switch (Cpu.pCurInstr->opcode)
     2701                    Assert(cbOp == pDis->opsize);
     2702                    switch (pDis->pCurInstr->opcode)
    27042703                    {
    27052704                    case OP_CLI:
     
    27162715                        fUpdateRIP = false;
    27172716                        rc = VINF_EM_HALT;
    2718                         pCtx->rip += Cpu.opsize;
     2717                        pCtx->rip += pDis->opsize;
    27192718                        STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
    27202719                        break;
     
    27272726                        X86EFLAGS eflags;
    27282727
    2729                         if (Cpu.prefix & PREFIX_OPSIZE)
     2728                        if (pDis->prefix & PREFIX_OPSIZE)
    27302729                        {
    27312730                            cbParm = 4;
     
    27692768                        X86EFLAGS eflags;
    27702769
    2771                         if (Cpu.prefix & PREFIX_OPSIZE)
     2770                        if (pDis->prefix & PREFIX_OPSIZE)
    27722771                        {
    27732772                            cbParm = 4;
     
    28102809                        uint16_t  aIretFrame[3];
    28112810
    2812                         if (Cpu.prefix & (PREFIX_OPSIZE | PREFIX_ADDRSIZE))
     2811                        if (pDis->prefix & (PREFIX_OPSIZE | PREFIX_ADDRSIZE))
    28132812                        {
    28142813                            rc = VERR_EM_INTERPRETER;
     
    28442843                        RTGCUINTPTR intInfo;
    28452844
    2846                         LogFlow(("Realmode: INT %x\n", Cpu.param1.parval & 0xff));
    2847                         intInfo  = Cpu.param1.parval & 0xff;
     2845                        LogFlow(("Realmode: INT %x\n", pDis->param1.parval & 0xff));
     2846                        intInfo  = pDis->param1.parval & 0xff;
    28482847                        intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
    28492848                        intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
     
    28922891
    28932892                    default:
    2894                         rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
     2893                        rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, CPUMCTX2CORE(pCtx), 0, &cbSize);
    28952894                        break;
    28962895                    }
     
    33413340        {
    33423341            /* ins/outs */
    3343             DISCPUSTATE Cpu;
     3342            PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
    33443343
    33453344            /* Disassemble manually to deal with segment prefixes. */
    33463345            /** @todo VMX_VMCS_EXIT_GUEST_LINEAR_ADDR contains the flat pointer operand of the instruction. */
    33473346            /** @todo VMX_VMCS32_RO_EXIT_INSTR_INFO also contains segment prefix info. */
    3348             rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, NULL);
     3347            rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
    33493348            if (rc == VINF_SUCCESS)
    33503349            {
     
    33533352                    Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
    33543353                    STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
    3355                     rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, Cpu.prefix, cbSize);
     3354                    rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->prefix, cbSize);
    33563355                }
    33573356                else
     
    33593358                    Log2(("IOMInterpretINSEx  %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
    33603359                    STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
    3361                     rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, Cpu.prefix, cbSize);
     3360                    rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->prefix, cbSize);
    33623361                }
    33633362            }
  • trunk/src/VBox/VMM/testcase/tstVMStructGC.cpp

    r20426 r20530  
    139139    GEN_CHECK_OFF(EMCPU, fForceRAW);
    140140    GEN_CHECK_OFF(EMCPU, u.achPaddingFatalLongJump);
     141    GEN_CHECK_OFF(EMCPU, DisState);
    141142    GEN_CHECK_OFF(EMCPU, StatForcedActions);
    142143    GEN_CHECK_OFF(EMCPU, StatTotalClis);
     
    158159    GEN_CHECK_OFF(IOM, pRangeLastReadR0);
    159160    GEN_CHECK_OFF(IOM, pRangeLastReadRC);
     161
     162    GEN_CHECK_SIZE(IOMCPU);
     163    GEN_CHECK_OFF(IOMCPU, DisState);
     164    GEN_CHECK_OFF(IOMCPU, Dummy[0]);
    160165
    161166    GEN_CHECK_SIZE(IOMMMIORANGE);
     
    472477    GEN_CHECK_OFF(PGMCPU, pfnRCBthVerifyAccessSyncPage);
    473478    GEN_CHECK_OFF(PGMCPU, pfnRCBthAssertCR3);
     479    GEN_CHECK_OFF(PGMCPU, DisState);
     480    GEN_CHECK_OFF(PGMCPU, cGuestModeChanges);
     481#ifdef VBOX_WITH_STATISTICS
     482    GEN_CHECK_OFF(PGMCPU, pStatTrap0eAttributionR0);
     483    GEN_CHECK_OFF(PGMCPU, pStatTrap0eAttributionRC);
     484#endif
    474485    GEN_CHECK_OFF(PGM, offVM);
    475486    GEN_CHECK_OFF(PGM, offVCpuPGM);
     
    551562    GEN_CHECK_OFF(PGM, cSharedPages);
    552563    GEN_CHECK_OFF(PGM, cZeroPages);
    553     GEN_CHECK_OFF(PGMCPU, cGuestModeChanges);
    554 #ifdef VBOX_WITH_STATISTICS
    555     GEN_CHECK_OFF(PGMCPU, pStatTrap0eAttributionR0);
    556     GEN_CHECK_OFF(PGMCPU, pStatTrap0eAttributionRC);
    557 #endif
    558564
    559565    GEN_CHECK_SIZE(PGMMAPPING);
  • trunk/src/VBox/VMM/testcase/tstVMStructSize.cpp

    r19735 r20530  
    310310    CHECK_MEMBER_ALIGNMENT(HWACCMCPU, Event.intInfo, 8);
    311311
     312    /* The various disassembler state members.  */
     313    CHECK_PADDING3(EMCPU, DisState, abDisStatePadding);
     314    CHECK_PADDING3(HWACCMCPU, DisState, abDisStatePadding);
     315    CHECK_PADDING3(IOMCPU, DisState, abDisStatePadding);
     316    CHECK_PADDING3(PGMCPU, DisState, abDisStatePadding);
     317
    312318    /* Make sure the set is large enough and has the correct size. */
    313319    CHECK_SIZE(VMCPUSET, 32);
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