Index: trunk/include/VBox/err.mac
===================================================================
--- trunk/include/VBox/err.mac	(revision 20741)
+++ trunk/include/VBox/err.mac	(revision 20742)
@@ -396,4 +396,5 @@
 %define VERR_VUSB_USBFS_PERMISSION    (-3405)
 %define VERR_VUSB_DEVICE_IS_RESETTING    (-3406)
+%define VERR_VUSB_DEVICE_IS_SUSPENDED    (-3407)
 %define VERR_VGA_INVALID_CUSTOM_MODE    (-3500)
 %define VINF_VGA_RESIZE_IN_PROGRESS    (3501)
Index: trunk/include/VBox/param.h
===================================================================
--- trunk/include/VBox/param.h	(revision 20741)
+++ trunk/include/VBox/param.h	(revision 20742)
@@ -122,5 +122,9 @@
  */
 /** VMM stack size. */
-#define VMM_STACK_SIZE              8192U
+#ifdef RT_OS_DARWIN
+# define VMM_STACK_SIZE             16384U
+#else
+# define VMM_STACK_SIZE             8192U
+#endif
 /** Min number of Virtual CPUs. */
 #define VMM_MIN_CPU_COUNT           1
Index: trunk/include/VBox/param.mac
===================================================================
--- trunk/include/VBox/param.mac	(revision 20741)
+++ trunk/include/VBox/param.mac	(revision 20742)
@@ -1,9 +1,21 @@
-%define VBOX_MAX_ALLOC_PAGE_COUNT   (128 * _1M / PAGE_SIZE)
+%ifndef ___VBox_param_h
+%define ___VBox_param_h
+%define VBOX_MAX_ALLOC_PAGE_COUNT   (128U * _1M / PAGE_SIZE)
 %define MM_HYPER_AREA_ADDRESS       UINT32_C(0xa0000000)
-%define MM_HYPER_AREA_MAX_SIZE      (40 * _1M)
-%define MM_HYPER_DYNAMIC_SIZE       (16 * PAGE_SIZE)
+%define MM_HYPER_AREA_MAX_SIZE      (40U * _1M)
+%define MM_HYPER_DYNAMIC_SIZE       (16U * PAGE_SIZE)
 %define MM_RAM_MIN                  UINT32_C(0x00400000)
+%if HC_ARCH_BITS == 64
+ %define MM_RAM_MAX                 UINT64_C(0x400000000)
+%else
+ %define MM_RAM_MAX                 UINT64_C(0x0E0000000)
+%endif
 %define MM_RAM_MIN_IN_MB            UINT32_C(4)
-%define MM_RAM_HOLE_SIZE_DEFAULT    (512 * _1M)
+%if HC_ARCH_BITS == 64
+ %define MM_RAM_MAX_IN_MB           UINT32_C(16384)
+%else
+ %define MM_RAM_MAX_IN_MB           UINT32_C(3584)
+%endif
+%define MM_RAM_HOLE_SIZE_DEFAULT    (512U * _1M)
 %define PGM_HANDY_PAGES             128
 %define PGM_HANDY_PAGES_SET_FF      32
@@ -12,5 +24,10 @@
 %define PGM_HANDY_PAGES_RZ_TO_R3    24
 %define PGM_HANDY_PAGES_MIN         32
-%define VMM_STACK_SIZE              8192
+%ifdef RT_OS_DARWIN
+ %define VMM_STACK_SIZE             16384
+%else
+ %define VMM_STACK_SIZE             8192
+%endif
 %define VMM_MIN_CPU_COUNT           1
 %define VMM_MAX_CPU_COUNT           32
+%endif
Index: trunk/include/VBox/various.sed
===================================================================
--- trunk/include/VBox/various.sed	(revision 20741)
+++ trunk/include/VBox/various.sed	(revision 20742)
@@ -1,8 +1,84 @@
-/___VBox_[a-zA-Z][a-zA-Z0-9]*_h/d
-/#define/!d
+
+# Check for markers (typically in comments).
+/ASM-INC/basm-inc
+/ASM-NOINC/basm-noinc
+
+# Strip comments and trailing space.
+s/[[:space:]][[:space:]]*\/\*.*$//g
+s/[[:space:]][[:space:]]*\/\/.*$//g
+s/[[:space:]][[:space:]]*$//g
+
+# Try identify the statement.
+/#[[:space:]]*define[[:space:]]/bdefine
+/#[[:space:]]*ifdef[[:space:]]/bifdef
+/#[[:space:]]*ifndef[[:space:]]/bifndef
+/#[[:space:]]*if[[:space:]]/bif
+/#[[:space:]]*elif[[:space:]]/belif
+/#[[:space:]]*else$/belse
+/#[[:space:]]*endif$/bendif
+
+# Not recognized, drop it.
+:asm-noinc
+d
+b end
+
+#
+# Defines needs some extra massaging to work in yasm.
+# Things like trailing type indicators ('U', 'ULL' ++) does not go down well.
+#
+:define
 /\$/d
-s/#define/%define/
-s/\([0-9a-fA-F][0-9a-fA-F]*\)U$/\1/
-s/\([0-9a-fA-F][0-9a-fA-F]*\)U[[:space:]]/\1 /
-s/[[:space:]]\/\*\*<.*$//
+s/#\([[:space:]]*\)define/\1%define/
 
+s/\([[:space:]]0[xX][0-9a-fA-F][0-9a-fA-F]*\)U$/\1/
+s/\([[:space:]]0[xX][0-9a-fA-F][0-9a-fA-F]*\)U\([[:space:]]*\))$/\1\2)/
+s/\([[:space:]][0-9][0-9]*\)U[[:space:]]*$/\1/
+s/\([[:space:]][0-9][0-9]*\)U\([[:space:]]*\))$/\1\2)/
+
+s/\([[:space:]]0[xX][0-9a-fA-F][0-9a-fA-F]*\)UL$/\1/
+s/\([[:space:]]0[xX][0-9a-fA-F][0-9a-fA-F]*\)UL\([[:space:]]*\))$/\1\2)/
+s/\([[:space:]][0-9][0-9]*\)UL[[:space:]]*$/\1/
+s/\([[:space:]][0-9][0-9]*\)UL\([[:space:]]*\))$/\1\2)/
+
+s/\([[:space:]]0[xX][0-9a-fA-F][0-9a-fA-F]*\)ULL$/\1/
+s/\([[:space:]]0[xX][0-9a-fA-F][0-9a-fA-F]*\)ULL\([[:space:]]*\))$/\1\2)/
+s/\([[:space:]][0-9][0-9]*\)ULL[[:space:]]*$/\1/
+s/\([[:space:]][0-9][0-9]*\)ULL\([[:space:]]*\))$/\1\2)/
+
+b end
+
+#
+# Conditional statements, 1:1.
+#
+:ifdef
+s/#\([[:space:]]*\)ifdef/\1%ifdef/
+b end
+
+:ifndef
+s/#\([[:space:]]*\)ifndef/\1%ifndef/
+b end
+
+:if
+s/#\([[:space:]]*\)if/\1%if/
+b end
+
+:elif
+s/#\([[:space:]]*\)elif/\1%elif/
+b end
+
+:else
+s/#\([[:space:]]*\)else.*$/\1%else/
+b end
+
+:endif
+s/#\([[:space:]]*\)endif.*$/\1%endif/
+b end
+
+#
+# Assembly statement... may need adjusting when used.
+#
+:asm-inc
+b end
+
+:end
+
Index: trunk/include/VBox/x86.h
===================================================================
--- trunk/include/VBox/x86.h	(revision 20741)
+++ trunk/include/VBox/x86.h	(revision 20742)
@@ -37,5 +37,5 @@
 
 /* Workaround for Solaris sys/regset.h defining CS, DS */
-#if defined(RT_OS_SOLARIS)
+#ifdef RT_OS_SOLARIS
 # undef CS
 # undef DS
@@ -2043,5 +2043,5 @@
  * Return the base address of a descriptor.
  */
-#define X86DESC_BASE(desc) \
+#define X86DESC_BASE(desc) /*ASM-NOINC*/ \
         (  ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
          | (           (desc).Gen.u8BaseHigh1  << 16) \
@@ -2051,5 +2051,5 @@
  * Return the limit of a descriptor.
  */
-#define X86DESC_LIMIT(desc) \
+#define X86DESC_LIMIT(desc) /*ASM-NOINC*/ \
         (  ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
          | (           (desc).Gen.u16LimitLow       ) )
Index: trunk/include/VBox/x86.mac
===================================================================
--- trunk/include/VBox/x86.mac	(revision 20741)
+++ trunk/include/VBox/x86.mac	(revision 20742)
@@ -1,2 +1,6 @@
+%ifndef ___VBox_x86_h
+%define ___VBox_x86_h
+%ifdef RT_OS_SOLARIS
+%endif
 %define X86_EFL_CF          RT_BIT(0)
 %define X86_EFL_PF          RT_BIT(2)
@@ -19,10 +23,10 @@
 %define X86_EFL_GET_IOPL(efl)   (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
 %define X86_EFL_POPF_BITS       (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID)
-%define X86_CPUID_VENDOR_INTEL_EBX      0x756e6547      /* Genu */
-%define X86_CPUID_VENDOR_INTEL_ECX      0x6c65746e      /* ntel */
-%define X86_CPUID_VENDOR_INTEL_EDX      0x49656e69      /* ineI */
-%define X86_CPUID_VENDOR_AMD_EBX        0x68747541      /* Auth */
-%define X86_CPUID_VENDOR_AMD_ECX        0x444d4163      /* cAMD */
-%define X86_CPUID_VENDOR_AMD_EDX        0x69746e65      /* enti */
+%define X86_CPUID_VENDOR_INTEL_EBX      0x756e6547
+%define X86_CPUID_VENDOR_INTEL_ECX      0x6c65746e
+%define X86_CPUID_VENDOR_INTEL_EDX      0x49656e69
+%define X86_CPUID_VENDOR_AMD_EBX        0x68747541
+%define X86_CPUID_VENDOR_AMD_ECX        0x444d4163
+%define X86_CPUID_VENDOR_AMD_EDX        0x69746e65
 %define X86_CPUID_FEATURE_ECX_SSE3      RT_BIT(0)
 %define X86_CPUID_FEATURE_ECX_MONITOR   RT_BIT(3)
@@ -193,5 +197,5 @@
 %define X86_DR7_LEN_DWORD                   3
 %define X86_DR7_LEN(iBp, cb)                ( (cb) << ((iBp) * 4 + 18) )
-%define X86_DR7_GET_LEN(uDR7, iBp)          ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
+%define X86_DR7_GET_LEN(uDR7, iBp)          ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3)
 %define X86_DR7_ENABLED_MASK                (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7))
 %define X86_DR7_IO_ENABLED_MASK             (X86_DR7_RW(0, X86_DR7_RW_IO) | X86_DR7_RW(1, X86_DR7_RW_IO) | X86_DR7_RW(2, X86_DR7_RW_IO) | X86_DR7_RW(3, X86_DR7_RW_IO))
@@ -199,5 +203,7 @@
 %define MSR_IA32_TSC                        0x10
 %define MSR_IA32_PLATFORM_ID                0x17
+%ifndef MSR_IA32_APICBASE
 %define MSR_IA32_APICBASE                   0x1b
+%endif
 %define MSR_IA32_FEATURE_CONTROL            0x3A
 %define MSR_IA32_FEATURE_CONTROL_LOCK       RT_BIT(0)
@@ -206,7 +212,9 @@
 %define MSR_IA32_BIOS_SIGN_ID               0x8B
 %define MSR_IA32_MTRR_CAP                   0xFE
+%ifndef MSR_IA32_SYSENTER_CS
 %define MSR_IA32_SYSENTER_CS                0x174
 %define MSR_IA32_SYSENTER_ESP               0x175
 %define MSR_IA32_SYSENTER_EIP               0x176
+%endif
 %define MSR_IA32_MCP_CAP                    0x179
 %define MSR_IA32_MCP_STATUS                 0x17A
@@ -288,15 +296,15 @@
 %define X86_PAGE_4K_SHIFT                   12
 %define X86_PAGE_4K_OFFSET_MASK             0xfff
-%define X86_PAGE_4K_BASE_MASK               0xfffffffffffff000ULL
+%define X86_PAGE_4K_BASE_MASK               0xfffffffffffff000
 %define X86_PAGE_4K_BASE_MASK_32            0xfffff000
 %define X86_PAGE_2M_SIZE                    _2M
 %define X86_PAGE_2M_SHIFT                   21
 %define X86_PAGE_2M_OFFSET_MASK             0x001fffff
-%define X86_PAGE_2M_BASE_MASK               0xffffffffffe00000ULL
+%define X86_PAGE_2M_BASE_MASK               0xffffffffffe00000
 %define X86_PAGE_2M_BASE_MASK_32            0xffe00000
 %define X86_PAGE_4M_SIZE                    _4M
 %define X86_PAGE_4M_SHIFT                   22
 %define X86_PAGE_4M_OFFSET_MASK             0x003fffff
-%define X86_PAGE_4M_BASE_MASK               0xffffffffffc00000ULL
+%define X86_PAGE_4M_BASE_MASK               0xffffffffffc00000
 %define X86_PAGE_4M_BASE_MASK_32            0xffc00000
 %define X86_PTE_BIT_P                       0
@@ -320,7 +328,10 @@
 %define X86_PTE_AVL_MASK                    (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
 %define X86_PTE_PG_MASK                     ( 0xfffff000 )
-%define X86_PTE_PAE_PG_MASK                 ( 0x0000fffffffff000ULL )
-%define X86_PTE_PAE_PG_MASK_FULL            ( 0x000ffffffffff000ULL )
-%define X86_PTE_PAE_PG_MASK                 ( 0x000ffffffffff000ULL )
+%if 1
+%define X86_PTE_PAE_PG_MASK                 ( 0x0000fffffffff000 )
+%define X86_PTE_PAE_PG_MASK_FULL            ( 0x000ffffffffff000 )
+%else
+%define X86_PTE_PAE_PG_MASK                 ( 0x000ffffffffff000 )
+%endif
 %define X86_PTE_PAE_NX                      RT_BIT_64(63)
 %define X86_PT_SHIFT                        12
@@ -337,7 +348,10 @@
 %define X86_PDE_AVL_MASK                    (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
 %define X86_PDE_PG_MASK                     ( 0xfffff000 )
-%define X86_PDE_PAE_PG_MASK                 ( 0x0000fffffffff000ULL )
-%define X86_PDE_PAE_PG_MASK_FULL            ( 0x000ffffffffff000ULL )
-%define X86_PDE_PAE_PG_MASK                 ( 0x000ffffffffff000ULL )
+%if 1
+%define X86_PDE_PAE_PG_MASK                 ( 0x0000fffffffff000 )
+%define X86_PDE_PAE_PG_MASK_FULL            ( 0x000ffffffffff000 )
+%else
+%define X86_PDE_PAE_PG_MASK                 ( 0x000ffffffffff000 )
+%endif
 %define X86_PDE_PAE_NX                      RT_BIT_64(63)
 %define X86_PDE4M_P                         RT_BIT(0)
@@ -356,5 +370,5 @@
 %define X86_PDE4M_PG_HIGH_MASK              ( 0x001fe000 )
 %define X86_PDE4M_PG_HIGH_SHIFT             19
-%define X86_PDE2M_PAE_PG_MASK               ( 0x000fffffffe00000ULL )
+%define X86_PDE2M_PAE_PG_MASK               ( 0x000fffffffe00000 )
 %define X86_PDE2M_PAE_NX                    X86_PDE2M_PAE_NX
 %define X86_PD_SHIFT                        22
@@ -369,7 +383,10 @@
 %define X86_PDPE_A                          RT_BIT(5)
 %define X86_PDPE_AVL_MASK                   (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
-%define X86_PDPE_PG_MASK                    ( 0x0000fffffffff000ULL )
-%define X86_PDPE_PG_MASK_FULL               ( 0x000ffffffffff000ULL )
-%define X86_PDPE_PG_MASK                    ( 0x000ffffffffff000ULL )
+%if 1
+%define X86_PDPE_PG_MASK                    ( 0x0000fffffffff000 )
+%define X86_PDPE_PG_MASK_FULL               ( 0x000ffffffffff000 )
+%else
+%define X86_PDPE_PG_MASK                    ( 0x000ffffffffff000 )
+%endif
 %define X86_PDPE_NX                         RT_BIT_64(63)
 %define X86_PDPT_SHIFT             30
@@ -383,12 +400,16 @@
 %define X86_PML4E_A                         RT_BIT(5)
 %define X86_PML4E_AVL_MASK                  (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
-%define X86_PML4E_PG_MASK                   ( 0x0000fffffffff000ULL )
-%define X86_PML4E_PG_MASK_FULL              ( 0x000ffffffffff000ULL )
-%define X86_PML4E_PG_MASK                   ( 0x000ffffffffff000ULL )
+%if 1
+%define X86_PML4E_PG_MASK                   ( 0x0000fffffffff000 )
+%define X86_PML4E_PG_MASK_FULL              ( 0x000ffffffffff000 )
+%else
+%define X86_PML4E_PG_MASK                   ( 0x000ffffffffff000 )
+%endif
 %define X86_PML4E_NX                        RT_BIT_64(63)
 %define X86_PML4_SHIFT              39
 %define X86_PML4_MASK               0x1ff
-%define X86DESC_BASE(desc) \
-%define X86DESC_LIMIT(desc) \
+%if HC_ARCH_BITS == 64
+%else
+%endif
 %define X86DESC64_BASE(desc) \
 %define X86_SEL_TYPE_CODE                   8
@@ -446,6 +467,9 @@
 %define X86_SEL_SHIFT       3
 %define AMD64_SEL_SHIFT     4
+%if HC_ARCH_BITS == 64
 %define X86_SEL_SHIFT_HC    AMD64_SEL_SHIFT
+%else
 %define X86_SEL_SHIFT_HC    X86_SEL_SHIFT
+%endif
 %define X86_SEL_MASK        0xfff8
 %define X86_SEL_LDT         0x0004
@@ -461,2 +485,3 @@
 %define X86_TRAP_PF_RSVD            RT_BIT(3)
 %define X86_TRAP_PF_ID              RT_BIT(4)
+%endif
