VirtualBox

Changeset 21208 in vbox for trunk/src


Ignore:
Timestamp:
Jul 3, 2009 2:38:58 PM (16 years ago)
Author:
vboxsync
Message:

Started with saving pending failed IO instructions.

Location:
trunk/src/VBox/VMM
Files:
7 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/EMHandleRCTmpl.h

    r21196 r21208  
    126126                                    PATMFL_MMIO_ACCESS | ((SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0));
    127127            if (RT_FAILURE(rc))
    128                 rc = emR3RawExecuteInstruction(pVM, pVCpu, "MMIO");
     128                rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
    129129            break;
    130130
    131131        case VINF_PATM_HC_MMIO_PATCH_WRITE:
    132132            AssertFailed(); /* not yet implemented. */
    133             rc = emR3RawExecuteInstruction(pVM, pVCpu, "MMIO");
     133            rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
    134134            break;
    135135#endif /* EMHANDLERC_WITH_PATM */
    … …  
    200200        case VINF_IOM_HC_IOPORT_READ:
    201201        case VINF_IOM_HC_IOPORT_WRITE:
    202             rc = emR3RawExecuteIOInstruction(pVM, pVCpu);
     202            rc = emR3ExecuteIOInstruction(pVM, pVCpu);
    203203            break;
    204204
    … …  
    209209        case VINF_IOM_HC_MMIO_WRITE:
    210210        case VINF_IOM_HC_MMIO_READ_WRITE:
    211             rc = emR3RawExecuteInstruction(pVM, pVCpu, "MMIO");
     211            rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
    212212            break;
    213213
    … …  
    226226         */
    227227        case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
    228             rc = emR3RawExecuteInstruction(pVM, pVCpu, "LDT FAULT: ");
     228            rc = emR3ExecuteInstruction(pVM, pVCpu, "LDT FAULT: ");
    229229            break;
    230230        case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
    231             rc = emR3RawExecuteInstruction(pVM, pVCpu, "GDT FAULT: ");
     231            rc = emR3ExecuteInstruction(pVM, pVCpu, "GDT FAULT: ");
    232232            break;
    233233        case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
    234             rc = emR3RawExecuteInstruction(pVM, pVCpu, "IDT FAULT: ");
     234            rc = emR3ExecuteInstruction(pVM, pVCpu, "IDT FAULT: ");
    235235            break;
    236236        case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
    237             rc = emR3RawExecuteInstruction(pVM, pVCpu, "TSS FAULT: ");
     237            rc = emR3ExecuteInstruction(pVM, pVCpu, "TSS FAULT: ");
    238238            break;
    239239        case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
    240             rc = emR3RawExecuteInstruction(pVM, pVCpu, "PD FAULT: ");
     240            rc = emR3ExecuteInstruction(pVM, pVCpu, "PD FAULT: ");
    241241            break;
    242242        case VINF_EM_RAW_EMULATE_INSTR_HLT:
    … …  
    248248#ifdef EMHANDLERC_WITH_PATM
    249249        case VINF_PATM_PENDING_IRQ_AFTER_IRET:
    250             rc = emR3RawExecuteInstruction(pVM, pVCpu, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
     250            rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
    251251            break;
    252252
    … …  
    256256#endif
    257257        case VINF_EM_RAW_EMULATE_INSTR:
    258             rc = emR3RawExecuteInstruction(pVM, pVCpu, "EMUL: ");
     258            rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ");
    259259            break;
    260260

  • trunk/src/VBox/VMM/EMHwaccm.cpp

    r21196 r21208  
    7878*   Internal Functions                                                         *
    7979*******************************************************************************/
    80 DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
    81 static int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
     80DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
     81static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
    8282static int emR3HwaccmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
    8383
    … …  
    181181 */
    182182#ifdef LOG_ENABLED
    183 static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
     183static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
    184184#else
    185 static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
     185static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
    186186#endif
    187187{
    … …  
    277277 * @param   rcGC        GC return code
    278278 */
    279 DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
     279DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
    280280{
    281281#ifdef LOG_ENABLED
    282     return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
     282    return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
    283283#else
    284     return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC);
     284    return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC);
    285285#endif
    286286}
    … …  
    293293 * @param   pVCpu       VMCPU handle.
    294294 */
    295 static int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
     295static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
    296296{
    297297    int         rc;
    … …  
    378378    }
    379379    STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
    380     return emR3RawExecuteInstruction(pVM, pVCpu, "IO: ");
     380    return emR3ExecuteInstruction(pVM, pVCpu, "IO: ");
    381381}
    382382

  • trunk/src/VBox/VMM/EMRaw.cpp

    r21196 r21208  
    8080*******************************************************************************/
    8181static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
    82 DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
     82DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
    8383static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu);
    8484static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret);
    8585static int emR3SingleStepExecRem(PVM pVM, uint32_t cIterations);
    8686static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu);
    87 static int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
     87static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
    8888static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu);
    8989
    … …  
    323323 */
    324324#ifdef LOG_ENABLED
    325 static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
     325static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
    326326#else
    327 static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
     327static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
    328328#endif
    329329{
    … …  
    358358    if (PATMIsPatchGCAddr(pVM, pCtx->eip))
    359359    {
    360         Log(("emR3RawExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));
     360        Log(("emR3ExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));
    361361
    362362        RTGCPTR pNewEip;
    … …  
    369369             */
    370370            case VINF_SUCCESS:
    371                 Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
     371                Log(("emR3ExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
    372372                     pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
    373373                pCtx->eip = pNewEip;
    … …  
    380380                     */
    381381                    Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
    382                     return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
     382                    return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
    383383                }
    384384                else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
    385385                {
    386386                    /* special case: iret, that sets IF,  detected a pending irq/event */
    387                     return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIRET");
     387                    return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIRET");
    388388                }
    389389                return VINF_EM_RESCHEDULE_REM;
    … …  
    393393             */
    394394            case VINF_PATCH_EMULATE_INSTR:
    395                 Log(("emR3RawExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
     395                Log(("emR3ExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
    396396                     pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
    397397                pCtx->eip = pNewEip;
    398                 return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
     398                return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
    399399
    400400            /*
    … …  
    402402             */
    403403            case VERR_PATCH_DISABLED:
    404                 Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
     404                Log(("emR3ExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
    405405                     pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
    406406                pCtx->eip = pNewEip;
    … …  
    411411                     */
    412412                    Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
    413                     return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
     413                    return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
    414414                }
    415415                return VINF_EM_RESCHEDULE_REM;
    … …  
    486486 * @param   rcGC        GC return code
    487487 */
    488 DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
     488DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
    489489{
    490490#ifdef LOG_ENABLED
    491     return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
     491    return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
    492492#else
    493     return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC);
     493    return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC);
    494494#endif
    495495}
    … …  
    502502 * @param   pVCpu       VMCPU handle.
    503503 */
    504 static int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
     504static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
    505505{
    506506    int         rc;
    … …  
    586586    }
    587587    STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
    588     return emR3RawExecuteInstruction(pVM, pVCpu, "IO: ");
     588    return emR3ExecuteInstruction(pVM, pVCpu, "IO: ");
    589589}
    590590
    … …  
    702702                    return rc;
    703703                }
    704                 return emR3RawExecuteInstruction(pVM, pVCpu, "Monitor: ");
     704                return emR3ExecuteInstruction(pVM, pVCpu, "Monitor: ");
    705705            }
    706706        }
    … …  
    724724            rc = TRPMResetTrap(pVCpu);
    725725            AssertRC(rc);
    726             return emR3RawExecuteInstruction(pVM, pVCpu, "IO Guest Trap: ");
     726            return emR3ExecuteInstruction(pVM, pVCpu, "IO Guest Trap: ");
    727727        }
    728728    }
    … …  
    809809
    810810    /* go to the REM to emulate a single instruction */
    811     return emR3RawExecuteInstruction(pVM, pVCpu, "RSWITCH: ");
     811    return emR3ExecuteInstruction(pVM, pVCpu, "RSWITCH: ");
    812812}
    813813
    … …  
    947947                    /* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
    948948
    949                     return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
     949                    return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
    950950                    /* Interrupts are enabled; just go back to the original instruction.
    951951                    return VINF_SUCCESS; */
    … …  
    962962                pCtx->eip = pNewEip;
    963963                AssertRelease(pCtx->eip);
    964                 return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHEMUL: ");
     964                return emR3ExecuteInstruction(pVM, pVCpu, "PATCHEMUL: ");
    965965
    966966            /*
    … …  
    979979                     */
    980980                    Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
    981                     return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
     981                    return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
    982982                }
    983983                return VINF_EM_RESCHEDULE_REM;
    … …  
    12421242        return emR3PatchTrap(pVM, pVCpu, pCtx, VINF_PATM_PATCH_TRAP_GP);
    12431243
    1244     return emR3RawExecuteInstruction(pVM, pVCpu, "PRIV");
     1244    return emR3ExecuteInstruction(pVM, pVCpu, "PRIV");
    12451245}
    12461246

  • trunk/src/VBox/VMM/HWACCMInternal.h

    r21001 r21208  
    168168    uint64_t            u;
    169169} VMX_CAPABILITY;
     170
     171typedef enum
     172{
     173    HWACCMPENDINGIO_INVALID = 0,
     174    HWACCMPENDINGIO_PORT_READ,
     175    HWACCMPENDINGIO_PORT_WRITE,
     176    HWACCMPENDINGIO_STRING_READ,
     177    HWACCMPENDINGIO_STRING_WRITE,
     178    /** The usual 32-bit paranoia. */
     179    HWACCMPENDINGIO_32BIT_HACK   = 0x7fffffff
     180} HWACCMPENDINGIO;
    170181
    171182/**
    … …  
    582593        uint64_t                cr0;
    583594    } EmulateIoBlock;
     595
     596    struct
     597    {
     598        /* Pending IO operation type. */
     599        HWACCMPENDINGIO         enmType;
     600        uint32_t                uPadding;
     601        union
     602        {
     603            struct
     604            {
     605                RTGCPTR         rip;
     606                unsigned        uPort;
     607                unsigned        uAndVal;
     608                unsigned        cbSize;
     609            } Read;
     610            struct
     611            {
     612                RTGCPTR         rip;
     613                unsigned        uPort;
     614                unsigned        uValue;
     615                unsigned        cbSize;
     616            } Write;
     617            uint64_t            aRaw[4];
     618        } Port;
     619    } PendingIO;
    584620
    585621    /** Currenty shadow paging mode. */

  • trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp

    r20981 r21208  
    12181218
    12191219    return 0;
     1220}
     1221
     1222/**
     1223 * Save a pending IO read.
     1224 *
     1225 * @param   pVCpu           The VMCPU to operate on.
     1226 * @param   GCPtrRIP        Address of IO instruction
     1227 * @param   uPort           Port address
     1228 * @param   uAndVal         And mask for saving the result in eax
     1229 * @param   cbSize          Read size
     1230 */
     1231VMMR0DECL(void) HWACCMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRIP, unsigned uPort, unsigned uAndVal, unsigned cbSize)
     1232{
     1233    pVCpu->hwaccm.s.PendingIO.enmType       = HWACCMPENDINGIO_PORT_READ;
     1234    pVCpu->hwaccm.s.PendingIO.Port.Read.rip      = GCPtrRIP;
     1235    pVCpu->hwaccm.s.PendingIO.Port.Read.uPort    = uPort;
     1236    pVCpu->hwaccm.s.PendingIO.Port.Read.uAndVal  = uAndVal;
     1237    pVCpu->hwaccm.s.PendingIO.Port.Read.cbSize   = cbSize;
     1238    return;
     1239}
     1240
     1241/**
     1242 * Save a pending IO write.
     1243 *
     1244 * @param   pVCpu           The VMCPU to operate on.
     1245 * @param   GCPtrRIP        Address of IO instruction
     1246 * @param   uPort           Port address
     1247 * @param   uValue          Value to write
     1248 * @param   cbSize          Read size
     1249 */
     1250VMMR0DECL(void) HWACCMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRIP, unsigned uPort, unsigned uValue, unsigned cbSize)
     1251{
     1252    pVCpu->hwaccm.s.PendingIO.enmType        = HWACCMPENDINGIO_PORT_WRITE;
     1253    pVCpu->hwaccm.s.PendingIO.Port.Write.rip      = GCPtrRIP;
     1254    pVCpu->hwaccm.s.PendingIO.Port.Write.uPort    = uPort;
     1255    pVCpu->hwaccm.s.PendingIO.Port.Write.uValue   = uValue;
     1256    pVCpu->hwaccm.s.PendingIO.Port.Write.cbSize   = cbSize;
     1257    return;
    12201258}
    12211259

  • trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

    r21196 r21208  
    21082108                STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
    21092109                rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
     2110                if (rc == VINF_IOM_HC_IOPORT_WRITE)
     2111                    HWACCMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
    21102112            }
    21112113            else
    … …  
    21212123                    Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
    21222124                }
     2125                else
     2126                if (rc == VINF_IOM_HC_IOPORT_READ)
     2127                    HWACCMR0SavePendingIOPortRead(pVCpu, pCtx->rip, IoExitInfo.n.u16Port, uAndVal, uIOSize);
    21232128            }
    21242129        }

  • trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

    r21196 r21208  
    33913391                STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
    33923392                rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
     3393                if (rc == VINF_IOM_HC_IOPORT_WRITE)
     3394                    HWACCMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, uPort, pCtx->eax & uAndVal, cbSize);
    33933395            }
    33943396            else
    … …  
    34033405                    pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
    34043406                }
     3407                else
     3408                if (rc == VINF_IOM_HC_IOPORT_READ)
     3409                    HWACCMR0SavePendingIOPortRead(pVCpu, pCtx->rip, uPort, uAndVal, cbSize);
    34053410            }
    34063411        }
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