Changeset 21666 in vbox

Timestamp:

Jul 17, 2009 9:33:05 AM (16 years ago)

Author:

vboxsync

Message:

Allow direct access to MSRs that are automatically saved/restored with vmload/vmsave (AMD-V).

Location:

trunk/src/VBox/VMM

Files:

• HWACCM.cpp (modified) (4 diffs)
• VMMR0/HWSVMR0.cpp (modified) (4 diffs)

trunk/src/VBox/VMM/HWACCM.cpp

@@ -1494 +1494 @@
 
 /**
- * Callback to patch a TPR instruction
+ * Callback to patch a TPR instruction (vmmcall or mov cr8)
  *
  * @returns VBox status code.
@@ -1502 +1502 @@
  *
  */
-DECLCALLBACK(int) hwaccmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
+DECLCALLBACK(int) hwaccmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
 {
     PCPUMCTX     pCtx   = (PCPUMCTX)pvUser;
@@ -1623 +1623 @@
 
 /**
+ * Callback to patch a TPR instruction (vmmcall or mov cr8)
+ *
+ * @returns VBox status code.
+ * @param   pVM     The VM handle.
+ * @param   pVCpu   The VMCPU for the EMT we're being called on. 
+ * @param   pvUser  User specified CPU context
+ *
+ */
+DECLCALLBACK(int) hwaccmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
+{
+    PCPUMCTX     pCtx   = (PCPUMCTX)pvUser;
+    RTGCPTR      oldrip = pCtx->rip;
+    PDISCPUSTATE pDis   = &pVCpu->hwaccm.s.DisState;
+    unsigned     cbOp;
+
+    Log(("Patch TPR access at %RGv\n", pCtx->rip));
+
+    int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
+    AssertRC(rc);
+    if (    rc == VINF_SUCCESS
+        &&  pDis->pCurInstr->opcode == OP_MOV)
+    {
+        if (pVM->hwaccm.s.svm.cPatches < RT_ELEMENTS(pVM->hwaccm.s.svm.aPatches))
+        {
+            uint32_t        idx = pVM->hwaccm.s.svm.cPatches;
+            PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
+
+            rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
+            AssertRC(rc);
+
+            pPatch->cbOp     = cbOp;
+
+            if (pDis->param1.flags == USE_DISPLACEMENT32)
+            {
+                /*
+                 * TPR write:
+                 *
+                 *  push ecx
+                 *  push edx
+                 *  push eax
+                 *  xor  edx, edx
+                 *  mov  eax, src_reg
+                 *  mov  ecx, MSR_K8_LSTAR (0xc0000082)
+                 *  rdmsr
+                 *  pop  eax
+                 *  pop  edx
+                 *  pop  ecx
+                 *
+                 */
+                if (pDis->param2.flags == USE_REG_GEN32)
+                {
+                    pPatch->enmType     = HWACCMTPRINSTR_WRITE_REG;
+                    pPatch->uSrcOperand = pDis->param2.base.reg_gen;
+                }
+                else
+                {
+                    Assert(pDis->param2.flags == USE_IMMEDIATE32);
+                    pPatch->enmType     = HWACCMTPRINSTR_WRITE_IMM;
+                    pPatch->uSrcOperand = pDis->param2.parval;
+                }
+//                rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
+//                AssertRC(rc);
+
+//                memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
+//                pPatch->cbNewOp = sizeof(aVMMCall);
+            }
+            else
+            {
+                /*
+                 * TPR read:
+                 *
+                 *  push ecx
+                 *  push edx
+                 *  push eax
+                 *  mov  ecx, MSR_K8_LSTAR (0xc0000082)
+                 *  rdmsr
+                 *  mov  target_reg, eax
+                 *  pop  eax
+                 *  pop  edx
+                 *  pop  ecx
+                 *
+                 */
+                Assert(pDis->param1.flags == USE_REG_GEN32);
+
+                pPatch->enmType     = HWACCMTPRINSTR_READ;
+                pPatch->uDstOperand = pDis->param1.base.reg_gen;
+
+//                rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
+//                AssertRC(rc);
+
+//                memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
+//                pPatch->cbNewOp = sizeof(aVMMCall);
+            }
+
+            pPatch->Core.Key = pCtx->eip;
+            rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
+            AssertRC(rc);
+
+            pVM->hwaccm.s.svm.cPatches++;
+            return VINF_SUCCESS;
+        }
+        return hwaccmR0EmulateTprMov(pVCpu, pDis, pCtx, cbOp);
+    }
+    return VERR_ACCESS_DENIED;
+}
+/**
  * Attempt to patch TPR mmio instructions
  *
@@ -1632 +1738 @@
 VMMR3DECL(int) HWACCMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
 {
-    int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, hwaccmR3PatchTprInstr, pCtx);
+    int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, (pVM->hwaccm.s.pGuestPatchMem) ? hwaccmR3PatchTprInstr : hwaccmR3ReplaceTprInstr, pCtx);
     AssertRC(rc);
     return rc;

trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

@@ -55 +55 @@
 static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID);
 static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
+static void svmR0SetMSRPermission(PVM pVM, unsigned ulMSR, bool fRead, bool fWrite);
 
 /*******************************************************************************
@@ -362 +363 @@
         pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
     }
+
+    /* The following MSRs are saved automatically by vmload/vmsave, so we allow the guest
+     * to modify them directly. 
+     */
+    svmR0SetMSRPermission(pVM, MSR_K8_LSTAR, true, true);
+    svmR0SetMSRPermission(pVM, MSR_K8_CSTAR, true, true);
+    svmR0SetMSRPermission(pVM, MSR_K6_STAR, true, true);
+    svmR0SetMSRPermission(pVM, MSR_K8_SF_MASK, true, true);
+    svmR0SetMSRPermission(pVM, MSR_K8_FS_BASE, true, true);
+    svmR0SetMSRPermission(pVM, MSR_K8_GS_BASE, true, true);
+    svmR0SetMSRPermission(pVM, MSR_K8_KERNEL_GS_BASE, true, true);
+    svmR0SetMSRPermission(pVM, MSR_IA32_SYSENTER_CS, true, true);
+    svmR0SetMSRPermission(pVM, MSR_IA32_SYSENTER_ESP, true, true);
+    svmR0SetMSRPermission(pVM, MSR_IA32_SYSENTER_EIP, true, true);
     return rc;
 }
 
+
+/**
+ * Sets the permission bits for the specified MSR
+ *
+ * @param   pVM         The VM to operate on.
+ * @param   ulMSR       MSR value
+ * @param   fRead       Reading allowed/disallowed
+ * @param   fWrite      Writing allowed/disallowed
+ */
+static void svmR0SetMSRPermission(PVM pVM, unsigned ulMSR, bool fRead, bool fWrite)
+{
+    unsigned ulBit;
+    uint8_t *pMSRBitmap = (uint8_t *)pVM->hwaccm.s.svm.pMSRBitmap;
+
+    if (ulMSR <= 0x00001FFF)
+    {
+        /* Pentium®-compatible MSRs */
+        ulBit    = ulMSR * 2;
+    }
+    else
+    if (    ulMSR >= 0xC0000000
+        &&  ulMSR <= 0xC0001FFF)
+    {
+        /* AMD Sixth Generation x86 Processor MSRs and SYSCALL */
+        ulBit = (ulMSR - 0xC0000000) * 2;
+        pMSRBitmap += 0x800;
+    }
+    else
+    if (    ulMSR >= 0xC0010000
+        &&  ulMSR <= 0xC0011FFF)
+    {
+        /* AMD Seventh and Eighth Generation Processor MSRs */
+        ulBit = (ulMSR - 0xC0001000) * 2;
+        pMSRBitmap += 0x1000;
+    }
+    else
+    {
+        AssertFailed();
+        return;
+    }
+    Assert(ulBit < 16 * 1024 - 1);
+    if (fRead)
+        ASMBitClear(pMSRBitmap, ulBit);
+    else
+        ASMBitSet(pMSRBitmap, ulBit);
+    
+    if (fWrite)
+        ASMBitClear(pMSRBitmap, ulBit + 1);
+    else
+        ASMBitSet(pMSRBitmap, ulBit + 1);
+}
 
 /**
@@ -1314 +1380 @@
     pCtx->rax        = pVMCB->guest.u64RAX;
 
+    /* Save all the MSRs that can be changed by the guest without causing a world switch. (fs & gs base are saved with SVM_READ_SELREG) */
+    pCtx->msrSTAR         = pVMCB->guest.u64STAR;            /* legacy syscall eip, cs & ss */
+    pCtx->msrLSTAR        = pVMCB->guest.u64LSTAR;           /* 64 bits mode syscall rip */
+    pCtx->msrCSTAR        = pVMCB->guest.u64CSTAR;           /* compatibility mode syscall rip */
+    pCtx->msrSFMASK       = pVMCB->guest.u64SFMASK;          /* syscall flag mask */
     pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase;    /* swapgs exchange value */
+    pCtx->SysEnter.cs     = pVMCB->guest.u64SysEnterCS;
+    pCtx->SysEnter.eip    = pVMCB->guest.u64SysEnterEIP;
+    pCtx->SysEnter.esp    = pVMCB->guest.u64SysEnterESP;
 
     /* Can be updated behind our back in the nested paging case. */
@@ -1326 +1400 @@
     SVM_READ_SELREG(FS, fs);
     SVM_READ_SELREG(GS, gs);
-
-    /*
-     * System MSRs
-     */
-    pCtx->SysEnter.cs       = pVMCB->guest.u64SysEnterCS;
-    pCtx->SysEnter.eip      = pVMCB->guest.u64SysEnterEIP;
-    pCtx->SysEnter.esp      = pVMCB->guest.u64SysEnterESP;
 
     /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */