Changeset 21709 in vbox

Timestamp:

Jul 17, 2009 4:07:35 PM (16 years ago)

Author:

vboxsync

Message:

Use LSTAR for TPR caching.

Location:

trunk/src/VBox/VMM

Files:

• HWACCM.cpp (modified) (4 diffs)
• HWACCMInternal.h (modified) (1 diff)
• VMMR0/HWSVMR0.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/HWACCM.cpp

@@ -1382 +1382 @@
 
     /* Clear all patch information. */
-    pVM->hwaccm.s.pGuestPatchMem      = 0;
-    pVM->hwaccm.s.pFreeGuestPatchMem  = 0;
-    pVM->hwaccm.s.cbGuestPatchMem     = 0;
-    pVM->hwaccm.s.svm.cPatches        = 0;
-    pVM->hwaccm.s.svm.PatchTree       = 0;
+    pVM->hwaccm.s.pGuestPatchMem         = 0;
+    pVM->hwaccm.s.pFreeGuestPatchMem     = 0;
+    pVM->hwaccm.s.cbGuestPatchMem        = 0;
+    pVM->hwaccm.s.svm.cPatches           = 0;
+    pVM->hwaccm.s.svm.PatchTree          = 0;
+    pVM->hwaccm.s.svm.fTPRPatchingActive = false;
     ASMMemZero32(pVM->hwaccm.s.svm.aPatches, sizeof(pVM->hwaccm.s.svm.aPatches));
 }
@@ -1443 +1444 @@
     pVM->hwaccm.s.svm.PatchTree       = 0;
     pVM->hwaccm.s.pFreeGuestPatchMem  = pVM->hwaccm.s.pGuestPatchMem;
+    pVM->hwaccm.s.svm.fTPRPatchingActive = false;
     return VINF_SUCCESS;
 }
@@ -1494 +1496 @@
     pVM->hwaccm.s.pFreeGuestPatchMem  = 0;
     pVM->hwaccm.s.cbGuestPatchMem     = 0;
+    pVM->hwaccm.s.svm.fTPRPatchingActive = false;
     return VINF_SUCCESS;
 }
@@ -1883 +1886 @@
 
                 pVM->hwaccm.s.svm.cPatches++;
+                pVM->hwaccm.s.svm.fTPRPatchingActive = true;
                 return VINF_SUCCESS;
             }

trunk/src/VBox/VMM/HWACCMInternal.h

@@ -406 +406 @@
         /** Set if erratum 170 affects the AMD cpu. */
         bool                        fAlwaysFlushTLB;
-        /** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
-         *  naturally. */
-        bool                        padding[1];
+        /** Set when TPR patching is active. */
+        bool                        fTPRPatchingActive;
 
         /** R0 memory object for the IO bitmap (12kb). */

trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

@@ -1076 +1076 @@
         int rc = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
         AssertRC(rc);
-        pVMCB->ctrl.IntCtrl.n.u8VTPR = (u8LastTPR >> 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
-
-        if (fPending)
-        {
-            /* A TPR change could activate a pending interrupt, so catch cr8 writes. */
-            pVMCB->ctrl.u16InterceptWrCRx |= RT_BIT(8);
+
+        if (pVM->hwaccm.s.svm.fTPRPatchingActive)
+        {
+            /* Our patch code uses LSTAR for TPR caching. */
+            pCtx->msrLSTAR = u8LastTPR;
         }
         else
-            /* No interrupts are pending, so we don't need to be explicitely notified.
-             * There are enough world switches for detecting pending interrupts.
-             */
-            pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
-
+        {
+            pVMCB->ctrl.IntCtrl.n.u8VTPR = (u8LastTPR >> 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
+
+            if (fPending)
+            {
+                /* A TPR change could activate a pending interrupt, so catch cr8 writes. */
+                pVMCB->ctrl.u16InterceptWrCRx |= RT_BIT(8);
+            }
+            else
+                /* No interrupts are pending, so we don't need to be explicitely notified.
+                * There are enough world switches for detecting pending interrupts.
+                */
+                pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
+        }
         fSyncTPR = !fPending;
     }
@@ -1473 +1481 @@
     /* Sync back the TPR if it was changed. */
     if (    fSyncTPR
-        &&  (u8LastTPR >> 4) != pVMCB->ctrl.IntCtrl.n.u8VTPR)
-    {
-        rc = PDMApicSetTPR(pVCpu, pVMCB->ctrl.IntCtrl.n.u8VTPR << 4);   /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
+        &&  pVM->hwaccm.s.svm.fTPRPatchingActive
+        &&  (pCtx->msrLSTAR & 0xff) != u8LastTPR)
+    {
+        /* Our patch code uses LSTAR for TPR caching. */
+        rc = PDMApicSetTPR(pVCpu, pCtx->msrLSTAR & 0xff);
         AssertRC(rc);
+    }
+    else
+    {
+        if (    fSyncTPR
+            &&  (u8LastTPR >> 4) != pVMCB->ctrl.IntCtrl.n.u8VTPR)
+        {
+            rc = PDMApicSetTPR(pVCpu, pVMCB->ctrl.IntCtrl.n.u8VTPR << 4);   /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
+            AssertRC(rc);
+        }
     }