Changeset 22079 in vbox for trunk/src/VBox/VMM
- Timestamp:
- Aug 7, 2009 4:26:25 PM (16 years ago)
- svn:sync-xref-src-repo-rev:
- 50826
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/HWACCMInternal.h
r22064 r22079 45 45 #define HWACCM_VTX_WITH_EPT 46 46 #define HWACCM_VTX_WITH_VPID 47 48 49 #if 0 50 /* Seeing somewhat random behaviour on my Nehalem system with auto-save of guest MSRs; 51 * for some strange reason the CPU doesn't save the MSRs during the VM-exit. 52 * Clearly visible with a dual VCPU configured OpenSolaris 200906 live cd VM. 53 * 54 * Note: change the assembly files when enabling this! (remove the manual auto load/save) 55 */ 56 #define VBOX_WITH_AUTO_MSR_LOAD_RESTORE 57 #endif 47 58 48 59 RT_C_DECLS_BEGIN … … 586 597 R0PTRTYPE(uint8_t *) pMSRBitmap; 587 598 599 #ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE 588 600 /** Physical address of the guest MSR load area (1 page). */ 589 601 RTHCPHYS pGuestMSRPhys; … … 599 611 /** Virtual address of the MSR load area (1 page). */ 600 612 R0PTRTYPE(uint8_t *) pHostMSR; 613 #endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */ 601 614 602 615 /* Number of automatically loaded/restored MSRs. */ -
trunk/src/VBox/VMM/VMMGC/HWACCMGCA.asm
r22040 r22079 232 232 ; * 233 233 ; */ 234 235 ; Load the guest LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs 236 ;; @todo use the automatic load feature for MSRs 237 LOADGUESTMSR MSR_K8_LSTAR, CPUMCTX.msrLSTAR 238 %if 0 ; not supported on Intel CPUs 239 LOADGUESTMSR MSR_K8_CSTAR, CPUMCTX.msrCSTAR 240 %endif 241 LOADGUESTMSR MSR_K6_STAR, CPUMCTX.msrSTAR 242 LOADGUESTMSR MSR_K8_SF_MASK, CPUMCTX.msrSFMASK 243 LOADGUESTMSR MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE 244 234 245 %ifdef VBOX_WITH_CRASHDUMP_MAGIC 235 246 mov qword [rbx + VMCSCACHE.uPos], 5 … … 297 308 298 309 pop rsi ; pCtx (needed in rsi by the macros below) 310 311 ;; @todo use the automatic load feature for MSRs 312 SAVEGUESTMSR MSR_K8_LSTAR, CPUMCTX.msrLSTAR 313 %if 0 ; not supported on Intel CPUs 314 SAVEGUESTMSR MSR_K8_CSTAR, CPUMCTX.msrCSTAR 315 %endif 316 SAVEGUESTMSR MSR_K6_STAR, CPUMCTX.msrSTAR 317 SAVEGUESTMSR MSR_K8_SF_MASK, CPUMCTX.msrSFMASK 318 SAVEGUESTMSR MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE 299 319 300 320 %ifdef VMX_USE_CACHED_VMCS_ACCESSES -
trunk/src/VBox/VMM/VMMR0/HWACCMR0Mixed.mac
r22040 r22079 414 414 %endif 415 415 416 ; Save the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs and restore the guest MSRs 417 ;; @todo use the automatic load feature for MSRs 418 LOADGUESTMSR MSR_K8_LSTAR, CPUMCTX.msrLSTAR 419 %if 0 ; not supported on Intel CPUs 420 LOADGUESTMSR MSR_K8_CSTAR, CPUMCTX.msrCSTAR 421 %endif 422 LOADGUESTMSR MSR_K6_STAR, CPUMCTX.msrSTAR 423 LOADGUESTMSR MSR_K8_SF_MASK, CPUMCTX.msrSFMASK 424 LOADGUESTMSR MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE 425 416 426 ; Save the pCtx pointer 417 427 push xSI … … 521 531 pop xSI ; pCtx (needed in rsi by the macros below) 522 532 533 ; Restore the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs 534 ;; @todo use the automatic load feature for MSRs 535 LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE 536 LOADHOSTMSREX MSR_K8_SF_MASK, CPUMCTX.msrSFMASK 537 LOADHOSTMSREX MSR_K6_STAR, CPUMCTX.msrSTAR 538 %if 0 ; not supported on Intel CPUs 539 LOADHOSTMSREX MSR_K8_CSTAR, CPUMCTX.msrCSTAR 540 %endif 541 LOADHOSTMSREX MSR_K8_LSTAR, CPUMCTX.msrLSTAR 542 523 543 %ifdef VMX_USE_CACHED_VMCS_ACCESSES 524 544 pop xDX ; saved pCache … … 569 589 pop xSI ; pCtx (needed in rsi by the macros below) 570 590 591 ; Restore the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs 592 ;; @todo use the automatic load feature for MSRs 593 LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE 594 LOADHOSTMSR MSR_K8_SF_MASK 595 LOADHOSTMSR MSR_K6_STAR 596 %if 0 ; not supported on Intel CPUs 597 LOADHOSTMSR MSR_K8_CSTAR 598 %endif 599 LOADHOSTMSR MSR_K8_LSTAR 600 571 601 %ifdef VMX_USE_CACHED_VMCS_ACCESSES 572 602 add xSP, xS ; pCache … … 592 622 593 623 pop xSI ; pCtx (needed in rsi by the macros below) 624 625 ; Restore the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs 626 ;; @todo use the automatic load feature for MSRs 627 LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE 628 LOADHOSTMSR MSR_K8_SF_MASK 629 LOADHOSTMSR MSR_K6_STAR 630 %if 0 ; not supported on Intel CPUs 631 LOADHOSTMSR MSR_K8_CSTAR 632 %endif 633 LOADHOSTMSR MSR_K8_LSTAR 594 634 595 635 %ifdef VMX_USE_CACHED_VMCS_ACCESSES -
trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp
r22063 r22079 258 258 } 259 259 260 #ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE 260 261 /* Allocate one page for the guest MSR load area (for preloading guest MSRs during the world switch). */ 261 262 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjGuestMSR, 1 << PAGE_SHIFT, true /* executable R0 mapping */); … … 277 278 pVCpu->hwaccm.s.vmx.pHostMSRPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjHostMSR, 0); 278 279 memset(pVCpu->hwaccm.s.vmx.pHostMSR, 0, PAGE_SIZE); 280 #endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */ 279 281 280 282 /* Current guest paging mode. */ … … 322 324 pVCpu->hwaccm.s.vmx.pMSRBitmapPhys = 0; 323 325 } 326 #ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE 324 327 if (pVCpu->hwaccm.s.vmx.pMemObjHostMSR != NIL_RTR0MEMOBJ) 325 328 { … … 336 339 pVCpu->hwaccm.s.vmx.pGuestMSRPhys = 0; 337 340 } 341 #endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */ 338 342 } 339 343 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ) … … 530 534 } 531 535 536 #ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE 532 537 /* Set the guest & host MSR load/store physical addresses. */ 533 538 Assert(pVCpu->hwaccm.s.vmx.pGuestMSRPhys); … … 540 545 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, pVCpu->hwaccm.s.vmx.pHostMSRPhys); 541 546 AssertRC(rc); 542 547 #endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */ 548 549 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT, 0); 550 AssertRC(rc); 551 552 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0); 553 AssertRC(rc); 554 543 555 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW) 544 556 { … … 1164 1176 AssertRC(rc); 1165 1177 1178 #ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE 1166 1179 /* Store all host MSRs in the VM-Exit load area, so they will be reloaded after the world switch back to the host. */ 1167 1180 PVMXMSR pMsr = (PVMXMSR)pVCpu->hwaccm.s.vmx.pHostMSR; … … 1181 1194 pMsr->u32IndexMSR = MSR_K6_EFER; 1182 1195 pMsr->u32Reserved = 0; 1183 # if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)1196 # if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) 1184 1197 if (CPUMIsGuestInLongMode(pVCpu)) 1185 1198 { … … 1188 1201 } 1189 1202 else 1190 # endif1203 # endif 1191 1204 pMsr->u64Value = ASMRdMsr(MSR_K6_EFER); 1192 1205 pMsr++; idxMsr++; 1193 1206 } 1194 1207 1195 # if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)1208 # if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL) 1196 1209 if (VMX_IS_64BIT_HOST_MODE()) 1197 1210 { … … 1209 1222 pMsr++; idxMsr++; 1210 1223 } 1211 # endif1224 # endif 1212 1225 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, idxMsr); 1213 1226 AssertRC(rc); 1227 #endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */ 1214 1228 1215 1229 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT; … … 1838 1852 vmxR0UpdateExceptionBitmap(pVM, pVCpu, pCtx); 1839 1853 1854 #ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE 1840 1855 /* Store all guest MSRs in the VM-Entry load area, so they will be loaded during the world switch. */ 1841 1856 PVMXMSR pMsr = (PVMXMSR)pVCpu->hwaccm.s.vmx.pGuestMSR; … … 1883 1898 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, idxMsr); 1884 1899 AssertRC(rc); 1900 #endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */ 1885 1901 1886 1902 /* Done. */ … … 2014 2030 } 2015 2031 2032 #ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE 2016 2033 /* Save the possibly changed MSRs that we automatically restore and save during a world switch. */ 2017 2034 for (unsigned i = 0; i < pVCpu->hwaccm.s.vmx.cCachedMSRs; i++) … … 2043 2060 } 2044 2061 } 2062 #endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */ 2045 2063 return VINF_SUCCESS; 2046 2064 }
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