- Timestamp:
- Apr 20, 2007 12:58:05 PM (18 years ago)
- Location:
- trunk/src/VBox/Devices
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Graphics/DevVGA.cpp
r2113 r2269 4079 4079 GCPhysAddress, GCPhysAddress + (pData->vram_size - 1), 4080 4080 vgaR3LFBAccessHandler, pData, 4081 g_DeviceVga.szR0Mod, "vgaR0LFBAccessHandler", pData->pDevInsHC->pvInstanceData HC,4081 g_DeviceVga.szR0Mod, "vgaR0LFBAccessHandler", pData->pDevInsHC->pvInstanceDataR0, 4082 4082 g_DeviceVga.szGCMod, "vgaGCLFBAccessHandler", pData->pDevInsHC->pvInstanceDataGC, 4083 4083 "VGA LFB"); -
trunk/src/VBox/Devices/PC/DevPIC.cpp
r490 r2269 992 992 pData->pPicHlpR0 = pData->pPicHlpR3->pfnGetR0Helpers(pDevIns); 993 993 994 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x20, 2, (void *)0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");994 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0"); 995 995 if (VBOX_FAILURE(rc)) 996 996 return rc; 997 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xa0, 2, (void *)1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");997 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1"); 998 998 if (VBOX_FAILURE(rc)) 999 999 return rc; … … 1022 1022 if (fR0Enabled) 1023 1023 { 1024 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d0, 1, &pData->aPics[0], 1024 RTR0PTR pDataR0 = PDMINS2DATA_R0PTR(pDevIns); 1025 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d0, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[0]), 1025 1026 "picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr"); 1026 1027 if (VBOX_FAILURE(rc)) 1027 1028 return rc; 1028 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d1, 1, &pData->aPics[1],1029 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d1, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[1]), 1029 1030 "picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr"); 1030 1031 if (VBOX_FAILURE(rc)) -
trunk/src/VBox/Devices/Storage/DevATA.cpp
r2216 r2269 4589 4589 { 4590 4590 rc2 = PDMDevHlpIOPortRegisterR0(pPciDev->pDevIns, (RTIOPORT)GCPhysAddress + i * 8, 8, 4591 (RT HCPTR)i, "ataBMDMAIOPortWrite", "ataBMDMAIOPortRead", NULL, NULL, "ATA Bus Master DMA");4591 (RTR0PTR)i, "ataBMDMAIOPortWrite", "ataBMDMAIOPortRead", NULL, NULL, "ATA Bus Master DMA"); 4592 4592 AssertRC(rc2); 4593 4593 if (rc2 < rc) … … 5784 5784 { 5785 5785 #if 1 5786 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pData->aCts[i].IOPortBase1, 8, (RT HCPTR)i,5786 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pData->aCts[i].IOPortBase1, 8, (RTR0PTR)i, 5787 5787 "ataIOPortWrite1", "ataIOPortRead1", NULL, NULL, "ATA I/O Base 1"); 5788 5788 #else 5789 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pData->aCts[i].IOPortBase1, 8, (RT HCPTR)i,5789 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pData->aCts[i].IOPortBase1, 8, (RTR0PTR)i, 5790 5790 "ataIOPortWrite1", "ataIOPortRead1", "ataIOPortWriteStr1", "ataIOPortReadStr1", "ATA I/O Base 1"); 5791 5791 #endif … … 5808 5808 if (fR0Enabled) 5809 5809 { 5810 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pData->aCts[i].IOPortBase2, 1, (RT HCPTR)i,5810 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pData->aCts[i].IOPortBase2, 1, (RTR0PTR)i, 5811 5811 "ataIOPortWrite2", "ataIOPortRead2", NULL, NULL, "ATA I/O Base 2"); 5812 5812 if (VBOX_FAILURE(rc)) -
trunk/src/VBox/Devices/testcase/tstDeviceStructSizeGC.cpp
r2246 r2269 89 89 GEN_CHECK_OFF(PDMDEVINS, pCfgHandle); 90 90 GEN_CHECK_OFF(PDMDEVINS, iInstance); 91 GEN_CHECK_OFF(PDMDEVINS, pvInstanceData HC);91 GEN_CHECK_OFF(PDMDEVINS, pvInstanceDataR3); 92 92 GEN_CHECK_OFF(PDMDEVINS, pvInstanceDataGC); 93 GEN_CHECK_OFF(PDMDEVINS, pvInstanceDataR0); 93 94 GEN_CHECK_OFF(PDMDEVINS, IBase); 94 95 GEN_CHECK_OFF(PDMDEVINS, achInstanceData);
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