Changeset 22890 in vbox for trunk/src/VBox/VMM/VMMAll
- Timestamp:
- Sep 9, 2009 11:11:31 PM (15 years ago)
- Location:
- trunk/src/VBox/VMM/VMMAll
- Files:
-
- 15 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp
r22070 r22890 1073 1073 1074 1074 if ( iLeaf == 1 1075 && pVM->cC PUs > 1)1075 && pVM->cCpus > 1) 1076 1076 { 1077 1077 /* Bits 31-24: Initial APIC ID */ … … 1311 1311 break; 1312 1312 } 1313 for ( unsigned i=0;i<pVM->cCPUs;i++)1313 for (VMCPUID i = 0; i < pVM->cCpus; i++) 1314 1314 { 1315 1315 PVMCPU pVCpu = &pVM->aCpus[i]; 1316 1317 1316 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID; 1318 1317 } … … 1431 1430 break; 1432 1431 } 1433 for ( unsigned i=0;i<pVM->cCPUs;i++)1432 for (VMCPUID i = 0; i < pVM->cCpus; i++) 1434 1433 { 1435 1434 PVMCPU pVCpu = &pVM->aCpus[i]; 1436 1437 1435 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID; 1438 1436 } -
trunk/src/VBox/VMM/VMMAll/HWACCMAll.cpp
r20981 r22890 116 116 VMCPUID idCurCpu = VMMGetCpuId(pVM); 117 117 118 for ( unsigned idCpu = 0; idCpu < pVM->cCPUs; idCpu++)118 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++) 119 119 { 120 120 PVMCPU pVCpu = &pVM->aCpus[idCpu]; … … 154 154 VMMDECL(int) HWACCMFlushTLBOnAllVCpus(PVM pVM) 155 155 { 156 if (pVM->cC PUs == 1)156 if (pVM->cCpus == 1) 157 157 return HWACCMFlushTLB(&pVM->aCpus[0]); 158 158 159 159 VMCPUID idThisCpu = VMMGetCpuId(pVM); 160 160 161 for ( unsigned idCpu = 0; idCpu < pVM->cCPUs; idCpu++)161 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++) 162 162 { 163 163 PVMCPU pVCpu = &pVM->aCpus[idCpu]; … … 231 231 VMCPUID idThisCpu = VMMGetCpuId(pVM); 232 232 233 for ( unsigned idCpu = 0; idCpu < pVM->cCPUs; idCpu++)233 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++) 234 234 { 235 235 PVMCPU pVCpu = &pVM->aCpus[idCpu]; -
trunk/src/VBox/VMM/VMMAll/IOMAll.cpp
r22493 r22890 50 50 int iomLock(PVM pVM) 51 51 { 52 Assert(pVM->cC PUs == 1 || !PGMIsLockOwner(pVM));52 Assert(pVM->cCpus == 1 || !PGMIsLockOwner(pVM)); 53 53 int rc = PDMCritSectEnter(&pVM->iom.s.EmtLock, VERR_SEM_BUSY); 54 54 return rc; -
trunk/src/VBox/VMM/VMMAll/PDMAllCritSect.cpp
r22039 r22890 493 493 PVM pVM = pCritSect->s.CTX_SUFF(pVM); 494 494 AssertPtr(pVM); 495 Assert(idCpu < pVM->cC PUs);495 Assert(idCpu < pVM->cCpus); 496 496 return pCritSect->s.Core.NativeThreadOwner == pVM->aCpus[idCpu].hNativeThread 497 497 && (pCritSect->s.Core.fFlags & PDMCRITSECT_FLAGS_PENDING_UNLOCK) == 0; -
trunk/src/VBox/VMM/VMMAll/PGMAll.cpp
r22545 r22890 460 460 # ifdef IN_RING0 461 461 /* Note: hack alert for difficult to reproduce problem. */ 462 if ( pVM->cC PUs > 1462 if ( pVM->cCpus > 1 463 463 && rc == VERR_PAGE_TABLE_NOT_PRESENT) 464 464 { … … 2518 2518 2519 2519 /* Only applies to raw mode -> 1 VPCU */ 2520 Assert(pVM->cC PUs == 1);2520 Assert(pVM->cCpus == 1); 2521 2521 PVMCPU pVCpu = &pVM->aCpus[0]; 2522 2522 -
trunk/src/VBox/VMM/VMMAll/PGMAllBth.h
r22600 r22890 856 856 uint64_t fPageShw; 857 857 rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL); 858 AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) || pVM->cC PUs > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */, ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));858 AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) || pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */, ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw)); 859 859 # endif /* VBOX_STRICT */ 860 860 STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c); … … 1729 1729 if (!PdeDst.n.u1Present) 1730 1730 { 1731 AssertMsg(pVM->cC PUs > 1, ("%Unexpected missing PDE p=%llx\n", pPdeDst, (uint64_t)PdeDst.u));1731 AssertMsg(pVM->cCpus > 1, ("%Unexpected missing PDE p=%llx\n", pPdeDst, (uint64_t)PdeDst.u)); 1732 1732 Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", GCPtrPage)); 1733 1733 return VINF_SUCCESS; /* force the instruction to be executed again. */ … … 2255 2255 else 2256 2256 /* Check for stale TLB entry; only applies to the SMP guest case. */ 2257 if ( pVM->cC PUs > 12257 if ( pVM->cCpus > 1 2258 2258 && pPdeDst->n.u1Write 2259 2259 && pPdeDst->n.u1Accessed) … … 2395 2395 else 2396 2396 /* Check for stale TLB entry; only applies to the SMP guest case. */ 2397 if ( pVM->cC PUs > 12397 if ( pVM->cCpus > 1 2398 2398 && pPteDst->n.u1Write == 1 2399 2399 && pPteDst->n.u1Accessed == 1) … … 4471 4471 4472 4472 /* Clean up the old CR3 root. */ 4473 if ( pOldShwPageCR3 4473 if ( pOldShwPageCR3 4474 4474 && pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */) 4475 4475 { -
trunk/src/VBox/VMM/VMMAll/PGMAllGst.h
r20374 r22890 484 484 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a); 485 485 486 for ( unsigned i=0;i<pVM->cCPUs;i++)486 for (VMCPUID i = 0; i < pVM->cCpus; i++) 487 487 { 488 488 PGMHVUSTATE State; … … 509 509 RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM); 510 510 511 for ( unsigned i=0;i<pVM->cCPUs;i++)511 for (VMCPUID i = 0; i < pVM->cCpus; i++) 512 512 { 513 513 PVMCPU pVCpu = &pVM->aCpus[i]; -
trunk/src/VBox/VMM/VMMAll/PGMAllHandler.cpp
r22756 r22890 1542 1542 for (unsigned iPage = 0; iPage < pVirt->cPages; iPage++, GCPtr += PAGE_SIZE) 1543 1543 { 1544 for ( unsigned i=0;i<pVM->cCPUs;i++)1544 for (VMCPUID i = 0; i < pVM->cCpus; i++) 1545 1545 { 1546 1546 PVMCPU pVCpu = &pVM->aCpus[i]; -
trunk/src/VBox/VMM/VMMAll/PGMAllMap.cpp
r21964 r22890 222 222 223 223 if ( !pgmMapAreMappingsEnabled(&pVM->pgm.s) 224 || pVM->cC PUs > 1)224 || pVM->cCpus > 1) 225 225 return; 226 226 … … 390 390 391 391 if ( !pgmMapAreMappingsEnabled(&pVM->pgm.s) 392 || pVM->cC PUs > 1)392 || pVM->cCpus > 1) 393 393 return; 394 394 … … 602 602 return; 603 603 604 Assert(pVM->cC PUs == 1);604 Assert(pVM->cCpus == 1); 605 605 606 606 /* This only applies to raw mode where we only support 1 VCPU. */ … … 636 636 */ 637 637 if ( !pgmMapAreMappingsEnabled(&pVM->pgm.s) 638 || pVM->cC PUs > 1)638 || pVM->cCpus > 1) 639 639 return VINF_SUCCESS; 640 640 … … 672 672 */ 673 673 if ( !pgmMapAreMappingsEnabled(&pVM->pgm.s) 674 || pVM->cC PUs > 1)674 || pVM->cCpus > 1) 675 675 return VINF_SUCCESS; 676 676 … … 705 705 return false; 706 706 707 Assert(pVM->cC PUs == 1);707 Assert(pVM->cCpus == 1); 708 708 709 709 /* This only applies to raw mode where we only support 1 VCPU. */ … … 801 801 return VINF_SUCCESS; 802 802 803 Assert(pVM->cC PUs == 1);803 Assert(pVM->cCpus == 1); 804 804 805 805 /* This only applies to raw mode where we only support 1 VCPU. */ -
trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp
r22788 r22890 885 885 return false; 886 886 } 887 if ( ( (pDis->param1.flags & USE_REG_GEN32) 887 if ( ( (pDis->param1.flags & USE_REG_GEN32) 888 888 || (pDis->param1.flags & USE_REG_GEN64)) 889 889 && (pDis->param1.base.reg_gen == USE_REG_ESP)) … … 1226 1226 if (fReused) 1227 1227 goto flushPage; 1228 1228 1229 1229 /* A mov instruction to change the first page table entry will be remembered so we can detect 1230 1230 * full page table changes early on. This will reduce the amount of unnecessary traps we'll take. … … 1315 1315 && !fForcedFlush 1316 1316 && pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT 1317 && ( fNotReusedNotForking 1317 && ( fNotReusedNotForking 1318 1318 || ( !pgmPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault) 1319 1319 && !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK)) … … 1362 1362 { 1363 1363 rc = PGMShwModifyPage(pVCpu, pvFault, 1, X86_PTE_RW, ~(uint64_t)X86_PTE_RW); 1364 AssertMsg(rc == VINF_SUCCESS 1364 AssertMsg(rc == VINF_SUCCESS 1365 1365 /* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */ 1366 || rc == VERR_PAGE_TABLE_NOT_PRESENT 1367 || rc == VERR_PAGE_NOT_PRESENT, 1366 || rc == VERR_PAGE_TABLE_NOT_PRESENT 1367 || rc == VERR_PAGE_NOT_PRESENT, 1368 1368 ("PGMShwModifyPage -> GCPtr=%RGv rc=%d\n", pvFault, rc)); 1369 1369 1370 1370 pgmPoolAddDirtyPage(pVM, pPool, pPage); 1371 1371 pPage->pvDirtyFault = pvFault; 1372 1372 1373 1373 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a); 1374 1374 pgmUnlock(pVM); … … 1388 1388 * interpret then. This may be a bit risky, in which case 1389 1389 * the reuse detection must be fixed. 1390 */ 1390 */ 1391 1391 rc = pgmPoolAccessHandlerFlush(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault); 1392 1392 if (rc == VINF_EM_RAW_EMULATE_INSTR && fReused) … … 1423 1423 RTHCPHYS HCPhys = -1; 1424 1424 int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys); 1425 if ( rc != VINF_SUCCESS 1425 if ( rc != VINF_SUCCESS 1426 1426 || (pShwPT->a[i].u & X86_PTE_PAE_PG_MASK) != HCPhys) 1427 1427 { … … 1555 1555 RTHCPHYS HCPhys; 1556 1556 rc = PGMShwGetPage(VMMGetCpu(pVM), pPage->pvDirtyFault, &fFlags, &HCPhys); 1557 AssertMsg( ( rc == VINF_SUCCESS 1557 AssertMsg( ( rc == VINF_SUCCESS 1558 1558 && (!(fFlags & X86_PTE_RW) || HCPhys != pPage->Core.Key)) 1559 1559 /* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */ 1560 || rc == VERR_PAGE_TABLE_NOT_PRESENT 1561 || rc == VERR_PAGE_NOT_PRESENT, 1560 || rc == VERR_PAGE_TABLE_NOT_PRESENT 1561 || rc == VERR_PAGE_NOT_PRESENT, 1562 1562 ("PGMShwGetPage -> GCPtr=%RGv rc=%d flags=%RX64\n", pPage->pvDirtyFault, rc, fFlags)); 1563 1563 #endif … … 1828 1828 1829 1829 /* 1830 * Found a usable page, flush it and return. 1830 * Found a usable page, flush it and return. 1831 1831 */ 1832 1832 return pgmPoolFlushPage(pPool, pPage); … … 2635 2635 2636 2636 /* Clear the PGM_SYNC_CLEAR_PGM_POOL flag on all VCPUs to prevent redundant flushes. */ 2637 for ( unsigned idCpu = 0; idCpu < pVM->cCPUs; idCpu++)2637 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++) 2638 2638 { 2639 2639 PVMCPU pVCpu = &pVM->aCpus[idCpu]; 2640 2641 2640 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL; 2642 2641 } … … 4911 4910 * including the root page. 4912 4911 */ 4913 for ( unsigned i=0;i<pVM->cCPUs;i++)4912 for (VMCPUID i = 0; i < pVM->cCpus; i++) 4914 4913 { 4915 4914 PVMCPU pVCpu = &pVM->aCpus[i]; … … 5067 5066 } 5068 5067 5069 for (unsigned i=0;i<pVM->cCPUs;i++) 5070 { 5071 PVMCPU pVCpu = &pVM->aCpus[i]; 5068 for (VMCPUID i = 0; i < pVM->cCpus; i++) 5069 { 5072 5070 /* 5073 5071 * Re-enter the shadowing mode and assert Sync CR3 FF. 5074 5072 */ 5073 PVMCPU pVCpu = &pVM->aCpus[i]; 5075 5074 pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu); 5076 5075 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); -
trunk/src/VBox/VMM/VMMAll/REMAll.cpp
r22707 r22890 211 211 VMMDECL(void) REMNotifyHandlerPhysicalFlushIfAlmostFull(PVM pVM, PVMCPU pVCpu) 212 212 { 213 Assert(pVM->cC PUs == 1);213 Assert(pVM->cCpus == 1); 214 214 215 215 /* -
trunk/src/VBox/VMM/VMMAll/SELMAll.cpp
r19334 r22890 56 56 VMMDECL(RTGCPTR) SELMToFlatBySel(PVM pVM, RTSEL Sel, RTGCPTR Addr) 57 57 { 58 Assert(pVM->cC PUs == 1 && !CPUMIsGuestInLongMode(VMMGetCpu(pVM))); /* DON'T USE! */58 Assert(pVM->cCpus == 1 && !CPUMIsGuestInLongMode(VMMGetCpu(pVM))); /* DON'T USE! */ 59 59 60 60 /** @todo check the limit. */ … … 835 835 VMMDECL(int) SELMValidateAndConvertCSAddrGCTrap(PVM pVM, X86EFLAGS eflags, RTSEL SelCPL, RTSEL SelCS, RTGCPTR Addr, PRTGCPTR ppvFlat, uint32_t *pcBits) 836 836 { 837 Assert(pVM->cC PUs == 1);837 Assert(pVM->cCpus == 1); 838 838 PVMCPU pVCpu = &pVM->aCpus[0]; 839 839 … … 996 996 VMMDECL(int) SELMGetRing1Stack(PVM pVM, uint32_t *pSS, PRTGCPTR32 pEsp) 997 997 { 998 Assert(pVM->cC PUs == 1);998 Assert(pVM->cCpus == 1); 999 999 PVMCPU pVCpu = &pVM->aCpus[0]; 1000 1000 -
trunk/src/VBox/VMM/VMMAll/TMAllVirtual.cpp
r22808 r22890 828 828 { 829 829 uint32_t c = ASMAtomicDecU32(&pVM->tm.s.cVirtualTicking); 830 AssertMsgReturn(c < pVM->cC PUs, ("%u vs %u\n", c, pVM->cCPUs), VERR_INTERNAL_ERROR);830 AssertMsgReturn(c < pVM->cCpus, ("%u vs %u\n", c, pVM->cCpus), VERR_INTERNAL_ERROR); 831 831 if (c == 0) 832 832 { … … 848 848 { 849 849 uint32_t c = ASMAtomicIncU32(&pVM->tm.s.cVirtualTicking); 850 AssertMsgReturn(c <= pVM->cC PUs, ("%u vs %u\n", c, pVM->cCPUs), VERR_INTERNAL_ERROR);850 AssertMsgReturn(c <= pVM->cCpus, ("%u vs %u\n", c, pVM->cCpus), VERR_INTERNAL_ERROR); 851 851 if (c == 1) 852 852 { -
trunk/src/VBox/VMM/VMMAll/TRPMAll.cpp
r20840 r22890 366 366 PVM pVM = pVCpu->CTX_SUFF(pVM); 367 367 X86EFLAGS eflags; 368 Assert(pVM->cC PUs == 1);368 Assert(pVM->cCpus == 1); 369 369 370 370 STAM_PROFILE_ADV_START(&pVM->trpm.s.CTX_SUFF_Z(StatForwardProf), a); -
trunk/src/VBox/VMM/VMMAll/VMMAll.cpp
r22823 r22890 65 65 66 66 #elif defined(IN_RING0) 67 if (pVM->cC PUs == 1)67 if (pVM->cCpus == 1) 68 68 return 0; 69 69 return HWACCMR0GetVMCPUId(pVM); … … 88 88 if (idCpu == NIL_VMCPUID) 89 89 return NULL; 90 Assert(idCpu < pVM->cC PUs);90 Assert(idCpu < pVM->cCpus); 91 91 return &pVM->aCpus[VMR3GetVMCPUId(pVM)]; 92 92 93 93 #elif defined(IN_RING0) 94 if (pVM->cC PUs == 1)94 if (pVM->cCpus == 1) 95 95 return &pVM->aCpus[0]; 96 96 return HWACCMR0GetVMCPU(pVM); … … 110 110 VMMDECL(PVMCPU) VMMGetCpu0(PVM pVM) 111 111 { 112 Assert(pVM->cC PUs == 1);112 Assert(pVM->cCpus == 1); 113 113 return &pVM->aCpus[0]; 114 114 } … … 125 125 VMMDECL(PVMCPU) VMMGetCpuById(PVM pVM, RTCPUID idCpu) 126 126 { 127 AssertReturn(idCpu < pVM->cC PUs, NULL);127 AssertReturn(idCpu < pVM->cCpus, NULL); 128 128 return &pVM->aCpus[idCpu]; 129 129 }
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