- Timestamp:
- Sep 23, 2009 11:56:01 AM (15 years ago)
- Location:
- trunk
- Files:
-
- 3 edited
-
include/VBox/pci.h (modified) (1 diff)
-
src/VBox/Devices/Bus/DevPCI.cpp (modified) (9 diffs)
-
src/VBox/Devices/Bus/PCIInternal.h (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/pci.h
r21217 r23253 199 199 union 200 200 { 201 #ifdef __PCIDEVICEINT_DECLARED__201 #ifdef PCIDEVICEINT_DECLARED 202 202 PCIDEVICEINT s; 203 203 #endif -
trunk/src/VBox/Devices/Bus/DevPCI.cpp
r23186 r23253 933 933 /* VGA: map frame buffer to default Bochs VBE address */ 934 934 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0xE0000000); 935 /* 935 /* 936 936 * Legacy VGA I/O ports are implicitly decoded by a VGA class device. But 937 937 * only the framebuffer (i.e., a memory region) is explicitly registered via … … 1258 1258 1259 1259 /** 1260 * Common worker for pciR3SaveExec and pcibridgeR3SaveExec. 1261 * 1262 * @returns VBox status code. 1263 * @param pBus The bus to save. 1264 * @param pSSM The saved state handle. 1265 */ 1266 static int pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM) 1267 { 1268 /* 1269 * Iterate thru all the devices. 1270 */ 1271 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++) 1272 { 1273 PPCIDEVICE pDev = pBus->devices[i]; 1274 if (pDev) 1275 { 1276 SSMR3PutU32(pSSM, i); 1277 SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config)); 1278 1279 int rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState); 1280 if (RT_FAILURE(rc)) 1281 return rc; 1282 } 1283 } 1284 return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */ 1285 } 1286 1287 1288 /** 1260 1289 * Saves a state of the PCI device. 1261 1290 * … … 1269 1298 uint32_t i; 1270 1299 PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS); 1271 PPCIBUS pBus = &pThis->PciBus;1272 1300 1273 1301 /* … … 1291 1319 1292 1320 /* 1293 * Iterate thru all the devices. 1294 */ 1295 for (i = 0; i < RT_ELEMENTS(pBus->devices); i++) 1296 { 1297 PPCIDEVICE pDev = pBus->devices[i]; 1298 if (pDev) 1299 { 1300 int rc; 1301 SSMR3PutU32(pSSMHandle, i); 1302 SSMR3PutMem(pSSMHandle, pDev->config, sizeof(pDev->config)); 1303 1304 rc = SSMR3PutS32(pSSMHandle, pDev->Int.s.uIrqPinState); 1305 if (RT_FAILURE(rc)) 1306 return rc; 1307 } 1308 } 1309 return SSMR3PutU32(pSSMHandle, ~0); /* terminator */ 1321 * Join paths with pcibridgeR3SaveExec. 1322 */ 1323 return pciR3CommonSaveExec(&pThis->PciBus, pSSMHandle); 1310 1324 } 1311 1325 … … 1522 1536 1523 1537 /** 1524 * Loads a saved PCI device state.1538 * Common worker for pciR3LoadExec and pcibridgeR3LoadExec. 1525 1539 * 1526 1540 * @returns VBox status code. 1527 * @param pDevIns The device instance. 1528 * @param pSSMHandle The handle to the saved state. 1529 * @param uVersion The data unit version number. 1530 * @param uPass The data pass. 1531 */ 1532 static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t uVersion, uint32_t uPass) 1533 { 1534 PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS); 1535 PPCIBUS pBus = &pThis->PciBus; 1541 * @param pBus The bus which data is being loaded. 1542 * @param pSSMHandle The saved state handle. 1543 * @param uVersion The data version. 1544 * @param uPass The pass. 1545 */ 1546 static DECLCALLBACK(int) pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSMHandle, uint32_t uVersion, uint32_t uPass) 1547 { 1536 1548 uint32_t u32; 1537 1549 uint32_t i; 1538 1550 int rc; 1539 1551 1540 /*1541 * Check the version.1542 */1543 if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)1544 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;1545 1552 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass); 1546 1547 /*1548 * Bus state data.1549 */1550 SSMR3GetU32(pSSMHandle, &pThis->uConfigReg);1551 if (uVersion > 1)1552 SSMR3GetBool(pSSMHandle, &pThis->fUseIoApic);1553 1554 /* Load IRQ states. */1555 if (uVersion > 2)1556 {1557 for (uint8_t i = 0; i < PCI_IRQ_PINS; i++)1558 SSMR3GetU32(pSSMHandle, (uint32_t *)&pThis->pci_irq_levels[i]);1559 for (uint8_t i = 0; i < PCI_APIC_IRQ_PINS; i++)1560 SSMR3GetU32(pSSMHandle, (uint32_t *)&pThis->pci_apic_irq_levels[i]);1561 1562 SSMR3GetU32(pSSMHandle, &pThis->acpi_irq_level);1563 SSMR3GetS32(pSSMHandle, &pThis->acpi_irq);1564 }1565 1566 /* separator */1567 rc = SSMR3GetU32(pSSMHandle, &u32);1568 if (RT_FAILURE(rc))1569 return rc;1570 if (u32 != (uint32_t)~0)1571 AssertMsgFailedReturn(("u32=%#x\n", u32), rc);1572 1553 1573 1554 /* … … 1604 1585 } 1605 1586 1606 /* Get the data */1587 /* get the data */ 1607 1588 DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */ 1608 1589 SSMR3GetMem(pSSMHandle, DevTmp.config, sizeof(DevTmp.config)); … … 1649 1630 1650 1631 return VINF_SUCCESS; 1632 } 1633 1634 1635 /** 1636 * Loads a saved PCI device state. 1637 * 1638 * @returns VBox status code. 1639 * @param pDevIns The device instance. 1640 * @param pSSMHandle The handle to the saved state. 1641 * @param uVersion The data unit version number. 1642 * @param uPass The data pass. 1643 */ 1644 static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t uVersion, uint32_t uPass) 1645 { 1646 PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS); 1647 PPCIBUS pBus = &pThis->PciBus; 1648 uint32_t u32; 1649 uint32_t i; 1650 int rc; 1651 1652 /* 1653 * Check the version. 1654 */ 1655 if (uVersion > VBOX_PCI_SAVED_STATE_VERSION) 1656 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION; 1657 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass); 1658 1659 /* 1660 * Bus state data. 1661 */ 1662 SSMR3GetU32(pSSMHandle, &pThis->uConfigReg); 1663 if (uVersion > 1) 1664 SSMR3GetBool(pSSMHandle, &pThis->fUseIoApic); 1665 1666 /* Load IRQ states. */ 1667 if (uVersion > 2) 1668 { 1669 for (uint8_t i = 0; i < PCI_IRQ_PINS; i++) 1670 SSMR3GetU32(pSSMHandle, (uint32_t *)&pThis->pci_irq_levels[i]); 1671 for (uint8_t i = 0; i < PCI_APIC_IRQ_PINS; i++) 1672 SSMR3GetU32(pSSMHandle, (uint32_t *)&pThis->pci_apic_irq_levels[i]); 1673 1674 SSMR3GetU32(pSSMHandle, &pThis->acpi_irq_level); 1675 SSMR3GetS32(pSSMHandle, &pThis->acpi_irq); 1676 } 1677 1678 /* separator */ 1679 rc = SSMR3GetU32(pSSMHandle, &u32); 1680 if (RT_FAILURE(rc)) 1681 return rc; 1682 if (u32 != (uint32_t)~0) 1683 AssertMsgFailedReturn(("u32=%#x\n", u32), rc); 1684 1685 /* 1686 * The devices. 1687 */ 1688 return pciR3CommonLoadExec(pBus, pSSMHandle, uVersion, uPass); 1651 1689 } 1652 1690 … … 2284 2322 static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle) 2285 2323 { 2286 /** @todo make common with pciR3SaveExec! */2287 uint32_t i;2288 2324 PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS); 2289 2290 /* 2291 * Iterate all the devices. 2292 */ 2293 for (i = 0; i < RT_ELEMENTS(pThis->devices); i++) 2294 { 2295 PPCIDEVICE pDev = pThis->devices[i]; 2296 if (pDev) 2297 { 2298 int rc; 2299 SSMR3PutU32(pSSMHandle, i); 2300 SSMR3PutMem(pSSMHandle, pDev->config, sizeof(pDev->config)); 2301 2302 rc = SSMR3PutS32(pSSMHandle, pDev->Int.s.uIrqPinState); 2303 if (RT_FAILURE(rc)) 2304 return rc; 2305 } 2306 } 2307 return SSMR3PutU32(pSSMHandle, ~0); /* terminator */ 2325 return pciR3CommonSaveExec(pThis, pSSMHandle); 2308 2326 } 2309 2327 … … 2336 2354 static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t uVersion, uint32_t uPass) 2337 2355 { 2338 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS); 2339 uint32_t u32; 2340 uint32_t i; 2341 int rc; 2342 2343 /** @todo r=bird: this is a copy of pciR3LoadExec. combine the two! */ 2344 2345 /* 2346 * Check the version. 2347 */ 2356 PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS); 2348 2357 if (uVersion > VBOX_PCI_SAVED_STATE_VERSION) 2349 2358 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION; 2350 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass); 2351 2352 /* 2353 * Iterate all the devices. 2354 */ 2355 for (i = 0;; i++) 2356 { 2357 PCIDEVICE DevTmp; 2358 PPCIDEVICE pDev; 2359 2360 /* index / terminator */ 2361 rc = SSMR3GetU32(pSSMHandle, &u32); 2362 if (RT_FAILURE(rc)) 2363 return rc; 2364 if (u32 == (uint32_t)~0) 2365 break; 2366 if ( u32 >= RT_ELEMENTS(pBus->devices) 2367 || u32 < i) 2368 { 2369 AssertMsgFailed(("u32=%#x i=%#x\n", u32, i)); 2370 return rc; 2371 } 2372 2373 /* skip forward to the device checking that no new devices are present. */ 2374 for (; i < u32; i++) 2375 { 2376 if (pBus->devices[i]) 2377 { 2378 LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pBus->devices[i]->name, 2379 PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i]))); 2380 if (SSMR3HandleGetAfter(pSSMHandle) != SSMAFTER_DEBUG_IT) 2381 AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH); 2382 } 2383 } 2384 2385 /* get the data */ 2386 DevTmp.Int.s.uIrqPinState = 0; 2387 SSMR3GetMem(pSSMHandle, DevTmp.config, sizeof(DevTmp.config)); 2388 rc = SSMR3GetS32(pSSMHandle, &DevTmp.Int.s.uIrqPinState); 2389 if (RT_FAILURE(rc)) 2390 return rc; 2391 2392 /* check that it's still around. */ 2393 pDev = pBus->devices[i]; 2394 if (!pDev) 2395 { 2396 LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i, 2397 PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp))); 2398 if (SSMR3HandleGetAfter(pSSMHandle) != SSMAFTER_DEBUG_IT) 2399 AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH); 2400 continue; 2401 } 2402 2403 /* match the vendor id assuming that this will never be changed. */ 2404 if ( DevTmp.config[0] != pDev->config[0] 2405 || DevTmp.config[1] != pDev->config[1]) 2406 { 2407 LogRel(("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs\n", 2408 i, pDev->name, DevTmp.config, pDev->config)); 2409 AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH); 2410 } 2411 2412 /* commit the loaded device config. */ 2413 pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */ 2414 2415 pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState; 2416 } 2417 2418 return VINF_SUCCESS; 2359 return pciR3CommonLoadExec(pThis, pSSMHandle, uVersion, uPass); 2419 2360 } 2420 2361 -
trunk/src/VBox/Devices/Bus/PCIInternal.h
r13217 r23253 98 98 * If clear the device and it's functions can be relocated to satisfy the slot request of another device. */ 99 99 bool fRequestedDevFn; 100 /** Flag whether the device is a pci-to-pci bridge. */ 100 /** Flag whether the device is a pci-to-pci bridge. 101 * This is set prior to device registration. */ 101 102 bool fPciToPciBridge; 102 103 /** Current state of the IRQ pin of the device. */ … … 115 116 116 117 /* Indicate that PCIDEVICE::Int.s can be declared. */ 117 #define __PCIDEVICEINT_DECLARED__118 #define PCIDEVICEINT_DECLARED 118 119 119 120 #endif
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