Changeset 23283 in vbox

Timestamp:

Sep 24, 2009 1:05:02 PM (15 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

52771

Message:

Use atomic operations to update page table entries.

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• PGMAllBth.h (modified) (3 diffs)
• PGMAllPool.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

@@ -2239 +2239 @@
                 if (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY)
                 {
+                    SHWPDE PdeDst = *pPdeDst;
+
                     STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
-                    Assert(pPdeSrc->b.u1Write);
+                    Assert(PdeDst.b.u1Write);
 
                     /* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
                      *       fault again and take this path to only invalidate the entry.
                      */
-                    pPdeDst->n.u1Write      = 1;
-                    pPdeDst->n.u1Accessed   = 1;
-                    pPdeDst->au32[0]       &= ~PGM_PDFLAGS_TRACK_DIRTY;
+                    PdeDst.n.u1Write      = 1;
+                    PdeDst.n.u1Accessed   = 1;
+                    PdeDst.au32[0]       &= ~PGM_PDFLAGS_TRACK_DIRTY;
+                    ASMAtomicWriteSize(pPdeDst, PdeDst.u);
                     PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
                     STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
@@ -2369 +2372 @@
                         if (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY)
                         {
-                            PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
+                            PPGMPAGE pPage  = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
+                            SHWPTE   PteDst = *pPteDst;
 
                             LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
                             STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
 
-                            Assert(pPteSrc->n.u1Write);
+                            Assert(PteDst.n.u1Write);
 
                             /* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
@@ -2383 +2387 @@
                             {
                                 /* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
-                                pPteDst->n.u1Write    = 0;
+                                PteDst.n.u1Write    = 0;
                             }
                             else
-                                pPteDst->n.u1Write    = 1;
-
-                            pPteDst->n.u1Dirty    = 1;
-                            pPteDst->n.u1Accessed = 1;
-                            pPteDst->au32[0]     &= ~PGM_PTFLAGS_TRACK_DIRTY;
+                                PteDst.n.u1Write    = 1;
+
+                            PteDst.n.u1Dirty    = 1;
+                            PteDst.n.u1Accessed = 1;
+                            PteDst.au32[0]     &= ~PGM_PTFLAGS_TRACK_DIRTY;
+                            ASMAtomicWriteSize(pPteDst, PteDst.u);
                             PGM_INVL_PG(pVCpu, GCPtrPage);
 

trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp

@@ -3195 +3195 @@
                 if ((pPT->a[i].u & (X86_PTE_PG_MASK | X86_PTE_P)) == u32)
                 {
+                    X86PTE Pte;
+
                     Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32 cRefs=%#x\n", i, pPT->a[i], cRefs));
-                    pPT->a[i].u = (pPT->a[i].u & u32AndMask) | u32OrMask;
-                    if (pPT->a[i].u & PGM_PTFLAGS_TRACK_DIRTY)
-                        pPT->a[i].n.u1Write = 0;    /* need to disallow writes when dirty bit tracking is still active. */
-
+                    Pte.u = (pPT->a[i].u & u32AndMask) | u32OrMask;
+                    if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
+                        Pte.n.u1Write = 0;    /* need to disallow writes when dirty bit tracking is still active. */
+
+                    ASMAtomicWriteSize(&pPT->a[i].u, Pte.u);
                     cRefs--;
                     if (!cRefs)
@@ -3258 +3261 @@
                 if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P)) == u64)
                 {
+                    X86PTEPAE Pte;
+
                     Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
-                    pPT->a[i].u = (pPT->a[i].u & u64AndMask) | u64OrMask;
-                    if (pPT->a[i].u & PGM_PTFLAGS_TRACK_DIRTY)
-                        pPT->a[i].n.u1Write = 0;    /* need to disallow writes when dirty bit tracking is still active. */
-
+                    Pte.u = (pPT->a[i].u & u64AndMask) | u64OrMask;
+                    if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
+                        Pte.n.u1Write = 0;    /* need to disallow writes when dirty bit tracking is still active. */
+
+                    ASMAtomicWriteSize(&pPT->a[i].u, Pte.u);
                     cRefs--;
                     if (!cRefs)