Changeset 23986 in vbox
- Timestamp:
- Oct 22, 2009 2:36:13 PM (15 years ago)
- svn:sync-xref-src-repo-rev:
- 53819
- Location:
- trunk/src/VBox/Devices/PC
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/PC/DevAPIC.cpp
r23900 r23986 2354 2354 #ifdef IN_RING3 2355 2355 2356 /* Print a 8-dword LAPIC bit map (256 bits). */ 2357 static void lapicDumpVec(APICDeviceInfo *dev, APICState *lapic, PCDBGFINFOHLP pHlp, unsigned start) 2358 { 2359 unsigned i; 2360 uint32_t val; 2361 2362 for (i = 0; i < 8; ++i) 2363 { 2364 val = apic_mem_readl(dev, lapic, start + (i << 4)); 2365 pHlp->pfnPrintf(pHlp, "%08X", val); 2366 } 2367 pHlp->pfnPrintf(pHlp, "\n"); 2368 } 2369 2370 /* Print basic LAPIC state. */ 2371 static DECLCALLBACK(void) lapicInfoBasic(APICDeviceInfo *dev, APICState *lapic, PCDBGFINFOHLP pHlp) 2372 { 2373 uint32_t val; 2374 unsigned max_lvt; 2375 2376 pHlp->pfnPrintf(pHlp, "Local APIC at %08X:\n", lapic->apicbase); 2377 val = apic_mem_readl(dev, lapic, 0x20); 2378 pHlp->pfnPrintf(pHlp, " LAPIC ID : %08X\n", val); 2379 pHlp->pfnPrintf(pHlp, " APIC ID = %02X\n", (val >> 24) & 0xff); 2380 val = apic_mem_readl(dev, lapic, 0x30); 2381 max_lvt = (val >> 16) & 0xff; 2382 pHlp->pfnPrintf(pHlp, " APIC VER : %08X\n", val); 2383 pHlp->pfnPrintf(pHlp, " version = %02X\n", val & 0xff); 2384 pHlp->pfnPrintf(pHlp, " lvts = %d\n", ((val >> 16) & 0xff) + 1); 2385 val = apic_mem_readl(dev, lapic, 0x80); 2386 pHlp->pfnPrintf(pHlp, " TPR : %08X\n", val); 2387 pHlp->pfnPrintf(pHlp, " task pri = %d/%d\n", (val >> 4) & 0xf, val & 0xf); 2388 val = apic_mem_readl(dev, lapic, 0xA0); 2389 pHlp->pfnPrintf(pHlp, " PPR : %08X\n", val); 2390 pHlp->pfnPrintf(pHlp, " cpu pri = %d/%d\n", (val >> 4) & 0xf, val & 0xf); 2391 val = apic_mem_readl(dev, lapic, 0xD0); 2392 pHlp->pfnPrintf(pHlp, " LDR : %08X\n", val); 2393 pHlp->pfnPrintf(pHlp, " log id = %02X\n", (val >> 24) & 0xff); 2394 val = apic_mem_readl(dev, lapic, 0xE0); 2395 pHlp->pfnPrintf(pHlp, " DFR : %08X\n", val); 2396 val = apic_mem_readl(dev, lapic, 0xF0); 2397 pHlp->pfnPrintf(pHlp, " SVR : %08X\n", val); 2398 pHlp->pfnPrintf(pHlp, " focus = %s\n", val & (1 << 9) ? "check off" : "check on"); 2399 pHlp->pfnPrintf(pHlp, " lapic = %s\n", val & (1 << 8) ? "ENABLED" : "DISABLED"); 2400 pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff); 2401 pHlp->pfnPrintf(pHlp, " ISR : "); 2402 lapicDumpVec(dev, lapic, pHlp, 0x100); 2403 val = get_highest_priority_int(lapic->isr); 2404 pHlp->pfnPrintf(pHlp, " highest = %02X\n", val == ~0 ? 0 : val); 2405 pHlp->pfnPrintf(pHlp, " IRR : "); 2406 lapicDumpVec(dev, lapic, pHlp, 0x200); 2407 val = get_highest_priority_int(lapic->irr); 2408 pHlp->pfnPrintf(pHlp, " highest = %02X\n", val == ~0 ? 0 : val); 2409 val = apic_mem_readl(dev, lapic, 0x320); 2410 } 2411 2412 /* Print the more interesting LAPIC LVT entries. */ 2413 static DECLCALLBACK(void) lapicInfoLVT(APICDeviceInfo *dev, APICState *lapic, PCDBGFINFOHLP pHlp) 2414 { 2415 uint32_t val; 2416 static char *dmodes[] = { "Fixed ", "Reserved", "SMI", "Reserved", 2417 "NMI", "INIT", "Reserved", "ExtINT" }; 2418 2419 val = apic_mem_readl(dev, lapic, 0x320); 2420 pHlp->pfnPrintf(pHlp, " LVT Timer : %08X\n", val); 2421 pHlp->pfnPrintf(pHlp, " mode = %s\n", val & (1 << 17) ? "periodic" : "one-shot"); 2422 pHlp->pfnPrintf(pHlp, " mask = %d\n", (val >> 16) & 1); 2423 pHlp->pfnPrintf(pHlp, " status = %s\n", val & (1 << 12) ? "pending" : "idle"); 2424 pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff); 2425 val = apic_mem_readl(dev, lapic, 0x350); 2426 pHlp->pfnPrintf(pHlp, " LVT LINT0 : %08X\n", val); 2427 pHlp->pfnPrintf(pHlp, " mask = %d\n", (val >> 16) & 1); 2428 pHlp->pfnPrintf(pHlp, " trigger = %s\n", val & (1 << 15) ? "level" : "edge"); 2429 pHlp->pfnPrintf(pHlp, " rem irr = %d\n", (val >> 14) & 1); 2430 pHlp->pfnPrintf(pHlp, " polarty = %d\n", (val >> 13) & 1); 2431 pHlp->pfnPrintf(pHlp, " status = %s\n", val & (1 << 12) ? "pending" : "idle"); 2432 pHlp->pfnPrintf(pHlp, " delivry = %s\n", dmodes[(val >> 8) & 7]); 2433 pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff); 2434 val = apic_mem_readl(dev, lapic, 0x360); 2435 pHlp->pfnPrintf(pHlp, " LVT LINT1 : %08X\n", val); 2436 pHlp->pfnPrintf(pHlp, " mask = %d\n", (val >> 16) & 1); 2437 pHlp->pfnPrintf(pHlp, " trigger = %s\n", val & (1 << 15) ? "level" : "edge"); 2438 pHlp->pfnPrintf(pHlp, " rem irr = %d\n", (val >> 14) & 1); 2439 pHlp->pfnPrintf(pHlp, " polarty = %d\n", (val >> 13) & 1); 2440 pHlp->pfnPrintf(pHlp, " status = %s\n", val & (1 << 12) ? "pending" : "idle"); 2441 pHlp->pfnPrintf(pHlp, " delivry = %s\n", dmodes[(val >> 8) & 7]); 2442 pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff); 2443 } 2444 2445 /* Print LAPIC timer state. */ 2446 static DECLCALLBACK(void) lapicInfoTimer(APICDeviceInfo *dev, APICState *lapic, PCDBGFINFOHLP pHlp) 2447 { 2448 uint32_t val; 2449 unsigned divider; 2450 2451 pHlp->pfnPrintf(pHlp, "Local APIC timer:\n"); 2452 val = apic_mem_readl(dev, lapic, 0x380); 2453 pHlp->pfnPrintf(pHlp, " Initial count : %08X\n", val); 2454 val = apic_mem_readl(dev, lapic, 0x390); 2455 pHlp->pfnPrintf(pHlp, " Current count : %08X\n", val); 2456 val = apic_mem_readl(dev, lapic, 0x3E0); 2457 pHlp->pfnPrintf(pHlp, " Divide config : %08X\n", val); 2458 divider = ((val >> 1) & 0x04) | (val & 0x03); 2459 pHlp->pfnPrintf(pHlp, " divider = %d\n", divider == 7 ? 1 : 2 << divider); 2460 } 2461 2462 /** 2463 * Info handler, device version. Dumps Local APIC(s) state according to given argument. 2464 * 2465 * @param pDevIns Device instance which registered the info. 2466 * @param pHlp Callback functions for doing output. 2467 * @param pszArgs Argument string. Optional. 2468 */ 2469 static DECLCALLBACK(void) lapicInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs) 2470 { 2471 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *); 2472 APICState *lapic; 2473 2474 lapic = getLapic(dev); 2475 2476 if (pszArgs == NULL || !strcmp(pszArgs, "basic")) 2477 { 2478 lapicInfoBasic(dev, lapic, pHlp); 2479 } 2480 else if (!strcmp(pszArgs, "lvt")) 2481 { 2482 lapicInfoLVT(dev, lapic, pHlp); 2483 } 2484 else if (!strcmp(pszArgs, "timer")) 2485 { 2486 lapicInfoTimer(dev, lapic, pHlp); 2487 } 2488 else 2489 { 2490 pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'lvt', 'timer'.\n"); 2491 } 2492 } 2493 2356 2494 /** 2357 2495 * @copydoc FNSSMDEVSAVEEXEC … … 2658 2796 if (RT_FAILURE(rc)) 2659 2797 return rc; 2798 2799 /* 2800 * Register debugger info callback. 2801 */ 2802 PDMDevHlpDBGFInfoRegister(pDevIns, "lapic", "Display Local APIC state for current CPU. " 2803 "Recognizes 'basic', 'lvt', 'timer' as arguments, defaulting to 'basic'.", lapicInfo); 2660 2804 2661 2805 #ifdef VBOX_WITH_STATISTICS … … 2809 2953 2810 2954 /** 2955 * Info handler, device version. Dumps I/O APIC state. 2956 * 2957 * @param pDevIns Device instance which registered the info. 2958 * @param pHlp Callback functions for doing output. 2959 * @param pszArgs Argument string. Optional and specific to the handler. 2960 */ 2961 static DECLCALLBACK(void) ioapicInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs) 2962 { 2963 IOAPICState *s = PDMINS_2_DATA(pDevIns, IOAPICState *); 2964 uint32_t val; 2965 unsigned i; 2966 unsigned max_redir; 2967 2968 pHlp->pfnPrintf(pHlp, "I/O APIC at %08X:\n", 0xfec00000); 2969 val = s->id << 24; /* Would be nice to call ioapic_mem_readl() directly, but that's not so simple. */ 2970 pHlp->pfnPrintf(pHlp, " IOAPICID : %08X\n", val); 2971 pHlp->pfnPrintf(pHlp, " APIC ID = %02X\n", (val >> 24) & 0xff); 2972 val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); 2973 max_redir = (val >> 16) & 0xff; 2974 pHlp->pfnPrintf(pHlp, " IOAPICVER : %08X\n", val); 2975 pHlp->pfnPrintf(pHlp, " version = %02X\n", val & 0xff); 2976 pHlp->pfnPrintf(pHlp, " redirs = %d\n", ((val >> 16) & 0xff) + 1); 2977 val = 0; 2978 pHlp->pfnPrintf(pHlp, " IOAPICARB : %08X\n", val); 2979 pHlp->pfnPrintf(pHlp, " arb ID = %02X\n", (val >> 24) & 0xff); 2980 Assert(sizeof(s->ioredtbl) / sizeof(s->ioredtbl[0]) > max_redir); 2981 pHlp->pfnPrintf(pHlp, "I/O redirection table\n"); 2982 pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask trigger rirr polarity dlvr_st dlvr_mode vector\n"); 2983 for (i = 0; i <= max_redir; ++i) 2984 { 2985 static char *dmodes[] = { "Fixed ", "LowPri", "SMI ", "Resrvd", 2986 "NMI ", "INIT ", "Resrvd", "ExtINT" }; 2987 2988 pHlp->pfnPrintf(pHlp, " %02d %s %02X %d %s %d %s %s %s %3d (%016llX)\n", 2989 i, 2990 s->ioredtbl[i] & (1 << 11) ? "log " : "phys", /* dest mode */ 2991 (int)(s->ioredtbl[i] >> 56), /* dest addr */ 2992 (int)(s->ioredtbl[i] >> 16) & 1, /* mask */ 2993 s->ioredtbl[i] & (1 << 15) ? "level" : "edge ", /* trigger */ 2994 (int)(s->ioredtbl[i] >> 14) & 1, /* remote IRR */ 2995 s->ioredtbl[i] & (1 << 13) ? "activelo" : "activehi", /* polarity */ 2996 s->ioredtbl[i] & (1 << 12) ? "pend" : "idle", /* delivery status */ 2997 dmodes[(s->ioredtbl[i] >> 8) & 0x07], /* delivery mode */ 2998 (int)s->ioredtbl[i] & 0xff, /* vector */ 2999 s->ioredtbl[i] /* entire register */ 3000 ); 3001 } 3002 } 3003 3004 /** 2811 3005 * @copydoc FNSSMDEVSAVEEXEC 2812 3006 */ … … 2937 3131 if (RT_FAILURE(rc)) 2938 3132 return rc; 3133 3134 /* 3135 * Register debugger info callback. 3136 */ 3137 PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display I/O APIC state.", ioapicInfo); 2939 3138 2940 3139 #ifdef VBOX_WITH_STATISTICS -
trunk/src/VBox/Devices/PC/DevDMA.cpp
r23940 r23986 137 137 unsigned int dshift; 138 138 struct dma_regs regs[4]; 139 uint8_t ext_page[4]; 139 140 }; 140 141 … … 160 161 }; 161 162 162 static int channels[8] = {-1, 2, 3, 1, - 1, -1, -1, 0};163 static int channels[8] = {-1, 2, 3, 1, -2, -3, -4, 0}; 163 164 164 165 static void write_page (void *opaque, uint32_t nport, uint32_t data) 166 { 167 struct dma_cont *d = (struct dma_cont*)opaque; 168 int ichan; 169 170 ichan = channels[nport & 7]; 171 if (ichan >= 0) 172 d->regs[ichan].page = data; 173 else 174 d->ext_page[-ichan - 1] = data; 175 } 176 177 static void write_pageh (void *opaque, uint32_t nport, uint32_t data) 165 178 { 166 179 struct dma_cont *d = (struct dma_cont*)opaque; … … 172 185 return; 173 186 } 174 d->regs[ichan].page = data;175 } 176 177 static void write_pageh (void *opaque, uint32_t nport, uint32_t data)187 d->regs[ichan].pageh = data; 188 } 189 190 static uint32_t read_page (void *opaque, uint32_t nport) 178 191 { 179 192 struct dma_cont *d = (struct dma_cont*)opaque; … … 181 194 182 195 ichan = channels[nport & 7]; 183 if (-1 == ichan) { 184 dolog ("invalid channel %#x %#x\n", nport, data); 185 return; 186 } 187 d->regs[ichan].pageh = data; 188 } 189 190 static uint32_t read_page (void *opaque, uint32_t nport) 191 { 192 struct dma_cont *d = (struct dma_cont*)opaque; 193 int ichan; 194 195 ichan = channels[nport & 7]; 196 if (-1 == ichan) { 197 dolog ("invalid channel read %#x\n", nport); 198 return 0; 199 } 200 return d->regs[ichan].page; 196 if (ichan >= 0) 197 return d->regs[ichan].page; 198 else 199 return d->regs[-ichan - 1].page; 201 200 } 202 201 … … 669 668 { 670 669 const static int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 }; 670 const static int misc_port_list[] = { 0x0, 0x4, 0x5, 0x6 }; 671 671 int i; 672 672 … … 707 707 PDMDevHlpIOPortRegister (s->pDevIns, base + ((i + 8) << dshift), 1, d, 708 708 io_write_cont, io_read_cont, NULL, NULL, "DMA cont"); 709 PDMDevHlpIOPortRegister (s->pDevIns, page_base + misc_port_list[i], 1, d, 710 io_write_page, io_read_page, NULL, NULL, "Dummy DMA Page"); 709 711 #else 710 712 register_ioport_write (base + ((i + 8) << dshift), 1, 1, -
trunk/src/VBox/Devices/PC/DevPIC.cpp
r22793 r23986 486 486 AssertReleaseMsgFailed(("single mode not supported")); 487 487 if (val & 0x08) 488 AssertReleaseMsgFailed(("level sensitive irq not supported"));488 LogRel(("level sensitive irq not supported - ignoring")); 489 489 } else if (val & 0x08) { 490 490 if (val & 0x04)
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