VirtualBox

Changeset 24045 in vbox for trunk/src


Ignore:
Timestamp:
Oct 23, 2009 4:19:17 PM (16 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
53903
Message:

DevAHCI: save and verify config (saved state).

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Storage/DevAHCI.cpp

    r23469 r24045  
    6868#define AHCI_MAX_NR_PORTS_IMPL 30
    6969#define AHCI_NR_COMMAND_SLOTS 32
    70 #define AHCI_SAVED_STATE_VERSION 2
    7170#define AHCI_NR_OF_ALLOWED_BIGGER_LISTS 100
     71
     72/** The current saved state version. */
     73#define AHCI_SAVED_STATE_VERSION                3
     74/** The saved state version use in VirtualBox 3.0 and earlier.
     75 * This was before the config was added and ahciIOTasks was dropped. */
     76#define AHCI_SAVED_STATE_VERSION_VBOX_30        2
    7277
    7378/**
    … …  
    59855990
    59865991/**
    5987  * Saves a state of the AHCI device.
    5988  *
    5989  * @returns VBox status code.
    5990  * @param   pDevIns     The device instance.
    5991  * @param   pSSMHandle  The handle to save the state to.
    5992  */
    5993 static DECLCALLBACK(int) ahciSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
    5994 {
    5995     PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
     5992 * @copydoc FNDEVSSMLIVEEXEC
     5993 */
     5994static DECLCALLBACK(int) ahciLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
     5995{
     5996    PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
     5997
     5998    /* config. */
     5999    SSMR3PutU32(pSSM, pThis->cPortsImpl);
     6000    for (uint32_t i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
     6001    {
     6002        SSMR3PutBool(pSSM, pThis->ahciPort[i].pDrvBase != NULL);
     6003        SSMR3PutStrZ(pSSM, pThis->ahciPort[i].szSerialNumber);
     6004        SSMR3PutStrZ(pSSM, pThis->ahciPort[i].szFirmwareRevision);
     6005        SSMR3PutStrZ(pSSM, pThis->ahciPort[i].szModelNumber);
     6006    }
     6007
     6008    static const char *s_apszIdeEmuPortNames[4] = { "PrimaryMaster", "PrimarySlave", "SecondaryMaster", "SecondarySlave" };
     6009    for (size_t i = 0; i < RT_ELEMENTS(s_apszIdeEmuPortNames); i++)
     6010    {
     6011        uint32_t iPort;
     6012        int rc = CFGMR3QueryU32Def(pDevIns->pCfgHandle, s_apszIdeEmuPortNames[i], &iPort, i);
     6013        AssertRCReturn(rc, rc);
     6014        SSMR3PutU32(pSSM, iPort);
     6015    }
     6016
     6017    return VINF_SSM_DONT_CALL_AGAIN;
     6018}
     6019
     6020/**
     6021 * @copydoc FNDEVSSMSAVEEXEC
     6022 */
     6023static DECLCALLBACK(int) ahciSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
     6024{
     6025    PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
    59966026    uint32_t i;
    5997 
    5998     Assert(!pAhci->f8ByteMMIO4BytesWrittenSuccessfully);
    5999 
    6000     /* First the main device structure. */
    6001     SSMR3PutU32(pSSMHandle, pAhci->regHbaCap);
    6002     SSMR3PutU32(pSSMHandle, pAhci->regHbaCtrl);
    6003     SSMR3PutU32(pSSMHandle, pAhci->regHbaIs);
    6004     SSMR3PutU32(pSSMHandle, pAhci->regHbaPi);
    6005     SSMR3PutU32(pSSMHandle, pAhci->regHbaVs);
    6006     SSMR3PutU32(pSSMHandle, pAhci->regHbaCccCtl);
    6007     SSMR3PutU32(pSSMHandle, pAhci->regHbaCccPorts);
    6008     SSMR3PutU8(pSSMHandle, pAhci->uCccPortNr);
    6009     SSMR3PutU64(pSSMHandle, pAhci->uCccTimeout);
    6010     SSMR3PutU32(pSSMHandle, pAhci->uCccNr);
    6011     SSMR3PutU32(pSSMHandle, pAhci->uCccCurrentNr);
    6012     SSMR3PutU32(pSSMHandle, pAhci->u32PortsInterrupted);
    6013     SSMR3PutBool(pSSMHandle, pAhci->fReset);
    6014     SSMR3PutBool(pSSMHandle, pAhci->f64BitAddr);
    6015     SSMR3PutBool(pSSMHandle, pAhci->fR0Enabled);
    6016     SSMR3PutBool(pSSMHandle, pAhci->fGCEnabled);
     6027    int rc;
     6028
     6029    Assert(!pThis->f8ByteMMIO4BytesWrittenSuccessfully);
     6030
     6031    /* The config */
     6032    rc = ahciLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
     6033    AssertRCReturn(rc, rc);
     6034
     6035    /* The main device structure. */
     6036    SSMR3PutU32(pSSM, pThis->regHbaCap);
     6037    SSMR3PutU32(pSSM, pThis->regHbaCtrl);
     6038    SSMR3PutU32(pSSM, pThis->regHbaIs);
     6039    SSMR3PutU32(pSSM, pThis->regHbaPi);
     6040    SSMR3PutU32(pSSM, pThis->regHbaVs);
     6041    SSMR3PutU32(pSSM, pThis->regHbaCccCtl);
     6042    SSMR3PutU32(pSSM, pThis->regHbaCccPorts);
     6043    SSMR3PutU8(pSSM, pThis->uCccPortNr);
     6044    SSMR3PutU64(pSSM, pThis->uCccTimeout);
     6045    SSMR3PutU32(pSSM, pThis->uCccNr);
     6046    SSMR3PutU32(pSSM, pThis->uCccCurrentNr);
     6047    SSMR3PutU32(pSSM, pThis->u32PortsInterrupted);
     6048    SSMR3PutBool(pSSM, pThis->fReset);
     6049    SSMR3PutBool(pSSM, pThis->f64BitAddr);
     6050    SSMR3PutBool(pSSM, pThis->fR0Enabled);
     6051    SSMR3PutBool(pSSM, pThis->fGCEnabled);
    60176052
    60186053    /* Now every port. */
    60196054    for (i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
    60206055    {
    6021         Assert(pAhci->ahciPort[i].uActTasksActive == 0);
    6022         SSMR3PutU32(pSSMHandle, pAhci->ahciPort[i].regCLB);
    6023         SSMR3PutU32(pSSMHandle, pAhci->ahciPort[i].regCLBU);
    6024         SSMR3PutU32(pSSMHandle, pAhci->ahciPort[i].regFB);
    6025         SSMR3PutU32(pSSMHandle, pAhci->ahciPort[i].regFBU);
    6026         SSMR3PutGCPhys(pSSMHandle, pAhci->ahciPort[i].GCPhysAddrClb);
    6027         SSMR3PutGCPhys(pSSMHandle, pAhci->ahciPort[i].GCPhysAddrFb);
    6028         SSMR3PutU32(pSSMHandle, pAhci->ahciPort[i].regIS);
    6029         SSMR3PutU32(pSSMHandle, pAhci->ahciPort[i].regIE);
    6030         SSMR3PutU32(pSSMHandle, pAhci->ahciPort[i].regCMD);
    6031         SSMR3PutU32(pSSMHandle, pAhci->ahciPort[i].regTFD);
    6032         SSMR3PutU32(pSSMHandle, pAhci->ahciPort[i].regSIG);
    6033         SSMR3PutU32(pSSMHandle, pAhci->ahciPort[i].regSSTS);
    6034         SSMR3PutU32(pSSMHandle, pAhci->ahciPort[i].regSCTL);
    6035         SSMR3PutU32(pSSMHandle, pAhci->ahciPort[i].regSERR);
    6036         SSMR3PutU32(pSSMHandle, pAhci->ahciPort[i].regSACT);
    6037         SSMR3PutU32(pSSMHandle, pAhci->ahciPort[i].regCI);
    6038         SSMR3PutU32(pSSMHandle, pAhci->ahciPort[i].PCHSGeometry.cCylinders);
    6039         SSMR3PutU32(pSSMHandle, pAhci->ahciPort[i].PCHSGeometry.cHeads);
    6040         SSMR3PutU32(pSSMHandle, pAhci->ahciPort[i].PCHSGeometry.cSectors);
    6041         SSMR3PutU64(pSSMHandle, pAhci->ahciPort[i].cTotalSectors);
    6042         SSMR3PutU32(pSSMHandle, pAhci->ahciPort[i].cMultSectors);
    6043         SSMR3PutU8(pSSMHandle, pAhci->ahciPort[i].uATATransferMode);
    6044         SSMR3PutBool(pSSMHandle, pAhci->ahciPort[i].fResetDevice);
    6045 
    6046         for (uint8_t uActTask = 0; uActTask < AHCI_NR_COMMAND_SLOTS; uActTask++)
    6047             SSMR3PutU8(pSSMHandle, pAhci->ahciPort[i].ahciIOTasks[uActTask]);
    6048 
    6049         SSMR3PutU8(pSSMHandle, pAhci->ahciPort[i].uActWritePos);
    6050         SSMR3PutU8(pSSMHandle, pAhci->ahciPort[i].uActReadPos);
    6051         SSMR3PutBool(pSSMHandle, pAhci->ahciPort[i].fPoweredOn);
    6052         SSMR3PutBool(pSSMHandle, pAhci->ahciPort[i].fSpunUp);
    6053         SSMR3PutU32(pSSMHandle, pAhci->ahciPort[i].u32TasksFinished);
    6054         SSMR3PutU32(pSSMHandle, pAhci->ahciPort[i].u32QueuedTasksFinished);
     6056        Assert(pThis->ahciPort[i].uActTasksActive == 0);
     6057        SSMR3PutU32(pSSM, pThis->ahciPort[i].regCLB);
     6058        SSMR3PutU32(pSSM, pThis->ahciPort[i].regCLBU);
     6059        SSMR3PutU32(pSSM, pThis->ahciPort[i].regFB);
     6060        SSMR3PutU32(pSSM, pThis->ahciPort[i].regFBU);
     6061        SSMR3PutGCPhys(pSSM, pThis->ahciPort[i].GCPhysAddrClb);
     6062        SSMR3PutGCPhys(pSSM, pThis->ahciPort[i].GCPhysAddrFb);
     6063        SSMR3PutU32(pSSM, pThis->ahciPort[i].regIS);
     6064        SSMR3PutU32(pSSM, pThis->ahciPort[i].regIE);
     6065        SSMR3PutU32(pSSM, pThis->ahciPort[i].regCMD);
     6066        SSMR3PutU32(pSSM, pThis->ahciPort[i].regTFD);
     6067        SSMR3PutU32(pSSM, pThis->ahciPort[i].regSIG);
     6068        SSMR3PutU32(pSSM, pThis->ahciPort[i].regSSTS);
     6069        SSMR3PutU32(pSSM, pThis->ahciPort[i].regSCTL);
     6070        SSMR3PutU32(pSSM, pThis->ahciPort[i].regSERR);
     6071        SSMR3PutU32(pSSM, pThis->ahciPort[i].regSACT);
     6072        SSMR3PutU32(pSSM, pThis->ahciPort[i].regCI);
     6073        SSMR3PutU32(pSSM, pThis->ahciPort[i].PCHSGeometry.cCylinders);
     6074        SSMR3PutU32(pSSM, pThis->ahciPort[i].PCHSGeometry.cHeads);
     6075        SSMR3PutU32(pSSM, pThis->ahciPort[i].PCHSGeometry.cSectors);
     6076        SSMR3PutU64(pSSM, pThis->ahciPort[i].cTotalSectors);
     6077        SSMR3PutU32(pSSM, pThis->ahciPort[i].cMultSectors);
     6078        SSMR3PutU8(pSSM, pThis->ahciPort[i].uATATransferMode);
     6079        SSMR3PutBool(pSSM, pThis->ahciPort[i].fResetDevice);
     6080
     6081        /* No need to save */
     6082        SSMR3PutU8(pSSM, pThis->ahciPort[i].uActWritePos);
     6083        SSMR3PutU8(pSSM, pThis->ahciPort[i].uActReadPos);
     6084        SSMR3PutBool(pSSM, pThis->ahciPort[i].fPoweredOn);
     6085        SSMR3PutBool(pSSM, pThis->ahciPort[i].fSpunUp);
     6086        SSMR3PutU32(pSSM, pThis->ahciPort[i].u32TasksFinished);
     6087        SSMR3PutU32(pSSM, pThis->ahciPort[i].u32QueuedTasksFinished);
    60556088    }
    60566089
    60576090    /* Now the emulated ata controllers. */
    6058     for (i = 0; i < RT_ELEMENTS(pAhci->aCts); i++)
    6059     {
    6060         int rc;
    6061 
    6062         rc = ataControllerSaveExec(&pAhci->aCts[i], pSSMHandle);
     6091    for (i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
     6092    {
     6093        rc = ataControllerSaveExec(&pThis->aCts[i], pSSM);
    60636094        if (RT_FAILURE(rc))
    60646095            return rc;
    60656096    }
    60666097
    6067     return SSMR3PutU32(pSSMHandle, ~0); /* sanity/terminator */
     6098    return SSMR3PutU32(pSSM, UINT32_MAX); /* sanity/terminator */
    60686099}
    60696100
    … …  
    60736104 * @returns VBox status code.
    60746105 * @param   pDevIns     The device instance.
    6075  * @param   pSSMHandle  The handle to the saved state.
     6106 * @param   pSSM  The handle to the saved state.
    60766107 * @param   uVersion  The data unit version number.
    60776108 * @param   uPass           The data pass.
    60786109 */
    6079 static DECLCALLBACK(int) ahciLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t uVersion, uint32_t uPass)
    6080 {
    6081     PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
     6110static DECLCALLBACK(int) ahciLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
     6111{
     6112    PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
    60826113    uint32_t u32;
    60836114    uint32_t i;
    6084 
    6085     if (uVersion != AHCI_SAVED_STATE_VERSION)
     6115    int rc;
     6116
     6117    if (    uVersion != AHCI_SAVED_STATE_VERSION
     6118        &&  uVersion != AHCI_SAVED_STATE_VERSION_VBOX_30)
    60866119        return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
    6087     Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
    6088 
    6089     /* Restore data. */
    6090 
    6091     /* First the main device structure. */
    6092     SSMR3GetU32(pSSMHandle, &pAhci->regHbaCap);
    6093     SSMR3GetU32(pSSMHandle, &pAhci->regHbaCtrl);
    6094     SSMR3GetU32(pSSMHandle, &pAhci->regHbaIs);
    6095     SSMR3GetU32(pSSMHandle, &pAhci->regHbaPi);
    6096     SSMR3GetU32(pSSMHandle, &pAhci->regHbaVs);
    6097     SSMR3GetU32(pSSMHandle, &pAhci->regHbaCccCtl);
    6098     SSMR3GetU32(pSSMHandle, &pAhci->regHbaCccPorts);
    6099     SSMR3GetU8(pSSMHandle, &pAhci->uCccPortNr);
    6100     SSMR3GetU64(pSSMHandle, &pAhci->uCccTimeout);
    6101     SSMR3GetU32(pSSMHandle, &pAhci->uCccNr);
    6102     SSMR3GetU32(pSSMHandle, &pAhci->uCccCurrentNr);
    6103 
    6104     SSMR3GetU32(pSSMHandle, &pAhci->u32PortsInterrupted);
    6105     SSMR3GetBool(pSSMHandle, &pAhci->fReset);
    6106     SSMR3GetBool(pSSMHandle, &pAhci->f64BitAddr);
    6107     SSMR3GetBool(pSSMHandle, &pAhci->fR0Enabled);
    6108     SSMR3GetBool(pSSMHandle, &pAhci->fGCEnabled);
    6109 
    6110     /* Now every port. */
    6111     for (i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
    6112     {
    6113         SSMR3GetU32(pSSMHandle, &pAhci->ahciPort[i].regCLB);
    6114         SSMR3GetU32(pSSMHandle, &pAhci->ahciPort[i].regCLBU);
    6115         SSMR3GetU32(pSSMHandle, &pAhci->ahciPort[i].regFB);
    6116         SSMR3GetU32(pSSMHandle, &pAhci->ahciPort[i].regFBU);
    6117         SSMR3GetGCPhys(pSSMHandle, (RTGCPHYS *)&pAhci->ahciPort[i].GCPhysAddrClb);
    6118         SSMR3GetGCPhys(pSSMHandle, (RTGCPHYS *)&pAhci->ahciPort[i].GCPhysAddrFb);
    6119         SSMR3GetU32(pSSMHandle, (uint32_t *)&pAhci->ahciPort[i].regIS);
    6120         SSMR3GetU32(pSSMHandle, &pAhci->ahciPort[i].regIE);
    6121         SSMR3GetU32(pSSMHandle, &pAhci->ahciPort[i].regCMD);
    6122         SSMR3GetU32(pSSMHandle, &pAhci->ahciPort[i].regTFD);
    6123         SSMR3GetU32(pSSMHandle, &pAhci->ahciPort[i].regSIG);
    6124         SSMR3GetU32(pSSMHandle, &pAhci->ahciPort[i].regSSTS);
    6125         SSMR3GetU32(pSSMHandle, &pAhci->ahciPort[i].regSCTL);
    6126         SSMR3GetU32(pSSMHandle, &pAhci->ahciPort[i].regSERR);
    6127         SSMR3GetU32(pSSMHandle, (uint32_t *)&pAhci->ahciPort[i].regSACT);
    6128         SSMR3GetU32(pSSMHandle, (uint32_t *)&pAhci->ahciPort[i].regCI);
    6129         SSMR3GetU32(pSSMHandle, &pAhci->ahciPort[i].PCHSGeometry.cCylinders);
    6130         SSMR3GetU32(pSSMHandle, &pAhci->ahciPort[i].PCHSGeometry.cHeads);
    6131         SSMR3GetU32(pSSMHandle, &pAhci->ahciPort[i].PCHSGeometry.cSectors);
    6132         SSMR3GetU64(pSSMHandle, &pAhci->ahciPort[i].cTotalSectors);
    6133         SSMR3GetU32(pSSMHandle, &pAhci->ahciPort[i].cMultSectors);
    6134         SSMR3GetU8(pSSMHandle, &pAhci->ahciPort[i].uATATransferMode);
    6135         SSMR3GetBool(pSSMHandle, &pAhci->ahciPort[i].fResetDevice);
    6136 
    6137         for (uint8_t uActTask = 0; uActTask < AHCI_NR_COMMAND_SLOTS; uActTask++)
    6138             SSMR3GetU8(pSSMHandle, (uint8_t *)&pAhci->ahciPort[i].ahciIOTasks[uActTask]);
    6139 
    6140         SSMR3GetU8(pSSMHandle, &pAhci->ahciPort[i].uActWritePos);
    6141         SSMR3GetU8(pSSMHandle, &pAhci->ahciPort[i].uActReadPos);
    6142         SSMR3GetBool(pSSMHandle, &pAhci->ahciPort[i].fPoweredOn);
    6143         SSMR3GetBool(pSSMHandle, &pAhci->ahciPort[i].fSpunUp);
    6144         SSMR3GetU32(pSSMHandle, (uint32_t *)&pAhci->ahciPort[i].u32TasksFinished);
    6145         SSMR3GetU32(pSSMHandle, (uint32_t *)&pAhci->ahciPort[i].u32QueuedTasksFinished);
    6146     }
    6147 
    6148     /* Now the emulated ata controllers. */
    6149     for (i = 0; i < RT_ELEMENTS(pAhci->aCts); i++)
    6150     {
    6151         int rc = ataControllerLoadExec(&pAhci->aCts[i], pSSMHandle);
     6120
     6121    /* Verify config. */
     6122    if (uVersion > AHCI_SAVED_STATE_VERSION_VBOX_30)
     6123    {
     6124        rc = SSMR3GetU32(pSSM, &u32);
     6125        AssertRCReturn(rc, rc);
     6126        if (u32 != pThis->cPortsImpl)
     6127        {
     6128            LogRel(("AHCI: Config mismatch: cPortsImpl - saved=%u config=%u\n", u32, pThis->cPortsImpl));
     6129            if (    u32 < pThis->cPortsImpl
     6130                ||  u32 > AHCI_MAX_NR_PORTS_IMPL)
     6131                return VERR_SSM_LOAD_CONFIG_MISMATCH;
     6132        }
     6133
     6134        for (uint32_t i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
     6135        {
     6136            bool fInUse;
     6137            rc = SSMR3GetBool(pSSM, &fInUse);
     6138            AssertRCReturn(rc, rc);
     6139            if (fInUse != (pThis->ahciPort[i].pDrvBase != NULL))
     6140            {
     6141                LogRel(("AHCI: Config mismatch: cPortsImpl - saved=%u config=%u\n", u32, pThis->cPortsImpl));
     6142                if (    u32 < pThis->cPortsImpl
     6143                    ||  u32 > AHCI_MAX_NR_PORTS_IMPL)
     6144                    return VERR_SSM_LOAD_CONFIG_MISMATCH;
     6145            }
     6146
     6147            char szSerialNumber[AHCI_SERIAL_NUMBER_LENGTH+1];
     6148            rc = SSMR3GetStrZ(pSSM, szSerialNumber,     sizeof(szSerialNumber));
     6149            AssertRCReturn(rc, rc);
     6150            if (strcmp(szSerialNumber, pThis->ahciPort[i].szSerialNumber))
     6151                LogRel(("ACHI: Port %u config mismatch: Serial number - saved='%s' config='%s'\n",
     6152                        szSerialNumber, pThis->ahciPort[i].szSerialNumber));
     6153
     6154            char szFirmwareRevision[AHCI_FIRMWARE_REVISION_LENGTH+1];
     6155            rc = SSMR3GetStrZ(pSSM, szFirmwareRevision, sizeof(szFirmwareRevision));
     6156            AssertRCReturn(rc, rc);
     6157            if (strcmp(szFirmwareRevision, pThis->ahciPort[i].szFirmwareRevision))
     6158                LogRel(("ACHI: Port %u config mismatch: Firmware revision - saved='%s' config='%s'\n",
     6159                        szFirmwareRevision, pThis->ahciPort[i].szFirmwareRevision));
     6160
     6161            char szModelNumber[AHCI_MODEL_NUMBER_LENGTH+1];
     6162            rc = SSMR3GetStrZ(pSSM, szModelNumber,      sizeof(szModelNumber));
     6163            AssertRCReturn(rc, rc);
     6164            if (strcmp(szModelNumber, pThis->ahciPort[i].szModelNumber))
     6165                LogRel(("ACHI: Port %u config mismatch: Model number - saved='%s' config='%s'\n",
     6166                        szModelNumber, pThis->ahciPort[i].szModelNumber));
     6167        }
     6168
     6169        static const char *s_apszIdeEmuPortNames[4] = { "PrimaryMaster", "PrimarySlave", "SecondaryMaster", "SecondarySlave" };
     6170        for (size_t i = 0; i < RT_ELEMENTS(s_apszIdeEmuPortNames); i++)
     6171        {
     6172            uint32_t iPort;
     6173            rc = CFGMR3QueryU32Def(pDevIns->pCfgHandle, s_apszIdeEmuPortNames[i], &iPort, i);
     6174            AssertRCReturn(rc, rc);
     6175
     6176            uint32_t iPortSaved;
     6177            rc = SSMR3GetU32(pSSM, &iPortSaved);
     6178            AssertRCReturn(rc, rc);
     6179
     6180            if (iPortSaved != iPort)
     6181            {
     6182                LogRel(("ACHI: IDE %s config mismatch: saved=%u config=%u\n",
     6183                        s_apszIdeEmuPortNames[i], iPortSaved, iPort));
     6184                return VERR_SSM_LOAD_CONFIG_MISMATCH;
     6185            }
     6186        }
     6187    }
     6188
     6189    if (uPass == SSM_PASS_FINAL)
     6190    {
     6191        /* Restore data. */
     6192
     6193        /* The main device structure. */
     6194        SSMR3GetU32(pSSM, &pThis->regHbaCap);
     6195        SSMR3GetU32(pSSM, &pThis->regHbaCtrl);
     6196        SSMR3GetU32(pSSM, &pThis->regHbaIs);
     6197        SSMR3GetU32(pSSM, &pThis->regHbaPi);
     6198        SSMR3GetU32(pSSM, &pThis->regHbaVs);
     6199        SSMR3GetU32(pSSM, &pThis->regHbaCccCtl);
     6200        SSMR3GetU32(pSSM, &pThis->regHbaCccPorts);
     6201        SSMR3GetU8(pSSM, &pThis->uCccPortNr);
     6202        SSMR3GetU64(pSSM, &pThis->uCccTimeout);
     6203        SSMR3GetU32(pSSM, &pThis->uCccNr);
     6204        SSMR3GetU32(pSSM, &pThis->uCccCurrentNr);
     6205
     6206        SSMR3GetU32(pSSM, &pThis->u32PortsInterrupted);
     6207        SSMR3GetBool(pSSM, &pThis->fReset);
     6208        SSMR3GetBool(pSSM, &pThis->f64BitAddr);
     6209        SSMR3GetBool(pSSM, &pThis->fR0Enabled);
     6210        SSMR3GetBool(pSSM, &pThis->fGCEnabled);
     6211
     6212        /* Now every port. */
     6213        for (i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
     6214        {
     6215            SSMR3GetU32(pSSM, &pThis->ahciPort[i].regCLB);
     6216            SSMR3GetU32(pSSM, &pThis->ahciPort[i].regCLBU);
     6217            SSMR3GetU32(pSSM, &pThis->ahciPort[i].regFB);
     6218            SSMR3GetU32(pSSM, &pThis->ahciPort[i].regFBU);
     6219            SSMR3GetGCPhys(pSSM, (RTGCPHYS *)&pThis->ahciPort[i].GCPhysAddrClb);
     6220            SSMR3GetGCPhys(pSSM, (RTGCPHYS *)&pThis->ahciPort[i].GCPhysAddrFb);
     6221            SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].regIS);
     6222            SSMR3GetU32(pSSM, &pThis->ahciPort[i].regIE);
     6223            SSMR3GetU32(pSSM, &pThis->ahciPort[i].regCMD);
     6224            SSMR3GetU32(pSSM, &pThis->ahciPort[i].regTFD);
     6225            SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSIG);
     6226            SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSSTS);
     6227            SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSCTL);
     6228            SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSERR);
     6229            SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].regSACT);
     6230            SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].regCI);
     6231            SSMR3GetU32(pSSM, &pThis->ahciPort[i].PCHSGeometry.cCylinders);
     6232            SSMR3GetU32(pSSM, &pThis->ahciPort[i].PCHSGeometry.cHeads);
     6233            SSMR3GetU32(pSSM, &pThis->ahciPort[i].PCHSGeometry.cSectors);
     6234            SSMR3GetU64(pSSM, &pThis->ahciPort[i].cTotalSectors);
     6235            SSMR3GetU32(pSSM, &pThis->ahciPort[i].cMultSectors);
     6236            SSMR3GetU8(pSSM, &pThis->ahciPort[i].uATATransferMode);
     6237            SSMR3GetBool(pSSM, &pThis->ahciPort[i].fResetDevice);
     6238
     6239            if (uVersion <= AHCI_SAVED_STATE_VERSION_VBOX_30)
     6240                SSMR3Skip(pSSM, AHCI_NR_COMMAND_SLOTS * sizeof(uint8_t)); /* no active data here */
     6241
     6242            SSMR3GetU8(pSSM, &pThis->ahciPort[i].uActWritePos);
     6243            SSMR3GetU8(pSSM, &pThis->ahciPort[i].uActReadPos);
     6244            SSMR3GetBool(pSSM, &pThis->ahciPort[i].fPoweredOn);
     6245            SSMR3GetBool(pSSM, &pThis->ahciPort[i].fSpunUp);
     6246            SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].u32TasksFinished);
     6247            SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].u32QueuedTasksFinished);
     6248        }
     6249
     6250        /* Now the emulated ata controllers. */
     6251        for (i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
     6252        {
     6253            rc = ataControllerLoadExec(&pThis->aCts[i], pSSM);
     6254            if (RT_FAILURE(rc))
     6255                return rc;
     6256        }
     6257
     6258        rc = SSMR3GetU32(pSSM, &u32);
    61526259        if (RT_FAILURE(rc))
    61536260            return rc;
    6154     }
    6155 
    6156     int rc = SSMR3GetU32(pSSMHandle, &u32);
    6157     if (RT_FAILURE(rc))
    6158         return rc;
    6159     AssertMsgReturn(u32 == ~0U, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
     6261        AssertMsgReturn(u32 == UINT32_MAX, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
     6262    }
    61606263
    61616264    return VINF_SUCCESS;
    … …  
    63466449     * Validate and read configuration.
    63476450     */
    6348     rc = CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0"
     6451    if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0"
    63496452                                          "R0Enabled\0"
    63506453                                          "PrimaryMaster\0"
    … …  
    63536456                                          "SecondarySlave\0"
    63546457                                          "PortCount\0"
    6355                                           "UseAsyncInterfaceIfAvailable\0");
    6356     if (RT_FAILURE(rc))
     6458                                          "UseAsyncInterfaceIfAvailable\0"
     6459                                          "HighIOThreshold\0"
     6460                                          "MillisToSleep\0"))
    63576461        return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
    63586462                                N_("AHCI configuration error: unknown option specified"));
    … …  
    65526656    {
    65536657        char szName[24];
    6554         RTStrPrintf(szName, sizeof(szName), "Port%d", i);
     6658        RTStrPrintf(szName, sizeof(szName), "Port%u", i);
    65556659
    65566660        PAHCIPort pAhciPort      = &pThis->ahciPort[i];
    … …  
    67836887
    67846888    rc = PDMDevHlpSSMRegisterEx(pDevIns, AHCI_SAVED_STATE_VERSION, sizeof(*pThis)+cbTotalBufferSize, NULL,
    6785                                 NULL, NULL, NULL,
     6889                                NULL,         ahciLiveExec, NULL,
    67866890                                ahciSavePrep, ahciSaveExec, NULL,
    67876891                                ahciLoadPrep, ahciLoadExec, NULL);
Note: See TracChangeset for help on using the changeset viewer.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette