Changeset 24125 in vbox for trunk

Timestamp:

Oct 28, 2009 9:58:41 AM (15 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

54037

Message:

DevAPIC/PDM: Properly route PIC interrupts through local APIC (fixes double time interrupt delivery in some Linux kernels).

Location:

trunk

Files:

• include/VBox/pdmdev.h (modified) (7 diffs)
• src/VBox/Devices/PC/DevAPIC.cpp (modified) (8 diffs)
• src/VBox/VMM/PDM.cpp (modified) (1 diff)
• src/VBox/VMM/PDMDevHlp.cpp (modified) (14 diffs)
• src/VBox/VMM/PDMDevMiscHlp.cpp (modified) (5 diffs)
• src/VBox/VMM/PDMInternal.h (modified) (3 diffs)
• src/VBox/VMM/VMMGC/PDMGCDevice.cpp (modified) (3 diffs)
• src/VBox/VMM/VMMR0/PDMR0Device.cpp (modified) (3 diffs)

trunk/include/VBox/pdmdev.h

@@ -1043 +1043 @@
                                                 uint8_t iVector, uint8_t u8Polarity, uint8_t u8TriggerMode));
 
+    /**
+     * Deliver a signal to CPU's local interrupt pins (LINT0/LINT1). Used for
+     * virtual wire mode when interrupts from the PIC are passed through LAPIC.
+     *
+     * @returns status code.
+     * @param   pDevIns         Device instance of the APIC.
+     * @param   u8Pin           Local pin number (0 or 1 for current CPUs).
+     */
+    DECLR3CALLBACKMEMBER(int,  pfnLocalInterruptR3,(PPDMDEVINS pDevIns, uint8_t u8Pin, uint8_t u8Level));
+
     /** The name of the RC GetInterrupt entry point. */
     const char         *pszGetInterruptRC;
@@ -1061 +1071 @@
     /** The name of the RC BusDeliver entry point. */
     const char         *pszBusDeliverRC;
+    /** The name of the RC LocalInterrupt entry point. */
+    const char         *pszLocalInterruptRC;
 
     /** The name of the R0 GetInterrupt entry point. */
@@ -1080 +1092 @@
     /** The name of the R0 BusDeliver entry point. */
     const char         *pszBusDeliverR0;
+    /** The name of the R0 LocalInterrupt entry point. */
+    const char         *pszLocalInterruptR0;
 
 } PDMAPICREG;
@@ -1119 +1133 @@
     /** SMI. */
     PDMAPICIRQ_SMI,
+    /** ExtINT (HW interrupt via PIC). */
+    PDMAPICIRQ_EXTINT,
     /** The usual 32-bit paranoia. */
     PDMAPICIRQ_32BIT_HACK = 0x7fffffff
@@ -1145 +1161 @@
      *
      * @param   pDevIns         Device instance of the APIC.
+     * @param   enmType         IRQ type.
      * @param   idCpu           Virtual CPU to clear flag upon.
      */
-    DECLRCCALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns, VMCPUID idCpu));
+    DECLRCCALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu));
 
     /**
@@ -1214 +1231 @@
      *
      * @param   pDevIns         Device instance of the APIC.
+     * @param   enmType         IRQ type.
      * @param   idCpu           Virtual CPU to clear flag upon.
      */
-    DECLR0CALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns, VMCPUID idCpu));
+    DECLR0CALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu));
 
     /**
@@ -1282 +1300 @@
      *
      * @param   pDevIns         Device instance of the APIC.
+     * @param   enmType         IRQ type.
      * @param   idCpu           Virtual CPU to clear flag upon.
      */
-    DECLR3CALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns, VMCPUID idCpu));
+    DECLR3CALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu));
 
     /**

trunk/src/VBox/Devices/PC/DevAPIC.cpp

@@ -390 +390 @@
                                            uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
                                            uint8_t u8TriggerMode);
+PDMBOTHCBDECL(int)  apicLocalInterrupt(PPDMDEVINS pDevIns, uint8_t u8Pin, uint8_t u8Level);
 PDMBOTHCBDECL(int)  apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value);
 PDMBOTHCBDECL(int)  apicReadMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value);
@@ -446 +447 @@
 }
 
-DECLINLINE(void) cpuClearInterrupt(APICDeviceInfo* dev, APICState *s)
+DECLINLINE(void) cpuClearInterrupt(APICDeviceInfo* dev, APICState *s, PDMAPICIRQ enmType = PDMAPICIRQ_HARDWARE)
 {
     LogFlow(("apic: clear interrupt flag\n"));
-    dev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(dev->CTX_SUFF(pDevIns),
+    dev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(dev->CTX_SUFF(pDevIns), enmType,
                                                  getCpuFromLapic(dev, s));
 }
@@ -961 +962 @@
     return apic_bus_deliver(dev, apic_get_delivery_bitmask(dev, u8Dest, u8DestMode),
                             u8DeliveryMode, iVector, u8Polarity, u8TriggerMode);
+}
+
+/**
+ * Local interrupt delivery, for devices attached to the CPU's LINT0/LINT1 pin.
+ * Normally used for 8259A PIC and NMI.
+ */
+PDMBOTHCBDECL(int) apicLocalInterrupt(PPDMDEVINS pDevIns, uint8_t u8Pin, uint8_t u8Level)
+{
+    APICDeviceInfo  *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
+    APICState       *s = getLapicById(dev, 0);
+
+    Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
+    LogFlow(("apicLocalInterrupt: pDevIns=%p u8Pin=%x\n", pDevIns, u8Pin));
+
+    /* If LAPIC is disabled, go straight to the CPU. */
+    if (!(s->spurious_vec & APIC_SV_ENABLE))
+    {
+        LogFlow(("apicLocalInterrupt: LAPIC disabled, delivering directly to CPU core.\n"));
+        if (u8Level)
+            cpuSetInterrupt(dev, s, PDMAPICIRQ_EXTINT);
+        else
+            cpuClearInterrupt(dev, s, PDMAPICIRQ_EXTINT);
+
+        return VINF_SUCCESS;
+    }
+
+    /* If LAPIC is enabled, interrupts are subject to LVT programming. */
+    if (u8Pin > 1)
+    {
+        /* There are only two local interrupt pins. */
+        AssertMsgFailed(("Invalid LAPIC pin %d\n", u8Pin));
+        return VERR_INVALID_PARAMETER;
+    }
+
+    /* NB: We currently only deliver local interrupts to the first CPU. In theory they
+     * should be delivered to all CPUs and it is the guest's responsibility to ensure
+     * no more than one CPU has the interrupt unmasked.
+     */
+    uint32_t    u32Lvec;
+
+    u32Lvec = s->lvt[APIC_LVT_LINT0 + u8Pin];   /* Fetch corresponding LVT entry. */
+    /* Drop int if entry is masked. May not be correct for level-triggered interrupts. */
+    if (!(u32Lvec & APIC_LVT_MASKED))
+    {   uint8_t     u8Delivery;
+        PDMAPICIRQ  enmType;
+
+        u8Delivery = (u32Lvec >> 8) & 7;
+        switch (u8Delivery) 
+        {
+        case APIC_DM_EXTINT:
+            Assert(u8Pin == 0); /* PIC should be wired to LINT0. */
+            enmType = PDMAPICIRQ_EXTINT;
+            break;
+        case APIC_DM_NMI:
+            Assert(u8Pin == 0); /* NMI should be wired to LINT1. */
+            enmType = PDMAPICIRQ_NMI;
+            break;
+        case APIC_DM_SMI:
+            enmType = PDMAPICIRQ_SMI;
+            break;
+
+        }
+        LogFlow(("apicLocalInterrupt: setting local interrupt type %d\n", enmType));
+        cpuSetInterrupt(dev, s, enmType);
+    }
+    return VINF_SUCCESS;
 }
 
@@ -2744 +2811 @@
     ApicReg.pfnReadMSRR3            = apicReadMSR;
     ApicReg.pfnBusDeliverR3         = apicBusDeliverCallback;
+    ApicReg.pfnLocalInterruptR3     = apicLocalInterrupt;
     if (fGCEnabled) {
         ApicReg.pszGetInterruptRC   = "apicGetInterrupt";
@@ -2754 +2822 @@
         ApicReg.pszReadMSRRC        = "apicReadMSR";
         ApicReg.pszBusDeliverRC     = "apicBusDeliverCallback";
+        ApicReg.pszLocalInterruptRC = "apicLocalInterrupt";
     } else {
         ApicReg.pszGetInterruptRC   = NULL;
@@ -2764 +2833 @@
         ApicReg.pszReadMSRRC        = NULL;
         ApicReg.pszBusDeliverRC     = NULL;
+        ApicReg.pszLocalInterruptRC = NULL;
     }
     if (fR0Enabled) {
@@ -2775 +2845 @@
         ApicReg.pszReadMSRR0        = "apicReadMSR";
         ApicReg.pszBusDeliverR0     = "apicBusDeliverCallback";
+        ApicReg.pszLocalInterruptR0 = "apicLocalInterrupt";
     } else {
         ApicReg.pszGetInterruptR0   = NULL;
@@ -2785 +2856 @@
         ApicReg.pszReadMSRR0        = NULL;
         ApicReg.pszBusDeliverR0     = NULL;
+        ApicReg.pszLocalInterruptR0 = NULL;
     }
 

trunk/src/VBox/VMM/PDM.cpp

@@ -424 +424 @@
         pVM->pdm.s.Apic.pfnGetTPRRC         += offDelta;
         pVM->pdm.s.Apic.pfnBusDeliverRC     += offDelta;
+        pVM->pdm.s.Apic.pfnLocalInterruptRC += offDelta;
         pVM->pdm.s.Apic.pfnWriteMSRRC       += offDelta;
         pVM->pdm.s.Apic.pfnReadMSRRC        += offDelta;

trunk/src/VBox/VMM/PDMDevHlp.cpp

@@ -1618 +1618 @@
     VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
     LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: pApicReg=%p:{.u32Version=%#x, .pfnGetInterruptR3=%p, .pfnSetBaseR3=%p, .pfnGetBaseR3=%p, "
-             ".pfnSetTPRR3=%p, .pfnGetTPRR3=%p, .pfnWriteMSR3=%p, .pfnReadMSR3=%p, .pfnBusDeliverR3=%p, pszGetInterruptRC=%p:{%s}, pszSetBaseRC=%p:{%s}, pszGetBaseRC=%p:{%s}, "
-             ".pszSetTPRRC=%p:{%s}, .pszGetTPRRC=%p:{%s}, .pszWriteMSRRC=%p:{%s}, .pszReadMSRRC=%p:{%s}, .pszBusDeliverRC=%p:{%s}} ppApicHlpR3=%p\n",
+             ".pfnSetTPRR3=%p, .pfnGetTPRR3=%p, .pfnWriteMSR3=%p, .pfnReadMSR3=%p, .pfnBusDeliverR3=%p, .pfnLocalInterruptR3=%p, pszGetInterruptRC=%p:{%s}, pszSetBaseRC=%p:{%s}, pszGetBaseRC=%p:{%s}, "
+             ".pszSetTPRRC=%p:{%s}, .pszGetTPRRC=%p:{%s}, .pszWriteMSRRC=%p:{%s}, .pszReadMSRRC=%p:{%s}, .pszBusDeliverRC=%p:{%s}, .pszLocalInterruptRC=%p:{%s}} ppApicHlpR3=%p\n",
              pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pApicReg, pApicReg->u32Version, pApicReg->pfnGetInterruptR3, pApicReg->pfnSetBaseR3,
-             pApicReg->pfnGetBaseR3, pApicReg->pfnSetTPRR3, pApicReg->pfnGetTPRR3, pApicReg->pfnWriteMSRR3, pApicReg->pfnReadMSRR3, pApicReg->pfnBusDeliverR3, pApicReg->pszGetInterruptRC,
+             pApicReg->pfnGetBaseR3, pApicReg->pfnSetTPRR3, pApicReg->pfnGetTPRR3, pApicReg->pfnWriteMSRR3, pApicReg->pfnReadMSRR3, pApicReg->pfnBusDeliverR3, pApicReg->pfnLocalInterruptR3, pApicReg->pszGetInterruptRC,
              pApicReg->pszGetInterruptRC, pApicReg->pszSetBaseRC, pApicReg->pszSetBaseRC, pApicReg->pszGetBaseRC, pApicReg->pszGetBaseRC,
              pApicReg->pszSetTPRRC, pApicReg->pszSetTPRRC, pApicReg->pszGetTPRRC, pApicReg->pszGetTPRRC, pApicReg->pszWriteMSRRC, pApicReg->pszWriteMSRRC, pApicReg->pszReadMSRRC, pApicReg->pszReadMSRRC, pApicReg->pszBusDeliverRC,
-             pApicReg->pszBusDeliverRC, ppApicHlpR3));
+             pApicReg->pszBusDeliverRC, pApicReg->pszLocalInterruptRC, pApicReg->pszLocalInterruptRC, ppApicHlpR3));
 
     /*
@@ -1643 +1643 @@
         ||  !pApicReg->pfnWriteMSRR3
         ||  !pApicReg->pfnReadMSRR3
-        ||  !pApicReg->pfnBusDeliverR3)
+        ||  !pApicReg->pfnBusDeliverR3
+        ||  !pApicReg->pfnLocalInterruptR3)
     {
         Assert(pApicReg->pfnGetInterruptR3);
@@ -1654 +1655 @@
         Assert(pApicReg->pfnReadMSRR3);
         Assert(pApicReg->pfnBusDeliverR3);
+        Assert(pApicReg->pfnLocalInterruptR3);
         LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc (R3 callbacks)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
         return VERR_INVALID_PARAMETER;
@@ -1665 +1667 @@
             ||  pApicReg->pszWriteMSRRC
             ||  pApicReg->pszReadMSRRC
-            ||  pApicReg->pszBusDeliverRC)
+            ||  pApicReg->pszBusDeliverRC
+            ||  pApicReg->pszLocalInterruptRC)
         &&  (   !VALID_PTR(pApicReg->pszGetInterruptRC)
             ||  !VALID_PTR(pApicReg->pszHasPendingIrqRC)
@@ -1674 +1677 @@
             ||  !VALID_PTR(pApicReg->pszWriteMSRRC)
             ||  !VALID_PTR(pApicReg->pszReadMSRRC)
-            ||  !VALID_PTR(pApicReg->pszBusDeliverRC))
+            ||  !VALID_PTR(pApicReg->pszBusDeliverRC)
+            ||  !VALID_PTR(pApicReg->pszLocalInterruptRC))
        )
     {
@@ -1686 +1690 @@
         Assert(VALID_PTR(pApicReg->pszWriteMSRRC));
         Assert(VALID_PTR(pApicReg->pszBusDeliverRC));
+        Assert(VALID_PTR(pApicReg->pszLocalInterruptRC));
         LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc (RC callbacks)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
         return VERR_INVALID_PARAMETER;
@@ -1697 +1702 @@
             ||  pApicReg->pszWriteMSRR0
             ||  pApicReg->pszReadMSRR0
-            ||  pApicReg->pszBusDeliverR0)
+            ||  pApicReg->pszBusDeliverR0
+            ||  pApicReg->pszLocalInterruptR0)
         &&  (   !VALID_PTR(pApicReg->pszGetInterruptR0)
             ||  !VALID_PTR(pApicReg->pszHasPendingIrqR0)
@@ -1706 +1712 @@
             ||  !VALID_PTR(pApicReg->pszReadMSRR0)
             ||  !VALID_PTR(pApicReg->pszWriteMSRR0)
-            ||  !VALID_PTR(pApicReg->pszBusDeliverR0))
+            ||  !VALID_PTR(pApicReg->pszBusDeliverR0)
+            ||  !VALID_PTR(pApicReg->pszLocalInterruptR0))
        )
     {
@@ -1718 +1725 @@
         Assert(VALID_PTR(pApicReg->pszWriteMSRR0));
         Assert(VALID_PTR(pApicReg->pszBusDeliverR0));
+        Assert(VALID_PTR(pApicReg->pszLocalInterruptR0));
         LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc (R0 callbacks)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
         return VERR_INVALID_PARAMETER;
@@ -1786 +1794 @@
             rc = PDMR3LdrGetSymbolRCLazy(pVM, pDevIns->pDevReg->szRCMod, pApicReg->pszBusDeliverRC, &pVM->pdm.s.Apic.pfnBusDeliverRC);
             AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szRCMod, pApicReg->pszBusDeliverRC, rc));
+        }
+        if (RT_SUCCESS(rc))
+        {
+            rc = PDMR3LdrGetSymbolRCLazy(pVM, pDevIns->pDevReg->szRCMod, pApicReg->pszLocalInterruptRC, &pVM->pdm.s.Apic.pfnLocalInterruptRC);
+            AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szRCMod, pApicReg->pszLocalInterruptRC, rc));
         }
         if (RT_FAILURE(rc))
@@ -1806 +1819 @@
         pVM->pdm.s.Apic.pfnReadMSRRC        = 0;
         pVM->pdm.s.Apic.pfnBusDeliverRC     = 0;
+        pVM->pdm.s.Apic.pfnLocalInterruptRC = 0;
     }
 
@@ -1854 +1868 @@
             rc = PDMR3LdrGetSymbolR0Lazy(pVM, pDevIns->pDevReg->szR0Mod, pApicReg->pszBusDeliverR0, &pVM->pdm.s.Apic.pfnBusDeliverR0);
             AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szR0Mod, pApicReg->pszBusDeliverR0, rc));
+        }
+        if (RT_SUCCESS(rc))
+        {
+            rc = PDMR3LdrGetSymbolR0Lazy(pVM, pDevIns->pDevReg->szR0Mod, pApicReg->pszLocalInterruptR0, &pVM->pdm.s.Apic.pfnLocalInterruptR0);
+            AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szR0Mod, pApicReg->pszLocalInterruptR0, rc));
         }
         if (RT_FAILURE(rc))
@@ -1874 +1893 @@
         pVM->pdm.s.Apic.pfnReadMSRR0        = 0;
         pVM->pdm.s.Apic.pfnBusDeliverR0     = 0;
+        pVM->pdm.s.Apic.pfnLocalInterruptR0 = 0;
         pVM->pdm.s.Apic.pDevInsR0           = 0;
     }
@@ -1890 +1910 @@
     pVM->pdm.s.Apic.pfnReadMSRR3        = pApicReg->pfnReadMSRR3;
     pVM->pdm.s.Apic.pfnBusDeliverR3     = pApicReg->pfnBusDeliverR3;
+    pVM->pdm.s.Apic.pfnLocalInterruptR3 = pApicReg->pfnLocalInterruptR3;
     Log(("PDM: Registered APIC device '%s'/%d pDevIns=%p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pDevIns));
 

trunk/src/VBox/VMM/PDMDevMiscHlp.cpp

@@ -48 +48 @@
     PDMDEV_ASSERT_DEVINS(pDevIns);
     PVM pVM = pDevIns->Internal.s.pVMR3;
+
+    if (pVM->pdm.s.Apic.pfnLocalInterruptR3)
+    {
+        LogFlow(("pdmR3PicHlp_SetInterruptFF: caller='%s'/%d: Setting local interrupt on LAPIC\n",
+                 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
+        /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
+        pVM->pdm.s.Apic.pfnLocalInterruptR3(pVM->pdm.s.Apic.pDevInsR3, 0, 1);
+        return;
+    }
+ 
     PVMCPU pVCpu = &pVM->aCpus[0];  /* for PIC we always deliver to CPU 0, MP use APIC */
 
@@ -65 +75 @@
     PVM pVM = pDevIns->Internal.s.pVMR3;
     PVMCPU pVCpu = &pVM->aCpus[0];  /* for PIC we always deliver to CPU 0, MP use APIC */
+
+    if (pVM->pdm.s.Apic.pfnLocalInterruptR3)
+    {
+        /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
+        LogFlow(("pdmR3PicHlp_ClearInterruptFF: caller='%s'/%d: Clearing local interrupt on LAPIC\n",
+                 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
+        /* Lower the LAPIC's LINT0 line instead of signaling the CPU directly. */
+        pVM->pdm.s.Apic.pfnLocalInterruptR3(pVM->pdm.s.Apic.pDevInsR3, 0, 0);
+        return;
+    }
 
     LogFlow(("pdmR3PicHlp_ClearInterruptFF: caller='%s'/%d: VM_FF_INTERRUPT_PIC %d -> 0\n",
@@ -167 +187 @@
             VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_SMI);
             break;
+        case PDMAPICIRQ_EXTINT:
+            VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC);
+            break;
         default:
             AssertMsgFailed(("enmType=%d\n", enmType));
@@ -177 +200 @@
 
 /** @copydoc PDMAPICHLPR3::pfnClearInterruptFF */
-static DECLCALLBACK(void) pdmR3ApicHlp_ClearInterruptFF(PPDMDEVINS pDevIns, VMCPUID idCpu)
+static DECLCALLBACK(void) pdmR3ApicHlp_ClearInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu)
 {
     PDMDEV_ASSERT_DEVINS(pDevIns);
@@ -188 +211 @@
              pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, idCpu, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_APIC)));
 
-    VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
+    /* Note: NMI/SMI can't be cleared. */
+    switch (enmType)
+    {
+        case PDMAPICIRQ_HARDWARE:
+            VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
+            break;
+        case PDMAPICIRQ_EXTINT:
+            VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
+            break;
+        default:
+            AssertMsgFailed(("enmType=%d\n", enmType));
+            break;
+    }
     REMR3NotifyInterruptClear(pVM, pVCpu);
 }

trunk/src/VBox/VMM/PDMInternal.h

@@ -438 +438 @@
     DECLR3CALLBACKMEMBER(int,       pfnBusDeliverR3,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
                                                      uint8_t iVector, uint8_t u8Polarity, uint8_t u8TriggerMode));
+    /** @copydoc PDMAPICREG::pfnLocalInterruptR3 */
+    DECLR3CALLBACKMEMBER(int,       pfnLocalInterruptR3,(PPDMDEVINS pDevIns, uint8_t u8Pin, uint8_t u8Level));
 
     /** Pointer to the APIC device instance - R0 Ptr. */
@@ -460 +462 @@
     DECLR0CALLBACKMEMBER(int,       pfnBusDeliverR0,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
                                                      uint8_t iVector, uint8_t u8Polarity, uint8_t u8TriggerMode));
+    /** @copydoc PDMAPICREG::pfnLocalInterruptR3 */
+    DECLR0CALLBACKMEMBER(int,       pfnLocalInterruptR0,(PPDMDEVINS pDevIns, uint8_t u8Pin, uint8_t u8Level));
 
     /** Pointer to the APIC device instance - RC Ptr. */
@@ -482 +486 @@
     DECLRCCALLBACKMEMBER(int,       pfnBusDeliverRC,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
                                                      uint8_t iVector, uint8_t u8Polarity, uint8_t u8TriggerMode));
+    /** @copydoc PDMAPICREG::pfnLocalInterruptR3 */
+    DECLRCCALLBACKMEMBER(int,       pfnLocalInterruptRC,(PPDMDEVINS pDevIns, uint8_t u8Pin, uint8_t u8Level));
+
 } PDMAPIC;
 

trunk/src/VBox/VMM/VMMGC/PDMGCDevice.cpp

@@ -87 +87 @@
  */
 static DECLCALLBACK(void) pdmRCApicHlp_SetInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu);
-static DECLCALLBACK(void) pdmRCApicHlp_ClearInterruptFF(PPDMDEVINS pDevIns, VMCPUID idCpu);
+static DECLCALLBACK(void) pdmRCApicHlp_ClearInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu);
 static DECLCALLBACK(void) pdmRCApicHlp_ChangeFeature(PPDMDEVINS pDevIns, PDMAPICVERSION enmVersion);
 static DECLCALLBACK(int) pdmRCApicHlp_Lock(PPDMDEVINS pDevIns, int rc);
@@ -441 +441 @@
 
 /** @copydoc PDMAPICHLPRC::pfnClearInterruptFF */
-static DECLCALLBACK(void) pdmRCApicHlp_ClearInterruptFF(PPDMDEVINS pDevIns, VMCPUID idCpu)
+static DECLCALLBACK(void) pdmRCApicHlp_ClearInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu)
 {
     PDMDEV_ASSERT_DEVINS(pDevIns);
@@ -451 +451 @@
     LogFlow(("pdmRCApicHlp_ClearInterruptFF: caller=%p/%d: VM_FF_INTERRUPT %d -> 0\n",
              pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_APIC)));
-    VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
+
+    /* Note: NMI/SMI can't be cleared. */
+    switch (enmType)
+    {
+        case PDMAPICIRQ_HARDWARE:
+            VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
+            break;
+        case PDMAPICIRQ_EXTINT:
+            VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
+            break;
+        default:
+            AssertMsgFailed(("enmType=%d\n", enmType));
+            break;
+    }
 }
 

trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp

@@ -90 +90 @@
  */
 static DECLCALLBACK(void) pdmR0ApicHlp_SetInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu);
-static DECLCALLBACK(void) pdmR0ApicHlp_ClearInterruptFF(PPDMDEVINS pDevIns, VMCPUID idCpu);
+static DECLCALLBACK(void) pdmR0ApicHlp_ClearInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu);
 static DECLCALLBACK(void) pdmR0ApicHlp_ChangeFeature(PPDMDEVINS pDevIns, PDMAPICVERSION enmVersion);
 static DECLCALLBACK(int)  pdmR0ApicHlp_Lock(PPDMDEVINS pDevIns, int rc);
@@ -475 +475 @@
 
 /** @copydoc PDMAPICHLPR0::pfnClearInterruptFF */
-static DECLCALLBACK(void) pdmR0ApicHlp_ClearInterruptFF(PPDMDEVINS pDevIns, VMCPUID idCpu)
+static DECLCALLBACK(void) pdmR0ApicHlp_ClearInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu)
 {
     PDMDEV_ASSERT_DEVINS(pDevIns);
@@ -485 +485 @@
     LogFlow(("pdmR0ApicHlp_ClearInterruptFF: caller=%p/%d: VM_FF_INTERRUPT %d -> 0\n",
              pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_APIC)));
-    VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
+
+    /* Note: NMI/SMI can't be cleared. */
+    switch (enmType)
+    {
+        case PDMAPICIRQ_HARDWARE:
+            VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
+            break;
+        case PDMAPICIRQ_EXTINT:
+            VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
+            break;
+        default:
+            AssertMsgFailed(("enmType=%d\n", enmType));
+            break;
+    }
 }