Changeset 2426 in vbox

Timestamp:

Apr 30, 2007 12:36:15 PM (18 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

20835

Message:

Removed the old recompiler code. (wonder why subversion didn't pick up these changes right way)

Location:

trunk/src/recompiler

Files:

• target-i386/helper.c (modified) (60 diffs)
• tests/Makefile (modified) (4 diffs)
• tests/qruncom.c (modified) (6 diffs)
• tests/test-i386-code16.S (modified) (1 diff)
• tests/test-i386-muldiv.h (modified) (4 diffs)
• tests/test-i386-shift.h (modified) (5 diffs)
• tests/test-i386.c (modified) (48 diffs)
• tests/test-i386.h (modified) (1 diff)

trunk/src/recompiler/target-i386/helper.c

@@ -18 +18 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
+#ifdef VBOX
+# include <VBox/err.h>
+#endif
 #include "exec.h"
-#ifdef VBOX
-#include <VBox/err.h>
-#endif
 
 //#define DEBUG_PCALL
@@ -28 +28 @@
 #define raise_exception_err(a, b)\
 do {\
-    fprintf(logfile, "raise_exception line=%d\n", __LINE__);\
+    if (logfile)\
+        fprintf(logfile, "raise_exception line=%d\n", __LINE__);\
     (raise_exception_err)(a, b);\
 } while (0)
@@ -224 +225 @@
             if ((e2 & DESC_C_MASK) && dpl > rpl)
                 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
-                
         } else if (seg_reg == R_SS) {
             /* SS must be writable data */
@@ -380 +380 @@
         for(i = 0; i < 6; i++)
             stw_kernel(env->tr.base + (0x48 + i * 4), env->segs[i].selector);
-
 #if defined(VBOX) && defined(DEBUG)
         printf("TSS 32 bits switch\n");
         printf("Saving CS=%08X\n", env->segs[R_CS].selector);
 #endif
-
     } else {
         /* 16 bit */
@@ -567 +565 @@
 }
 
+#ifdef TARGET_X86_64
+#define SET_ESP(val, sp_mask)\
+do {\
+    if ((sp_mask) == 0xffff)\
+        ESP = (ESP & ~0xffff) | ((val) & 0xffff);\
+    else if ((sp_mask) == 0xffffffffLL)\
+        ESP = (uint32_t)(val);\
+    else\
+        ESP = (val);\
+} while (0)
+#else
+#define SET_ESP(val, sp_mask) ESP = (ESP & ~(sp_mask)) | ((val) & (sp_mask))
+#endif
+
 /* XXX: add a is_user flag to have proper security support */
 #define PUSHW(ssp, sp, sp_mask, val)\
@@ -598 +610 @@
     SegmentCache *dt;
     target_ulong ptr, ssp;
-    int type, dpl, selector, ss_dpl, cpl, sp_mask;
+    int type, dpl, selector, ss_dpl, cpl;
     int has_error_code, new_stack, shift;
     uint32_t e1, e2, offset, ss, esp, ss_e1, ss_e2;
-    uint32_t old_eip;
+    uint32_t old_eip, sp_mask;
 
 #ifdef VBOX
@@ -642 +654 @@
         switch_tss(intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
         if (has_error_code) {
-            int mask, type;
+            int type;
+            uint32_t mask;
             /* push the error code */
             type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
@@ -656 +669 @@
             else
                 stw_kernel(ssp, error_code);
-            ESP = (esp & mask) | (ESP & ~mask);
+            SET_ESP(esp, mask);
         }
         return;
@@ -787 +800 @@
                                ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
     }
-    ESP = (ESP & ~sp_mask) | (esp & sp_mask);
+    SET_ESP(esp, sp_mask);
 
     selector = (selector & ~3) | dpl;
@@ -896 +909 @@
         env->eflags &= ~IF_MASK;
 }
-#endif
+#endif /* VBOX */
 
 #ifdef TARGET_X86_64
@@ -1078 +1091 @@
         cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc, 
                            0, 0xffffffff, 
-                               DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
+                               DESC_G_MASK | DESC_P_MASK |
                                DESC_S_MASK |
                                DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | DESC_L_MASK);
@@ -1129 +1142 @@
             cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3, 
                                    0, 0xffffffff, 
-                                   DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
+                                   DESC_G_MASK | DESC_P_MASK |
                                    DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
                                    DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | 
@@ -1184 +1197 @@
 void helper_external_event(void)
 {
+#if defined(__DARWIN__) && defined(VBOX_STRICT)
+# if 0
+    //uintptr_t uFrameAddr = (uintptr_t)__builtin_frame_address(0); - this is broken (uses %ebp)
+    //AssertMsg(!( (uFrameAddr - sizeof(uintptr_t)) & 7 ), ("uFrameAddr=%#p\n", uFrameAddr));
+# else     
+    uintptr_t uESP;
+    __asm__ __volatile__("movl %%esp, %0" : "=r" (uESP));
+    AssertMsg(!(uESP & 15), ("esp=%#p\n", uESP));
+# endif
+#endif 
     if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_HARD)
     {
@@ -1278 +1301 @@
                   target_ulong next_eip, int is_hw)
 {
-#ifdef DEBUG_PCALL
-    if (loglevel & (CPU_LOG_PCALL | CPU_LOG_INT)) {
+    if (loglevel & CPU_LOG_INT) {
         if ((env->cr[0] & CR0_PE_MASK)) {
             static int count;
@@ -1294 +1316 @@
             }
             fprintf(logfile, "\n");
+            cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
 #if 0
-            cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
             {
                 int i;
@@ -1310 +1332 @@
         }
     }
-#endif
     if (env->cr[0] & CR0_PE_MASK) {
 #if TARGET_X86_64
@@ -1328 +1349 @@
                 do_soft_interrupt_vme(intno, error_code, next_eip);
             else
-#endif
+#endif /* VBOX */
                 do_interrupt_protected(intno, is_int, error_code, next_eip, is_hw);
         }
@@ -1376 +1397 @@
     raise_interrupt(exception_index, 0, 0, 0);
 }
+
+/* SMM support */
+
+#if defined(CONFIG_USER_ONLY) 
+
+void do_smm_enter(void)
+{
+}
+
+void helper_rsm(void)
+{
+}
+
+#else
+
+#ifdef TARGET_X86_64
+#define SMM_REVISION_ID 0x00020064
+#else
+#define SMM_REVISION_ID 0x00020000
+#endif
+
+void do_smm_enter(void)
+{
+#ifdef VBOX 
+    cpu_abort(env, "do_ssm_enter");
+#else /* !VBOX */
+    target_ulong sm_state;
+    SegmentCache *dt;
+    int i, offset;
+
+    if (loglevel & CPU_LOG_INT) {
+        fprintf(logfile, "SMM: enter\n");
+        cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
+    }
+
+    env->hflags |= HF_SMM_MASK;
+    cpu_smm_update(env);
+
+    sm_state = env->smbase + 0x8000;
+    
+#ifdef TARGET_X86_64
+    for(i = 0; i < 6; i++) {
+        dt = &env->segs[i];
+        offset = 0x7e00 + i * 16;
+        stw_phys(sm_state + offset, dt->selector);
+        stw_phys(sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
+        stl_phys(sm_state + offset + 4, dt->limit);
+        stq_phys(sm_state + offset + 8, dt->base);
+    }
+
+    stq_phys(sm_state + 0x7e68, env->gdt.base);
+    stl_phys(sm_state + 0x7e64, env->gdt.limit);
+
+    stw_phys(sm_state + 0x7e70, env->ldt.selector);
+    stq_phys(sm_state + 0x7e78, env->ldt.base);
+    stl_phys(sm_state + 0x7e74, env->ldt.limit);
+    stw_phys(sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
+    
+    stq_phys(sm_state + 0x7e88, env->idt.base);
+    stl_phys(sm_state + 0x7e84, env->idt.limit);
+
+    stw_phys(sm_state + 0x7e90, env->tr.selector);
+    stq_phys(sm_state + 0x7e98, env->tr.base);
+    stl_phys(sm_state + 0x7e94, env->tr.limit);
+    stw_phys(sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
+    
+    stq_phys(sm_state + 0x7ed0, env->efer);
+
+    stq_phys(sm_state + 0x7ff8, EAX);
+    stq_phys(sm_state + 0x7ff0, ECX);
+    stq_phys(sm_state + 0x7fe8, EDX);
+    stq_phys(sm_state + 0x7fe0, EBX);
+    stq_phys(sm_state + 0x7fd8, ESP);
+    stq_phys(sm_state + 0x7fd0, EBP);
+    stq_phys(sm_state + 0x7fc8, ESI);
+    stq_phys(sm_state + 0x7fc0, EDI);
+    for(i = 8; i < 16; i++) 
+        stq_phys(sm_state + 0x7ff8 - i * 8, env->regs[i]);
+    stq_phys(sm_state + 0x7f78, env->eip);
+    stl_phys(sm_state + 0x7f70, compute_eflags());
+    stl_phys(sm_state + 0x7f68, env->dr[6]);
+    stl_phys(sm_state + 0x7f60, env->dr[7]);
+
+    stl_phys(sm_state + 0x7f48, env->cr[4]);
+    stl_phys(sm_state + 0x7f50, env->cr[3]);
+    stl_phys(sm_state + 0x7f58, env->cr[0]);
+
+    stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
+    stl_phys(sm_state + 0x7f00, env->smbase);
+#else
+    stl_phys(sm_state + 0x7ffc, env->cr[0]);
+    stl_phys(sm_state + 0x7ff8, env->cr[3]);
+    stl_phys(sm_state + 0x7ff4, compute_eflags());
+    stl_phys(sm_state + 0x7ff0, env->eip);
+    stl_phys(sm_state + 0x7fec, EDI);
+    stl_phys(sm_state + 0x7fe8, ESI);
+    stl_phys(sm_state + 0x7fe4, EBP);
+    stl_phys(sm_state + 0x7fe0, ESP);
+    stl_phys(sm_state + 0x7fdc, EBX);
+    stl_phys(sm_state + 0x7fd8, EDX);
+    stl_phys(sm_state + 0x7fd4, ECX);
+    stl_phys(sm_state + 0x7fd0, EAX);
+    stl_phys(sm_state + 0x7fcc, env->dr[6]);
+    stl_phys(sm_state + 0x7fc8, env->dr[7]);
+    
+    stl_phys(sm_state + 0x7fc4, env->tr.selector);
+    stl_phys(sm_state + 0x7f64, env->tr.base);
+    stl_phys(sm_state + 0x7f60, env->tr.limit);
+    stl_phys(sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
+    
+    stl_phys(sm_state + 0x7fc0, env->ldt.selector);
+    stl_phys(sm_state + 0x7f80, env->ldt.base);
+    stl_phys(sm_state + 0x7f7c, env->ldt.limit);
+    stl_phys(sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
+    
+    stl_phys(sm_state + 0x7f74, env->gdt.base);
+    stl_phys(sm_state + 0x7f70, env->gdt.limit);
+
+    stl_phys(sm_state + 0x7f58, env->idt.base);
+    stl_phys(sm_state + 0x7f54, env->idt.limit);
+
+    for(i = 0; i < 6; i++) {
+        dt = &env->segs[i];
+        if (i < 3)
+            offset = 0x7f84 + i * 12;
+        else
+            offset = 0x7f2c + (i - 3) * 12;
+        stl_phys(sm_state + 0x7fa8 + i * 4, dt->selector);
+        stl_phys(sm_state + offset + 8, dt->base);
+        stl_phys(sm_state + offset + 4, dt->limit);
+        stl_phys(sm_state + offset, (dt->flags >> 8) & 0xf0ff);
+    }
+    stl_phys(sm_state + 0x7f14, env->cr[4]);
+
+    stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
+    stl_phys(sm_state + 0x7ef8, env->smbase);
+#endif
+    /* init SMM cpu state */
+
+#ifdef TARGET_X86_64
+    env->efer = 0;
+    env->hflags &= ~HF_LMA_MASK;
+#endif
+    load_eflags(0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
+    env->eip = 0x00008000;
+    cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
+                           0xffffffff, 0);
+    cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff, 0);
+    cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff, 0);
+    cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff, 0);
+    cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff, 0);
+    cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff, 0);
+    
+    cpu_x86_update_cr0(env, 
+                       env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK | CR0_PG_MASK));
+    cpu_x86_update_cr4(env, 0);
+    env->dr[7] = 0x00000400;
+    CC_OP = CC_OP_EFLAGS;
+#endif /* VBOX */
+}
+
+void helper_rsm(void)
+{
+#ifdef VBOX
+   cpu_abort(env, "helper_rsm");
+#else /* !VBOX */
+    target_ulong sm_state;
+    int i, offset;
+    uint32_t val;
+
+    sm_state = env->smbase + 0x8000;
+#ifdef TARGET_X86_64
+    env->efer = ldq_phys(sm_state + 0x7ed0);
+    if (env->efer & MSR_EFER_LMA)
+        env->hflags |= HF_LMA_MASK;
+    else
+        env->hflags &= ~HF_LMA_MASK;
+
+    for(i = 0; i < 6; i++) {
+        offset = 0x7e00 + i * 16;
+        cpu_x86_load_seg_cache(env, i, 
+                               lduw_phys(sm_state + offset),
+                               ldq_phys(sm_state + offset + 8),
+                               ldl_phys(sm_state + offset + 4),
+                               (lduw_phys(sm_state + offset + 2) & 0xf0ff) << 8);
+    }
+
+    env->gdt.base = ldq_phys(sm_state + 0x7e68);
+    env->gdt.limit = ldl_phys(sm_state + 0x7e64);
+
+    env->ldt.selector = lduw_phys(sm_state + 0x7e70);
+    env->ldt.base = ldq_phys(sm_state + 0x7e78);
+    env->ldt.limit = ldl_phys(sm_state + 0x7e74);
+    env->ldt.flags = (lduw_phys(sm_state + 0x7e72) & 0xf0ff) << 8;
+    
+    env->idt.base = ldq_phys(sm_state + 0x7e88);
+    env->idt.limit = ldl_phys(sm_state + 0x7e84);
+
+    env->tr.selector = lduw_phys(sm_state + 0x7e90);
+    env->tr.base = ldq_phys(sm_state + 0x7e98);
+    env->tr.limit = ldl_phys(sm_state + 0x7e94);
+    env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8;
+    
+    EAX = ldq_phys(sm_state + 0x7ff8);
+    ECX = ldq_phys(sm_state + 0x7ff0);
+    EDX = ldq_phys(sm_state + 0x7fe8);
+    EBX = ldq_phys(sm_state + 0x7fe0);
+    ESP = ldq_phys(sm_state + 0x7fd8);
+    EBP = ldq_phys(sm_state + 0x7fd0);
+    ESI = ldq_phys(sm_state + 0x7fc8);
+    EDI = ldq_phys(sm_state + 0x7fc0);
+    for(i = 8; i < 16; i++) 
+        env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8);
+    env->eip = ldq_phys(sm_state + 0x7f78);
+    load_eflags(ldl_phys(sm_state + 0x7f70), 
+                ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
+    env->dr[6] = ldl_phys(sm_state + 0x7f68);
+    env->dr[7] = ldl_phys(sm_state + 0x7f60);
+
+    cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f48));
+    cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7f50));
+    cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7f58));
+
+    val = ldl_phys(sm_state + 0x7efc); /* revision ID */
+    if (val & 0x20000) {
+        env->smbase = ldl_phys(sm_state + 0x7f00) & ~0x7fff;
+    }
+#else
+    cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7ffc));
+    cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7ff8));
+    load_eflags(ldl_phys(sm_state + 0x7ff4), 
+                ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
+    env->eip = ldl_phys(sm_state + 0x7ff0);
+    EDI = ldl_phys(sm_state + 0x7fec);
+    ESI = ldl_phys(sm_state + 0x7fe8);
+    EBP = ldl_phys(sm_state + 0x7fe4);
+    ESP = ldl_phys(sm_state + 0x7fe0);
+    EBX = ldl_phys(sm_state + 0x7fdc);
+    EDX = ldl_phys(sm_state + 0x7fd8);
+    ECX = ldl_phys(sm_state + 0x7fd4);
+    EAX = ldl_phys(sm_state + 0x7fd0);
+    env->dr[6] = ldl_phys(sm_state + 0x7fcc);
+    env->dr[7] = ldl_phys(sm_state + 0x7fc8);
+    
+    env->tr.selector = ldl_phys(sm_state + 0x7fc4) & 0xffff;
+    env->tr.base = ldl_phys(sm_state + 0x7f64);
+    env->tr.limit = ldl_phys(sm_state + 0x7f60);
+    env->tr.flags = (ldl_phys(sm_state + 0x7f5c) & 0xf0ff) << 8;
+    
+    env->ldt.selector = ldl_phys(sm_state + 0x7fc0) & 0xffff;
+    env->ldt.base = ldl_phys(sm_state + 0x7f80);
+    env->ldt.limit = ldl_phys(sm_state + 0x7f7c);
+    env->ldt.flags = (ldl_phys(sm_state + 0x7f78) & 0xf0ff) << 8;
+    
+    env->gdt.base = ldl_phys(sm_state + 0x7f74);
+    env->gdt.limit = ldl_phys(sm_state + 0x7f70);
+
+    env->idt.base = ldl_phys(sm_state + 0x7f58);
+    env->idt.limit = ldl_phys(sm_state + 0x7f54);
+
+    for(i = 0; i < 6; i++) {
+        if (i < 3)
+            offset = 0x7f84 + i * 12;
+        else
+            offset = 0x7f2c + (i - 3) * 12;
+        cpu_x86_load_seg_cache(env, i, 
+                               ldl_phys(sm_state + 0x7fa8 + i * 4) & 0xffff,
+                               ldl_phys(sm_state + offset + 8),
+                               ldl_phys(sm_state + offset + 4),
+                               (ldl_phys(sm_state + offset) & 0xf0ff) << 8);
+    }
+    cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f14));
+
+    val = ldl_phys(sm_state + 0x7efc); /* revision ID */
+    if (val & 0x20000) {
+        env->smbase = ldl_phys(sm_state + 0x7ef8) & ~0x7fff;
+    }
+#endif
+    CC_OP = CC_OP_EFLAGS;
+    env->hflags &= ~HF_SMM_MASK;
+    cpu_smm_update(env);
+
+    if (loglevel & CPU_LOG_INT) {
+        fprintf(logfile, "SMM: after RSM\n");
+        cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
+    }
+#endif /* !VBOX */
+}
+
+#endif /* !CONFIG_USER_ONLY */
+
 
 #ifdef BUGGY_GCC_DIV64
@@ -1458 +1770 @@
 {
 #ifndef VBOX
-    switch((uint32_t)EAX) {
+    uint32_t index;
+    index = (uint32_t)EAX;
+    
+    /* test if maximum index reached */
+    if (index & 0x80000000) {
+        if (index > env->cpuid_xlevel) 
+            index = env->cpuid_level;
+    } else {
+        if (index > env->cpuid_level) 
+            index = env->cpuid_level;
+    }
+        
+    switch(index) {
     case 0:
-        EAX = 2; /* max EAX index supported */
+        EAX = env->cpuid_level;
         EBX = env->cpuid_vendor1;
         EDX = env->cpuid_vendor2;
@@ -1467 +1791 @@
     case 1:
         EAX = env->cpuid_version;
-        EBX = 0;
+        EBX = 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
         ECX = env->cpuid_ext_features;
         EDX = env->cpuid_features;
         break;
-
-    default:
+    case 2:
         /* cache info: needed for Pentium Pro compatibility */
         EAX = 0x410601;
@@ -1479 +1802 @@
         EDX = 0;
         break;
-
-#ifdef TARGET_X86_64
     case 0x80000000:
-        EAX = 0x80000008;
+        EAX = env->cpuid_xlevel;
         EBX = env->cpuid_vendor1;
         EDX = env->cpuid_vendor2;
@@ -1491 +1812 @@
         EBX = 0;
         ECX = 0;
-        /* long mode + syscall/sysret features */
-        EDX = (env->cpuid_features & 0x0183F3FF) | (1 << 29) | (1 << 11);
+        EDX = env->cpuid_ext2_features;
+        break;
+    case 0x80000002:
+    case 0x80000003:
+    case 0x80000004:
+        EAX = env->cpuid_model[(index - 0x80000002) * 4 + 0];
+        EBX = env->cpuid_model[(index - 0x80000002) * 4 + 1];
+        ECX = env->cpuid_model[(index - 0x80000002) * 4 + 2];
+        EDX = env->cpuid_model[(index - 0x80000002) * 4 + 3];
+        break;
+    case 0x80000005:
+        /* cache info (L1 cache) */
+        EAX = 0x01ff01ff;
+        EBX = 0x01ff01ff;
+        ECX = 0x40020140;
+        EDX = 0x40020140;
+        break;
+    case 0x80000006:
+        /* cache info (L2 cache) */
+        EAX = 0;
+        EBX = 0x42004200;
+        ECX = 0x02008140;
+        EDX = 0;
         break;
     case 0x80000008:
@@ -1501 +1843 @@
         EDX = 0;
         break;
-#endif
+    default:
+        /* reserved values: zero */
+        EAX = 0;
+        EBX = 0;
+        ECX = 0;
+        EDX = 0;
+        break;
     }
 #else /* VBOX */
@@ -1634 +1982 @@
     int index, type, entry_limit;
     target_ulong ptr;
+    
 #ifdef VBOX
     Log(("helper_ltr_T0: old tr=%RTsel {.base=%VGv, .limit=%VGv, .flags=%RX32} new=%RTsel\n", 
@@ -1750 +2099 @@
             if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
                 /* if not conforming code, test rights */
-                if (dpl < cpl || dpl < rpl)
+                if (dpl < cpl || dpl < rpl) 
                     raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
             }
@@ -1890 +2239 @@
     }
 
-    ESP = (ESP & ~esp_mask) | (esp & esp_mask);
+    SET_ESP(esp, esp_mask);
     env->eip = new_eip;
     env->segs[R_CS].selector = new_cs;
@@ -1976 +2325 @@
                 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
             /* from this point, not restartable */
-            ESP = (ESP & ~sp_mask) | (sp & sp_mask);
+            SET_ESP(sp, sp_mask);
             cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
                                    get_seg_base(e1, e2), limit, e2);
@@ -2105 +2454 @@
                        e2);
         cpu_x86_set_cpl(env, dpl);
-        ESP = (ESP & ~sp_mask) | (sp & sp_mask);
+        SET_ESP(sp, sp_mask);
         EIP = offset;
     }
@@ -2122 +2471 @@
     target_ulong ssp;
     int eflags_mask;
-
 #ifdef VBOX
     bool fVME = false;
 
     remR3TrapClear(env->pVM);
-#endif
+#endif /* VBOX */
 
     sp_mask = 0xffff; /* XXXX: use SS segment size ? */
@@ -2154 +2502 @@
         if (    ((new_eflags & IF_MASK) && (env->eflags & VIP_MASK)) 
             ||  (new_eflags & TF_MASK)) 
-        {
             raise_exception(EXCP0D_GPF);
-        }
-    }
-#endif
+    }
+#endif /* VBOX */
 
     ESP = (ESP & ~sp_mask) | (sp & sp_mask);
@@ -2174 +2520 @@
     if (shift == 0)
         eflags_mask &= 0xffff;
-
     load_eflags(new_eflags, eflags_mask);
 
@@ -2185 +2530 @@
             env->eflags &= ~VIF_MASK;
     }
-#endif
+#endif /* VBOX */
 }
 
@@ -2192 +2537 @@
     int dpl;
     uint32_t e2;
-    
+
+    /* XXX: on x86_64, we do not want to nullify FS and GS because
+       they may still contain a valid base. I would be interested to
+       know how a real x86_64 CPU behaves */
+    if ((seg_reg == R_FS || seg_reg == R_GS) && 
+        (env->segs[seg_reg].selector & 0xfffc) == 0)
+        return;
+
     e2 = env->segs[seg_reg].flags;
     dpl = (e2 >> DESC_DPL_SHIFT) & 3;
@@ -2217 +2569 @@
     else
 #endif
-    sp_mask = get_sp_mask(env->segs[R_SS].flags);
+        sp_mask = get_sp_mask(env->segs[R_SS].flags);
     sp = ESP;
     ssp = env->segs[R_SS].base;
@@ -2363 +2715 @@
 #ifdef TARGET_X86_64
             /* NULL ss is allowed in long mode if cpl != 3*/
+            /* XXX: test CS64 ? */
             if ((env->hflags & HF_LMA_MASK) && rpl != 3) {
                 cpu_x86_load_seg_cache(env, R_SS, new_ss, 
@@ -2369 +2722 @@
                                        DESC_S_MASK | (rpl << DESC_DPL_SHIFT) |
                                        DESC_W_MASK | DESC_A_MASK);
+                ss_e2 = DESC_B_MASK; /* XXX: should not be needed ? */
             } else 
 #endif
@@ -2415 +2769 @@
         sp += addend;
     }
-    ESP = (ESP & ~sp_mask) | (sp & sp_mask);
+    SET_ESP(sp, sp_mask);
     env->eip = new_eip;
     if (is_iret) {
@@ -2426 +2780 @@
             eflags_mask |= IOPL_MASK;
 #endif
-
         iopl = (env->eflags >> IOPL_SHIFT) & 3;
         if (cpl <= iopl)
@@ -2495 +2848 @@
         helper_ret_protected(shift, 1, 0);
     }
+#ifdef USE_KQEMU
+    if (kqemu_is_ok(env)) {
+        CC_OP = CC_OP_EFLAGS;
+        env->exception_index = -1;
+        cpu_loop_exit();
+    }
+#endif
 }
 
@@ -2500 +2860 @@
 {
     helper_ret_protected(shift, 0, addend);
+#ifdef USE_KQEMU
+    if (kqemu_is_ok(env)) {
+        env->exception_index = -1;
+        cpu_loop_exit();
+    }
+#endif
 }
 
@@ -2544 +2910 @@
     ESP = ECX;
     EIP = EDX;
+#ifdef USE_KQEMU
+    if (kqemu_is_ok(env)) {
+        env->exception_index = -1;
+        cpu_loop_exit();
+    }
+#endif
 }
 
@@ -2575 +2947 @@
 }
 
-void helper_invlpg(unsigned int addr)
+void helper_invlpg(target_ulong addr)
 {
     cpu_x86_flush_tlb(env, addr);
@@ -2586 +2958 @@
     if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
         raise_exception(EXCP0D_GPF);
-    }    
+    }
     val = cpu_get_tsc(env);
     EAX = (uint32_t)(val);
@@ -2620 +2992 @@
         cpu_set_apic_base(env, val);
         break;
-#ifdef TARGET_X86_64
     case MSR_EFER:
-#define MSR_EFER_UPDATE_MASK (MSR_EFER_SCE | MSR_EFER_LME | \
-                              MSR_EFER_NXE | MSR_EFER_FFXSR)
-        env->efer = (env->efer & ~MSR_EFER_UPDATE_MASK) | 
-            (val & MSR_EFER_UPDATE_MASK);
+        {
+            uint64_t update_mask;
+            update_mask = 0;
+            if (env->cpuid_ext2_features & CPUID_EXT2_SYSCALL)
+                update_mask |= MSR_EFER_SCE;
+            if (env->cpuid_ext2_features & CPUID_EXT2_LM)
+                update_mask |= MSR_EFER_LME;
+            if (env->cpuid_ext2_features & CPUID_EXT2_FFXSR)
+                update_mask |= MSR_EFER_FFXSR;
+            if (env->cpuid_ext2_features & CPUID_EXT2_NX)
+                update_mask |= MSR_EFER_NXE;
+            env->efer = (env->efer & ~update_mask) | 
+            (val & update_mask);
+        }
         break;
     case MSR_STAR:
         env->star = val;
         break;
+    case MSR_PAT:
+        env->pat = val;
+        break;
+#ifdef TARGET_X86_64
     case MSR_LSTAR:
         env->lstar = val;
@@ -2671 +3056 @@
         val = cpu_get_apic_base(env);
         break;
-#ifdef TARGET_X86_64
     case MSR_EFER:
         val = env->efer;
@@ -2678 +3062 @@
         val = env->star;
         break;
+    case MSR_PAT:
+        val = env->pat;
+        break;
+#ifdef TARGET_X86_64
     case MSR_LSTAR:
         val = env->lstar;
@@ -2927 +3315 @@
 void helper_fbst_ST0_A0(void)
 {
-    CPU86_LDouble tmp;
     int v;
     target_ulong mem_ref, mem_end;
     int64_t val;
 
-    tmp = rint(ST0);
-    val = (int64_t)tmp;
+    val = floatx_to_int64(ST0, &env->fp_status);
     mem_ref = A0;
     mem_end = mem_ref + 9;
@@ -3126 +3512 @@
 void helper_frndint(void)
 {
-    CPU86_LDouble a;
-
-    a = ST0;
-#ifdef __arm__
-    switch(env->fpuc & RC_MASK) {
-    default:
-    case RC_NEAR:
-        asm("rndd %0, %1" : "=f" (a) : "f"(a));
-        break;
-    case RC_DOWN:
-        asm("rnddm %0, %1" : "=f" (a) : "f"(a));
-        break;
-    case RC_UP:
-        asm("rnddp %0, %1" : "=f" (a) : "f"(a));
-        break;
-    case RC_CHOP:
-        asm("rnddz %0, %1" : "=f" (a) : "f"(a));
-        break;
-    }
-#else
-    a = rint(a);
-#endif
-    ST0 = a;
+    ST0 = floatx_round_to_int(ST0, &env->fp_status);
 }
 
 void helper_fscale(void)
 {
-    CPU86_LDouble fpsrcop, fptemp;
-
-    fpsrcop = 2.0;
-    fptemp = pow(fpsrcop,ST1);
-    ST0 *= fptemp;
+    ST0 = ldexp (ST0, (int)(ST1)); 
 }
 
@@ -3395 +3755 @@
 
     if (env->cr[4] & CR4_OSFXSR_MASK) {
-        /* XXX: finish it, endianness */
+        /* XXX: finish it */
         env->mxcsr = ldl(ptr + 0x18);
         //ldl(ptr + 0x1c);
@@ -3523 +3883 @@
     *phigh += v;
 #ifdef DEBUG_MULDIV
-    printf("mul: 0x%016llx * 0x%016llx = 0x%016llx%016llx\n",
+    printf("mul: 0x%016" PRIx64 " * 0x%016" PRIx64 " = 0x%016" PRIx64 "%016" PRIx64 "\n",
            a, b, *phigh, *plow);
 #endif
@@ -3572 +3932 @@
         }
 #if defined(DEBUG_MULDIV)
-        printf("div: 0x%016llx%016llx / 0x%016llx: q=0x%016llx r=0x%016llx\n",
+        printf("div: 0x%016" PRIx64 "%016" PRIx64 " / 0x%016" PRIx64 ": q=0x%016" PRIx64 " r=0x%016" PRIx64 "\n",
                *phigh, *plow, b, a0, a1);
 #endif
@@ -3666 +4026 @@
 }
 
-#endif
-
-/* XXX: do it */
-int fpu_isnan(double a)
-{
-    return 0;
-}
+void helper_bswapq_T0(void)
+{
+    T0 = bswap64(T0);
+}
+#endif
 
 void helper_hlt(void)
 {
     env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
+    env->hflags |= HF_HALTED_MASK;
     env->exception_index = EXCP_HLT;
     cpu_loop_exit();
@@ -3683 +4042 @@
 void helper_monitor(void)
 {
-    if (ECX != 0)
+    if ((uint32_t)ECX != 0)
         raise_exception(EXCP0D_GPF);
     /* XXX: store address ? */
@@ -3690 +4049 @@
 void helper_mwait(void)
 {
-    if (ECX != 0)
+    if ((uint32_t)ECX != 0)
         raise_exception(EXCP0D_GPF);
 #ifdef VBOX
@@ -3715 +4074 @@
 }
 
-/* XXX: find a better solution */
-double helper_sqrt(double a)
-{
-    return sqrt(a);
+void update_fp_status(void)
+{
+    int rnd_type;
+
+    /* set rounding mode */
+    switch(env->fpuc & RC_MASK) {
+    default:
+    case RC_NEAR:
+        rnd_type = float_round_nearest_even;
+        break;
+    case RC_DOWN:
+        rnd_type = float_round_down;
+        break;
+    case RC_UP:
+        rnd_type = float_round_up;
+        break;
+    case RC_CHOP:
+        rnd_type = float_round_to_zero;
+        break;
+    }
+    set_float_rounding_mode(rnd_type, &env->fp_status);
+#ifdef FLOATX80
+    switch((env->fpuc >> 8) & 3) {
+    case 0:
+        rnd_type = 32;
+        break;
+    case 2:
+        rnd_type = 64;
+        break;
+    case 3:
+    default:
+        rnd_type = 80;
+        break;
+    }
+    set_floatx80_rounding_precision(rnd_type, &env->fp_status);
+#endif
 }
 
@@ -3769 +4160 @@
         }
         if (retaddr)
-            raise_exception_err(EXCP0E_PAGE, env->error_code);
-        else {
-            raise_exception_err_norestore(EXCP0E_PAGE, env->error_code);
-        }
+            raise_exception_err(env->exception_index, env->error_code);
+        else
+            raise_exception_err_norestore(env->exception_index, env->error_code);
     }
     env = saved_env;
 }
 
-#if defined(VBOX)
+#ifdef VBOX
 
 /**
@@ -4029 +4419 @@
     int csize;
     void (*gen_func)(void);
-    uint8_t *pvCode;
+    uint8_t *tc_ptr;
     uint32_t old_eip;
 
@@ -4038 +4428 @@
     RAWEx_ProfileStart(env, STATS_EMULATE_SINGLE_INSTR);
 
-    pvCode = env->pvCodeBuffer;
-
-    // Setup temporary translation block
-    tb_temp.hash_next = 0;
-    tb_temp.jmp_first = 0;
-    tb_temp.jmp_next[0] = 0;
-    tb_temp.jmp_next[1] = 0;
+    tc_ptr = env->pvCodeBuffer;
+
+    /*
+     * Setup temporary translation block.
+     */
+    /* tb_alloc: */
+    tb_temp.pc = env->segs[R_CS].base + env->eip;
+    tb_temp.cflags = 0;
+
+    /* tb_find_slow: */
+    tb_temp.tc_ptr = tc_ptr;
+    tb_temp.cs_base = env->segs[R_CS].base;
+    tb_temp.flags = env->hflags | (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
+
+    /* Initialize the rest with sensible values. */
+    tb_temp.size = 0;
+    tb_temp.phys_hash_next = NULL;
+    tb_temp.page_next[0] = NULL;
+    tb_temp.page_next[1] = NULL;
     tb_temp.page_addr[0] = 0;
     tb_temp.page_addr[1] = 0;
-    tb_temp.page_next[0] = 0;
-    tb_temp.page_next[1] = 0;
-    tb_temp.hash_next = 0;
-
     tb_temp.tb_next_offset[0] = 0xffff;
     tb_temp.tb_next_offset[1] = 0xffff;
-
-    tb_temp.cs_base = (unsigned long)env->segs[R_CS].base;
-    tb_temp.pc      = tb_temp.cs_base + env->eip;
-    tb_temp.cflags  = 0;
-    tb_temp.flags   = env->hflags;
-    tb_temp.flags  |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
-    tb_temp.tc_ptr  = pvCode;
+    tb_temp.tb_next[0] = 0xffff;
+    tb_temp.tb_next[1] = 0xffff;
+    tb_temp.jmp_next[0] = NULL;
+    tb_temp.jmp_next[1] = NULL;
+    tb_temp.jmp_first = NULL;
 
     current = env->current_tb;
     env->current_tb = NULL;
 
-    // Translate only one instruction 
-    ASMAtomicOrS32(&env->state, CPU_EMULATE_SINGLE_INSTR);
+    /* 
+     * Translate only one instruction.
+     */
+    ASMAtomicOrU32(&env->state, CPU_EMULATE_SINGLE_INSTR);
     if (cpu_gen_code(env, &tb_temp, env->cbCodeBuffer, &csize) < 0)
     {
         AssertFailed();
         RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
-        ASMAtomicAndS32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
+        ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
         env = savedenv;
         return -1;
@@ -4079 +4477 @@
         RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
         AssertFailed();
-        ASMAtomicAndS32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
+        ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
         env = savedenv;
         return -1;
     }
-    if (tb_temp.tc_ptr != pvCode)
+    if (tb_temp.tc_ptr != tc_ptr)
     {
         RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
         AssertFailed();
-        ASMAtomicAndS32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
+        ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
         env = savedenv;
         return -1;
     }
 #endif
-    ASMAtomicAndS32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
-
-    tb_link(&tb_temp);
-
+    ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
+
+    /* tb_link_phys: */
+    tb_temp.jmp_first = (TranslationBlock *)((intptr_t)&tb_temp | 2);
+    Assert(tb_temp.jmp_next[0] == NULL); Assert(tb_temp.jmp_next[1] == NULL);
+    if (tb_temp.tb_next_offset[0] != 0xffff)
+        tb_set_jmp_target(&tb_temp, 0, (uintptr_t)(tb_temp.tc_ptr + tb_temp.tb_next_offset[0]));
+    if (tb_temp.tb_next_offset[1] != 0xffff)
+        tb_set_jmp_target(&tb_temp, 1, (uintptr_t)(tb_temp.tc_ptr + tb_temp.tb_next_offset[1]));
+
+    /*
+     * Execute it using emulation
+     */
     old_eip = env->eip;
-    // Execute it using emulation
     gen_func = (void *)tb_temp.tc_ptr;
     env->current_tb = &tb_temp;
@@ -4119 +4525 @@
     env->current_tb = current;
 
+    Assert(tb_temp.phys_hash_next == NULL);
+    Assert(tb_temp.page_next[0] == NULL);
+    Assert(tb_temp.page_next[1] == NULL);
+    Assert(tb_temp.page_addr[0] == 0);
+    Assert(tb_temp.page_addr[1] == 0);
+/*
+    Assert(tb_temp.tb_next_offset[0] == 0xffff);
+    Assert(tb_temp.tb_next_offset[1] == 0xffff);
+    Assert(tb_temp.tb_next[0] == 0xffff);
+    Assert(tb_temp.tb_next[1] == 0xffff);
+    Assert(tb_temp.jmp_next[0] == NULL);
+    Assert(tb_temp.jmp_next[1] == NULL);
+    Assert(tb_temp.jmp_first == NULL); */
+    
     RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
 
+    /*                                                              
+     * Execute the next instruction when we encounter instruction fusing.
+     */
     if (env->hflags & HF_INHIBIT_IRQ_MASK)
     {

trunk/src/recompiler/tests/Makefile

@@ -1 @@
-#-include ../config-host.mak
-CC=gcc
+-include ../config-host.mak
+
 CFLAGS=-Wall -O2 -g
+#CFLAGS+=-msse2
 LDFLAGS=
 
 ifeq ($(ARCH),i386)
 TESTS=linux-test testthread sha1-i386 test-i386 runcom
+endif
+ifeq ($(ARCH),x86_64)
+TESTS=test-x86_64
 endif
 TESTS+=sha1# test_path
@@ -25 +29 @@
         ./$@ || { rm $@; exit 1; }
 
-# i386 emulation test (test various opcodes) */
+# i386/x86_64 emulation test (test various opcodes) */
 test-i386: test-i386.c test-i386-code16.S test-i386-vm86.S \
            test-i386.h test-i386-shift.h test-i386-muldiv.h
-        $(CC) $(CFLAGS) $(LDFLAGS) -static -o $@ test-i386.c \
-              test-i386-code16.S test-i386-vm86.S -lm
+        $(CC) $(CFLAGS) $(LDFLAGS) -static -o $@ \
+              test-i386.c test-i386-code16.S test-i386-vm86.S -lm
+
+test-x86_64: test-i386.c \
+           test-i386.h test-i386-shift.h test-i386-muldiv.h
+        $(CC) $(CFLAGS) $(LDFLAGS) -static -o $@ test-i386.c -lm
 
 ifeq ($(ARCH),i386)
@@ -65 +73 @@
 # NOTE: -fomit-frame-pointer is currently needed : this is a bug in libqemu
 qruncom: qruncom.c ../i386-user/libqemu.a
-        $(CC) $(CFLAGS) -fomit-frame-pointer $(LDFLAGS) -I../target-i386 -I.. -I../i386-user \
+        $(CC) $(CFLAGS) -fomit-frame-pointer $(LDFLAGS) -I../target-i386 -I.. -I../i386-user -I../fpu \
               -o $@ $< -L../i386-user -lqemu -lm
 
@@ -75 +83 @@
         arm-linux-gcc -Wall -g -O2 -c -o $@ $<
 
+# MIPS test
+hello-mips: hello-mips.c
+        mips-linux-gnu-gcc -nostdlib -static -mno-abicalls -fno-PIC -mabi=32 -Wall -Wextra -g -O2 -o $@ $<
+
+hello-mipsel: hello-mips.c
+        mipsel-linux-gnu-gcc -nostdlib -static -mno-abicalls -fno-PIC -mabi=32 -Wall -Wextra -g -O2 -o $@ $<
+
 # XXX: find a way to compile easily a test for each arch
 test2:
-        @for arch in i386 arm sparc ppc; do \
+        @for arch in i386 arm armeb sparc ppc mips mipsel; do \
            ../$${arch}-user/qemu-$${arch} $${arch}/ls -l linux-test.c ; \
         done
 
 clean:
-        rm -f *~ *.o test-i386.out test-i386.ref qruncom $(TESTS)
+        rm -f *~ *.o test-i386.out test-i386.ref \
+           test-x86_64.log test-x86_64.ref qruncom $(TESTS)

trunk/src/recompiler/tests/qruncom.c

@@ -11 +11 @@
 #include <sys/mman.h>
 #include <signal.h>
+#include <malloc.h>
 
 #include "cpu.h"
 
 //#define SIGTEST
-
-CPUState *cpu_single_env = NULL;
 
 void cpu_outb(CPUState *env, int addr, int val)
@@ -87 +86 @@
 {
     return malloc(size);
+}
+
+void *qemu_mallocz(size_t size)
+{
+    void *ptr;
+    ptr = qemu_malloc(size);
+    if (!ptr)
+        return NULL;
+    memset(ptr, 0, size);
+    return ptr;
+}
+
+void *qemu_vmalloc(size_t size)
+{
+    return memalign(4096, size);
+}
+
+void qemu_vfree(void *ptr)
+{
+    free(ptr);
 }
 
@@ -207 +226 @@
 
     cpu_x86_load_seg_cache(env, R_CS, seg, 
-                           (uint8_t *)(seg << 4), 0xffff, 0);
+                           (seg << 4), 0xffff, 0);
     cpu_x86_load_seg_cache(env, R_SS, seg, 
-                           (uint8_t *)(seg << 4), 0xffff, 0);
+                           (seg << 4), 0xffff, 0);
     cpu_x86_load_seg_cache(env, R_DS, seg, 
-                           (uint8_t *)(seg << 4), 0xffff, 0);
+                           (seg << 4), 0xffff, 0);
     cpu_x86_load_seg_cache(env, R_ES, seg, 
-                           (uint8_t *)(seg << 4), 0xffff, 0);
+                           (seg << 4), 0xffff, 0);
     cpu_x86_load_seg_cache(env, R_FS, seg, 
-                           (uint8_t *)(seg << 4), 0xffff, 0);
+                           (seg << 4), 0xffff, 0);
     cpu_x86_load_seg_cache(env, R_GS, seg, 
-                           (uint8_t *)(seg << 4), 0xffff, 0);
+                           (seg << 4), 0xffff, 0);
 
     /* exception support */
-    env->idt.base = (void *)idt_table;
+    env->idt.base = (unsigned long)idt_table;
     env->idt.limit = sizeof(idt_table) - 1;
     set_idt(0, 0);
@@ -266 +285 @@
             {
                 int int_num, ah;
-                int_num = *(env->segs[R_CS].base + env->eip + 1);
+                int_num = *(uint8_t *)(env->segs[R_CS].base + env->eip + 1);
                 if (int_num != 0x21)
                     goto unknown_int;
@@ -294 +313 @@
                 unknown_int:
                     fprintf(stderr, "unsupported int 0x%02x\n", int_num);
-                    cpu_dump_state(env, stderr, 0);
+                    cpu_dump_state(env, stderr, fprintf, 0);
                     //                    exit(1);
                 }
@@ -302 +321 @@
         default:
             fprintf(stderr, "unhandled cpu_exec return code (0x%x)\n", ret);
-            cpu_dump_state(env, stderr, 0);
+            cpu_dump_state(env, stderr, fprintf, 0);
             exit(1);
         }

trunk/src/recompiler/tests/test-i386-code16.S

@@ -78 +78 @@
 
 code16_end:
-
-
-/* other 32 bits tests */
-        .code32
-
-        .globl func_lret32
-func_lret32:
-        movl $0x87654321, %eax
-        lret
-
-        .globl func_iret32
-func_iret32:
-        movl $0xabcd4321, %eax
-        iret
-
-                
-
-        

trunk/src/recompiler/tests/test-i386-muldiv.h

@@ -1 +1 @@
 
-void glue(glue(test_, OP), b)(int op0, int op1) 
+void glue(glue(test_, OP), b)(long op0, long op1) 
 {
-    int res, s1, s0, flags;
+    long res, s1, s0, flags;
     s0 = op0;
     s1 = op1;
@@ -11 +11 @@
          stringify(OP)"b %b2\n\t" 
          "pushf\n\t"
-         "popl %1\n\t"
+         "pop %1\n\t"
          : "=a" (res), "=g" (flags)
          : "q" (s1), "0" (res), "1" (flags));
-    printf("%-10s A=%08x B=%08x R=%08x CC=%04x\n",
+    printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
            stringify(OP) "b", s0, s1, res, flags & CC_MASK);
 }
 
-void glue(glue(test_, OP), w)(int op0h, int op0, int op1) 
+void glue(glue(test_, OP), w)(long op0h, long op0, long op1) 
 {
-    int res, s1, flags, resh;
+    long res, s1, flags, resh;
     s1 = op1;
     resh = op0h;
@@ -29 +29 @@
          stringify(OP) "w %w3\n\t" 
          "pushf\n\t"
-         "popl %1\n\t"
+         "pop %1\n\t"
          : "=a" (res), "=g" (flags), "=d" (resh)
          : "q" (s1), "0" (res), "1" (flags), "2" (resh));
-    printf("%-10s AH=%08x AL=%08x B=%08x RH=%08x RL=%08x CC=%04x\n",
+    printf("%-10s AH=" FMTLX " AL=" FMTLX " B=" FMTLX " RH=" FMTLX " RL=" FMTLX " CC=%04lx\n",
            stringify(OP) "w", op0h, op0, s1, resh, res, flags & CC_MASK);
 }
 
-void glue(glue(test_, OP), l)(int op0h, int op0, int op1) 
+void glue(glue(test_, OP), l)(long op0h, long op0, long op1) 
 {
-    int res, s1, flags, resh;
+    long res, s1, flags, resh;
     s1 = op1;
     resh = op0h;
@@ -45 +45 @@
     asm ("push %5\n\t"
          "popf\n\t"
-         stringify(OP) "l %3\n\t" 
+         stringify(OP) "l %k3\n\t" 
          "pushf\n\t"
-         "popl %1\n\t"
+         "pop %1\n\t"
          : "=a" (res), "=g" (flags), "=d" (resh)
          : "q" (s1), "0" (res), "1" (flags), "2" (resh));
-    printf("%-10s AH=%08x AL=%08x B=%08x RH=%08x RL=%08x CC=%04x\n",
+    printf("%-10s AH=" FMTLX " AL=" FMTLX " B=" FMTLX " RH=" FMTLX " RL=" FMTLX " CC=%04lx\n",
            stringify(OP) "l", op0h, op0, s1, resh, res, flags & CC_MASK);
 }
 
+#if defined(__x86_64__)
+void glue(glue(test_, OP), q)(long op0h, long op0, long op1) 
+{
+    long res, s1, flags, resh;
+    s1 = op1;
+    resh = op0h;
+    res = op0;
+    flags = 0;
+    asm ("push %5\n\t"
+         "popf\n\t"
+         stringify(OP) "q %3\n\t" 
+         "pushf\n\t"
+         "pop %1\n\t"
+         : "=a" (res), "=g" (flags), "=d" (resh)
+         : "q" (s1), "0" (res), "1" (flags), "2" (resh));
+    printf("%-10s AH=" FMTLX " AL=" FMTLX " B=" FMTLX " RH=" FMTLX " RL=" FMTLX " CC=%04lx\n",
+           stringify(OP) "q", op0h, op0, s1, resh, res, flags & CC_MASK);
+}
+#endif
+
 #undef OP

trunk/src/recompiler/tests/test-i386-shift.h

@@ -1 +1 @@
 
 #define exec_op glue(exec_, OP)
+#define exec_opq glue(glue(exec_, OP), q)
 #define exec_opl glue(glue(exec_, OP), l)
 #define exec_opw glue(glue(exec_, OP), w)
@@ -8 +9 @@
 
 #ifdef OP_NOBYTE
-#define EXECSHIFT(size, res, s1, s2, flags) \
+#define EXECSHIFT(size, rsize, res, s1, s2, flags) \
     asm ("push %4\n\t"\
          "popf\n\t"\
-         stringify(OP) size " %" size "2, %" size "0\n\t" \
+         stringify(OP) size " %" rsize "2, %" rsize "0\n\t" \
          "pushf\n\t"\
-         "popl %1\n\t"\
+         "pop %1\n\t"\
          : "=g" (res), "=g" (flags)\
          : "r" (s1), "0" (res), "1" (flags));
 #else
-#define EXECSHIFT(size, res, s1, s2, flags) \
+#define EXECSHIFT(size, rsize, res, s1, s2, flags) \
     asm ("push %4\n\t"\
          "popf\n\t"\
-         stringify(OP) size " %%cl, %" size "0\n\t" \
+         stringify(OP) size " %%cl, %" rsize "0\n\t" \
          "pushf\n\t"\
-         "popl %1\n\t"\
+         "pop %1\n\t"\
          : "=q" (res), "=g" (flags)\
          : "c" (s1), "0" (res), "1" (flags));
 #endif
 
-void exec_opl(int s2, int s0, int s1, int iflags)
+#if defined(__x86_64__)
+void exec_opq(long s2, long s0, long s1, long iflags)
 {
-    int res, flags;
+    long res, flags;
     res = s0;
     flags = iflags;
-    EXECSHIFT("", res, s1, s2, flags);
+    EXECSHIFT("q", "", res, s1, s2, flags);
     /* overflow is undefined if count != 1 */
     if (s1 != 1)
       flags &= ~CC_O;
-    printf("%-10s A=%08x B=%08x R=%08x CCIN=%04x CC=%04x\n",
+    printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CCIN=%04lx CC=%04lx\n",
+           stringify(OP) "q", s0, s1, res, iflags, flags & CC_MASK);
+}
+#endif
+
+void exec_opl(long s2, long s0, long s1, long iflags)
+{
+    long res, flags;
+    res = s0;
+    flags = iflags;
+    EXECSHIFT("l", "k", res, s1, s2, flags);
+    /* overflow is undefined if count != 1 */
+    if (s1 != 1)
+      flags &= ~CC_O;
+    printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CCIN=%04lx CC=%04lx\n",
            stringify(OP) "l", s0, s1, res, iflags, flags & CC_MASK);
 }
 
-void exec_opw(int s2, int s0, int s1, int iflags)
+void exec_opw(long s2, long s0, long s1, long iflags)
 {
-    int res, flags;
+    long res, flags;
     res = s0;
     flags = iflags;
-    EXECSHIFT("w", res, s1, s2, flags);
+    EXECSHIFT("w", "w", res, s1, s2, flags);
     /* overflow is undefined if count != 1 */
     if (s1 != 1)
       flags &= ~CC_O;
-    printf("%-10s A=%08x B=%08x R=%08x CCIN=%04x CC=%04x\n",
+    printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CCIN=%04lx CC=%04lx\n",
            stringify(OP) "w", s0, s1, res, iflags, flags & CC_MASK);
 }
 
 #else
-#define EXECSHIFT(size, res, s1, s2, flags) \
+#define EXECSHIFT(size, rsize, res, s1, s2, flags) \
     asm ("push %4\n\t"\
          "popf\n\t"\
-         stringify(OP) size " %%cl, %" size "5, %" size "0\n\t" \
+         stringify(OP) size " %%cl, %" rsize "5, %" rsize "0\n\t" \
          "pushf\n\t"\
-         "popl %1\n\t"\
+         "pop %1\n\t"\
          : "=g" (res), "=g" (flags)\
          : "c" (s1), "0" (res), "1" (flags), "r" (s2));
 
-void exec_opl(int s2, int s0, int s1, int iflags)
+#if defined(__x86_64__)
+void exec_opq(long s2, long s0, long s1, long iflags)
 {
-    int res, flags;
+    long res, flags;
     res = s0;
     flags = iflags;
-    EXECSHIFT("", res, s1, s2, flags);
+    EXECSHIFT("q", "", res, s1, s2, flags);
     /* overflow is undefined if count != 1 */
     if (s1 != 1)
       flags &= ~CC_O;
-    printf("%-10s A=%08x B=%08x C=%08x R=%08x CCIN=%04x CC=%04x\n",
+    printf("%-10s A=" FMTLX " B=" FMTLX " C=" FMTLX " R=" FMTLX " CCIN=%04lx CC=%04lx\n",
+           stringify(OP) "q", s0, s2, s1, res, iflags, flags & CC_MASK);
+}
+#endif
+
+void exec_opl(long s2, long s0, long s1, long iflags)
+{
+    long res, flags;
+    res = s0;
+    flags = iflags;
+    EXECSHIFT("l", "k", res, s1, s2, flags);
+    /* overflow is undefined if count != 1 */
+    if (s1 != 1)
+      flags &= ~CC_O;
+    printf("%-10s A=" FMTLX " B=" FMTLX " C=" FMTLX " R=" FMTLX " CCIN=%04lx CC=%04lx\n",
            stringify(OP) "l", s0, s2, s1, res, iflags, flags & CC_MASK);
 }
 
-void exec_opw(int s2, int s0, int s1, int iflags)
+void exec_opw(long s2, long s0, long s1, long iflags)
 {
-    int res, flags;
+    long res, flags;
     res = s0;
     flags = iflags;
-    EXECSHIFT("w", res, s1, s2, flags);
+    EXECSHIFT("w", "w", res, s1, s2, flags);
     /* overflow is undefined if count != 1 */
     if (s1 != 1)
       flags &= ~CC_O;
-    printf("%-10s A=%08x B=%08x C=%08x R=%08x CCIN=%04x CC=%04x\n",
+    printf("%-10s A=" FMTLX " B=" FMTLX " C=" FMTLX " R=" FMTLX " CCIN=%04lx CC=%04lx\n",
            stringify(OP) "w", s0, s2, s1, res, iflags, flags & CC_MASK);
 }
@@ -92 +123 @@
 
 #ifndef OP_NOBYTE
-void exec_opb(int s0, int s1, int iflags)
+void exec_opb(long s0, long s1, long iflags)
 {
-    int res, flags;
+    long res, flags;
     res = s0;
     flags = iflags;
-    EXECSHIFT("b", res, s1, 0, flags);
+    EXECSHIFT("b", "b", res, s1, 0, flags);
     /* overflow is undefined if count != 1 */
     if (s1 != 1)
       flags &= ~CC_O;
-    printf("%-10s A=%08x B=%08x R=%08x CCIN=%04x CC=%04x\n",
+    printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CCIN=%04lx CC=%04lx\n",
            stringify(OP) "b", s0, s1, res, iflags, flags & CC_MASK);
 }
 #endif
 
-void exec_op(int s2, int s0, int s1)
+void exec_op(long s2, long s0, long s1)
 {
+    s2 = i2l(s2);
+    s0 = i2l(s0);
+#if defined(__x86_64__)
+    exec_opq(s2, s0, s1, 0);
+#endif
     exec_opl(s2, s0, s1, 0);
 #ifdef OP_SHIFTD
@@ -119 +155 @@
 #endif
 #ifdef OP_CC
+#if defined(__x86_64__)
+    exec_opq(s2, s0, s1, CC_C);
+#endif
     exec_opl(s2, s0, s1, CC_C);
     exec_opw(s2, s0, s1, CC_C);
@@ -127 +166 @@
 void glue(test_, OP)(void)
 {
-    int i;
-    for(i = 0; i < 32; i++)
+    int i, n;
+#if defined(__x86_64__)
+    n = 64;
+#else
+    n = 32;
+#endif
+    for(i = 0; i < n; i++)
         exec_op(0x21ad3d34, 0x12345678, i);
-    for(i = 0; i < 32; i++)
-        exec_op(0x813f3421, 0x82345678, i);
+    for(i = 0; i < n; i++)
+        exec_op(0x813f3421, 0x82345679, i);
 }
 

trunk/src/recompiler/tests/test-i386.c

@@ -29 +29 @@
 #include <sys/ucontext.h>
 #include <sys/mman.h>
-#include <asm/vm86.h>
-
+
+#if !defined(__x86_64__)
+#define TEST_VM86
+#define TEST_SEGS
+#endif
+//#define LINUX_VM86_IOPL_FIX
+//#define TEST_P4_FLAGS
+#if defined(__x86_64__)
+#define TEST_SSE
+#define TEST_CMOV  1
+#define TEST_FCOMI 1
+#else
+//#define TEST_SSE
 #define TEST_CMOV  0
 #define TEST_FCOMI 0
-//#define LINUX_VM86_IOPL_FIX
-//#define TEST_P4_FLAGS
+#endif
+
+#if defined(__x86_64__)
+#define FMT64X "%016lx"
+#define FMTLX "%016lx"
+#define X86_64_ONLY(x) x
+#else
+#define FMT64X "%016" PRIx64
+#define FMTLX "%08lx"
+#define X86_64_ONLY(x)
+#endif
+
+#ifdef TEST_VM86
+#include <asm/vm86.h>
+#endif
 
 #define xglue(x, y) x ## y
@@ -48 +72 @@
 #define CC_O    0x0800
 
-#define __init_call     __attribute__ ((unused,__section__ (".initcall.init")))
-
-static void *call_start __init_call = NULL;
+#define __init_call     __attribute__ ((unused,__section__ ("initcall")))
 
 #define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)
+
+#if defined(__x86_64__)
+static inline long i2l(long v)
+{
+    return v | ((v ^ 0xabcd) << 32);
+}
+#else
+static inline long i2l(long v)
+{
+    return v;
+}
+#endif
 
 #define OP add
@@ -157 +191 @@
 
 /* lea test (modrm support) */
-#define TEST_LEA(STR)\
-{\
-    asm("leal " STR ", %0"\
+#define TEST_LEAQ(STR)\
+{\
+    asm("lea " STR ", %0"\
         : "=r" (res)\
         : "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
-    printf("lea %s = %08x\n", STR, res);\
+    printf("lea %s = " FMTLX "\n", STR, res);\
+}
+
+#define TEST_LEA(STR)\
+{\
+    asm("lea " STR ", %0"\
+        : "=r" (res)\
+        : "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
+    printf("lea %s = " FMTLX "\n", STR, res);\
 }
 
@@ -170 +212 @@
         : "=wq" (res)\
         : "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
-    printf("lea %s = %08x\n", STR, res);\
+    printf("lea %s = %08lx\n", STR, res);\
 }
 
@@ -176 +218 @@
 void test_lea(void)
 {
-    int eax, ebx, ecx, edx, esi, edi, res;
-    eax = 0x0001;
-    ebx = 0x0002;
-    ecx = 0x0004;
-    edx = 0x0008;
-    esi = 0x0010;
-    edi = 0x0020;
+    long eax, ebx, ecx, edx, esi, edi, res;
+    eax = i2l(0x0001);
+    ebx = i2l(0x0002);
+    ecx = i2l(0x0004);
+    edx = i2l(0x0008);
+    esi = i2l(0x0010);
+    edi = i2l(0x0020);
 
     TEST_LEA("0x4000");
@@ -238 +280 @@
     TEST_LEA("0x4000(%%esi, %%ecx, 8)");
 
+#if defined(__x86_64__)
+    TEST_LEAQ("0x4000");
+    TEST_LEAQ("0x4000(%%rip)");
+
+    TEST_LEAQ("(%%rax)");
+    TEST_LEAQ("(%%rbx)");
+    TEST_LEAQ("(%%rcx)");
+    TEST_LEAQ("(%%rdx)");
+    TEST_LEAQ("(%%rsi)");
+    TEST_LEAQ("(%%rdi)");
+
+    TEST_LEAQ("0x40(%%rax)");
+    TEST_LEAQ("0x40(%%rbx)");
+    TEST_LEAQ("0x40(%%rcx)");
+    TEST_LEAQ("0x40(%%rdx)");
+    TEST_LEAQ("0x40(%%rsi)");
+    TEST_LEAQ("0x40(%%rdi)");
+
+    TEST_LEAQ("0x4000(%%rax)");
+    TEST_LEAQ("0x4000(%%rbx)");
+    TEST_LEAQ("0x4000(%%rcx)");
+    TEST_LEAQ("0x4000(%%rdx)");
+    TEST_LEAQ("0x4000(%%rsi)");
+    TEST_LEAQ("0x4000(%%rdi)");
+
+    TEST_LEAQ("(%%rax, %%rcx)");
+    TEST_LEAQ("(%%rbx, %%rdx)");
+    TEST_LEAQ("(%%rcx, %%rcx)");
+    TEST_LEAQ("(%%rdx, %%rcx)");
+    TEST_LEAQ("(%%rsi, %%rcx)");
+    TEST_LEAQ("(%%rdi, %%rcx)");
+
+    TEST_LEAQ("0x40(%%rax, %%rcx)");
+    TEST_LEAQ("0x4000(%%rbx, %%rdx)");
+
+    TEST_LEAQ("(%%rcx, %%rcx, 2)");
+    TEST_LEAQ("(%%rdx, %%rcx, 4)");
+    TEST_LEAQ("(%%rsi, %%rcx, 8)");
+
+    TEST_LEAQ("(,%%rax, 2)");
+    TEST_LEAQ("(,%%rbx, 4)");
+    TEST_LEAQ("(,%%rcx, 8)");
+
+    TEST_LEAQ("0x40(,%%rax, 2)");
+    TEST_LEAQ("0x40(,%%rbx, 4)");
+    TEST_LEAQ("0x40(,%%rcx, 8)");
+
+
+    TEST_LEAQ("-10(%%rcx, %%rcx, 2)");
+    TEST_LEAQ("-10(%%rdx, %%rcx, 4)");
+    TEST_LEAQ("-10(%%rsi, %%rcx, 8)");
+
+    TEST_LEAQ("0x4000(%%rcx, %%rcx, 2)");
+    TEST_LEAQ("0x4000(%%rdx, %%rcx, 4)");
+    TEST_LEAQ("0x4000(%%rsi, %%rcx, 8)");
+#else
     /* limited 16 bit addressing test */
     TEST_LEA16("0x4000");
@@ -254 +352 @@
     TEST_LEA16("0x4000(%%bx,%%si)");
     TEST_LEA16("0x4000(%%bx,%%di)");
+#endif
 }
 
@@ -275 +374 @@
     printf("%-10s %d\n", "set" JCC, res);\
  if (TEST_CMOV) {\
-    asm("movl $0x12345678, %0\n\t"\
-        "cmpl %2, %1\n\t"\
-        "cmov" JCC "l %3, %0\n\t"\
+    long val = i2l(1);\
+    long res = i2l(0x12345678);\
+X86_64_ONLY(\
+    asm("cmpl %2, %1\n\t"\
+        "cmov" JCC "q %3, %0\n\t"\
         : "=r" (res)\
-        : "r" (v1), "r" (v2), "m" (1));\
-        printf("%-10s R=0x%08x\n", "cmov" JCC "l", res);\
-    asm("movl $0x12345678, %0\n\t"\
-        "cmpl %2, %1\n\t"\
+        : "r" (v1), "r" (v2), "m" (val), "0" (res));\
+        printf("%-10s R=" FMTLX "\n", "cmov" JCC "q", res);)\
+    asm("cmpl %2, %1\n\t"\
+        "cmov" JCC "l %k3, %k0\n\t"\
+        : "=r" (res)\
+        : "r" (v1), "r" (v2), "m" (val), "0" (res));\
+        printf("%-10s R=" FMTLX "\n", "cmov" JCC "l", res);\
+    asm("cmpl %2, %1\n\t"\
         "cmov" JCC "w %w3, %w0\n\t"\
         : "=r" (res)\
-        : "r" (v1), "r" (v2), "r" (1));\
-        printf("%-10s R=0x%08x\n", "cmov" JCC "w", res);\
+        : "r" (v1), "r" (v2), "r" (1), "0" (res));\
+        printf("%-10s R=" FMTLX "\n", "cmov" JCC "w", res);\
  } \
 }
@@ -366 +471 @@
 #include "test-i386-muldiv.h"
 
-void test_imulw2(int op0, int op1) 
-{
-    int res, s1, s0, flags;
+void test_imulw2(long op0, long op1) 
+{
+    long res, s1, s0, flags;
     s0 = op0;
     s1 = op1;
     res = s0;
     flags = 0;
-    asm ("push %4\n\t"
+    asm volatile ("push %4\n\t"
          "popf\n\t"
          "imulw %w2, %w0\n\t" 
          "pushf\n\t"
-         "popl %1\n\t"
+         "pop %1\n\t"
          : "=q" (res), "=g" (flags)
          : "q" (s1), "0" (res), "1" (flags));
-    printf("%-10s A=%08x B=%08x R=%08x CC=%04x\n",
+    printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
            "imulw", s0, s1, res, flags & CC_MASK);
 }
 
-void test_imull2(int op0, int op1) 
-{
-    int res, s1, s0, flags;
+void test_imull2(long op0, long op1) 
+{
+    long res, s1, s0, flags;
     s0 = op0;
     s1 = op1;
     res = s0;
     flags = 0;
-    asm ("push %4\n\t"
+    asm volatile ("push %4\n\t"
          "popf\n\t"
-         "imull %2, %0\n\t" 
+         "imull %k2, %k0\n\t" 
          "pushf\n\t"
-         "popl %1\n\t"
+         "pop %1\n\t"
          : "=q" (res), "=g" (flags)
          : "q" (s1), "0" (res), "1" (flags));
-    printf("%-10s A=%08x B=%08x R=%08x CC=%04x\n",
+    printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
            "imull", s0, s1, res, flags & CC_MASK);
 }
 
-#define TEST_IMUL_IM(size, size1, op0, op1)\
-{\
-    int res, flags;\
+#if defined(__x86_64__)
+void test_imulq2(long op0, long op1) 
+{
+    long res, s1, s0, flags;
+    s0 = op0;
+    s1 = op1;
+    res = s0;
+    flags = 0;
+    asm volatile ("push %4\n\t"
+         "popf\n\t"
+         "imulq %2, %0\n\t" 
+         "pushf\n\t"
+         "pop %1\n\t"
+         : "=q" (res), "=g" (flags)
+         : "q" (s1), "0" (res), "1" (flags));
+    printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
+           "imulq", s0, s1, res, flags & CC_MASK);
+}
+#endif
+
+#define TEST_IMUL_IM(size, rsize, op0, op1)\
+{\
+    long res, flags, s1;\
     flags = 0;\
     res = 0;\
-    asm ("push %3\n\t"\
+    s1 = op1;\
+    asm volatile ("push %3\n\t"\
          "popf\n\t"\
-         "imul" size " $" #op0 ", %" size1 "2, %" size1 "0\n\t" \
+         "imul" size " $" #op0 ", %" rsize "2, %" rsize "0\n\t" \
          "pushf\n\t"\
-         "popl %1\n\t"\
+         "pop %1\n\t"\
          : "=r" (res), "=g" (flags)\
-         : "r" (op1), "1" (flags), "0" (res));\
-    printf("%-10s A=%08x B=%08x R=%08x CC=%04x\n",\
-           "imul" size, op0, op1, res, flags & CC_MASK);\
+         : "r" (s1), "1" (flags), "0" (res));\
+    printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",\
+           "imul" size " im", (long)op0, (long)op1, res, flags & CC_MASK);\
 }
 
@@ -475 +601 @@
     TEST_IMUL_IM("w", "w", 0x7fff, 0x1000);
 
-    TEST_IMUL_IM("l", "", 45, 0x1234);
-    TEST_IMUL_IM("l", "", -45, 23);
-    TEST_IMUL_IM("l", "", 0x8000, 0x80000000);
-    TEST_IMUL_IM("l", "", 0x7fff, 0x1000);
+    TEST_IMUL_IM("l", "k", 45, 0x1234);
+    TEST_IMUL_IM("l", "k", -45, 23);
+    TEST_IMUL_IM("l", "k", 0x8000, 0x80000000);
+    TEST_IMUL_IM("l", "k", 0x7fff, 0x1000);
 
     test_idivb(0x12341678, 0x127e);
@@ -507 +633 @@
     test_divl(0, 0x80000000, -1);
     test_divl(0x12343, 0x12345678, 0x81234567);
+
+#if defined(__x86_64__)
+    test_imulq(0, 0x1234001d1234001d, 45);
+    test_imulq(0, 23, -45);
+    test_imulq(0, 0x8000000000000000, 0x8000000000000000);
+    test_imulq(0, 0x100000000, 0x100000000);
+
+    test_mulq(0, 0x1234001d1234001d, 45);
+    test_mulq(0, 23, -45);
+    test_mulq(0, 0x8000000000000000, 0x8000000000000000);
+    test_mulq(0, 0x100000000, 0x100000000);
+
+    test_imulq2(0x1234001d1234001d, 45);
+    test_imulq2(23, -45);
+    test_imulq2(0x8000000000000000, 0x8000000000000000);
+    test_imulq2(0x100000000, 0x100000000);
+
+    TEST_IMUL_IM("q", "", 45, 0x12341234);
+    TEST_IMUL_IM("q", "", -45, 23);
+    TEST_IMUL_IM("q", "", 0x8000, 0x8000000000000000);
+    TEST_IMUL_IM("q", "", 0x7fff, 0x10000000);
+
+    test_idivq(0, 0x12345678abcdef, 12347);
+    test_idivq(0, -233223, -45);
+    test_idivq(0, 0x8000000000000000, -1);
+    test_idivq(0x12343, 0x12345678, 0x81234567);
+
+    test_divq(0, 0x12345678abcdef, 12347);
+    test_divq(0, -233223, -45);
+    test_divq(0, 0x8000000000000000, -1);
+    test_divq(0x12343, 0x12345678, 0x81234567);
+#endif
 }
 
 #define TEST_BSX(op, size, op0)\
 {\
-    int res, val, resz;\
+    long res, val, resz;\
     val = op0;\
-    asm("xorl %1, %1\n"\
-        "movl $0x12345678, %0\n"\
+    asm("xor %1, %1\n"\
+        "mov $0x12345678, %0\n"\
         #op " %" size "2, %" size "0 ; setz %b1" \
         : "=r" (res), "=q" (resz)\
         : "g" (val));\
-    printf("%-10s A=%08x R=%08x %d\n", #op, val, res, resz);\
+    printf("%-10s A=" FMTLX " R=" FMTLX " %ld\n", #op, val, res, resz);\
 }
 
@@ -525 +683 @@
     TEST_BSX(bsrw, "w", 0);
     TEST_BSX(bsrw, "w", 0x12340128);
-    TEST_BSX(bsrl, "", 0);
-    TEST_BSX(bsrl, "", 0x00340128);
     TEST_BSX(bsfw, "w", 0);
     TEST_BSX(bsfw, "w", 0x12340128);
-    TEST_BSX(bsfl, "", 0);
-    TEST_BSX(bsfl, "", 0x00340128);
+    TEST_BSX(bsrl, "k", 0);
+    TEST_BSX(bsrl, "k", 0x00340128);
+    TEST_BSX(bsfl, "k", 0);
+    TEST_BSX(bsfl, "k", 0x00340128);
+#if defined(__x86_64__)
+    TEST_BSX(bsrq, "", 0);
+    TEST_BSX(bsrq, "", 0x003401281234);
+    TEST_BSX(bsfq, "", 0);
+    TEST_BSX(bsfq, "", 0x003401281234);
+#endif
 }
 
 /**********************************************/
+
+union float64u {
+    double d;
+    uint64_t l;
+};
+
+union float64u q_nan = { .l = 0xFFF8000000000000 };
+union float64u s_nan = { .l = 0xFFF0000000000000 };
 
 void test_fops(double a, double b)
@@ -556 +728 @@
 }
 
+void fpu_clear_exceptions(void)
+{
+    struct __attribute__((packed)) {
+        uint16_t fpuc;
+        uint16_t dummy1;
+        uint16_t fpus;
+        uint16_t dummy2;
+        uint16_t fptag;
+        uint16_t dummy3;
+        uint32_t ignored[4];
+        long double fpregs[8];
+    } float_env32;
+    
+    asm volatile ("fnstenv %0\n" : : "m" (float_env32));
+    float_env32.fpus &= ~0x7f;
+    asm volatile ("fldenv %0\n" : : "m" (float_env32));
+}
+
+/* XXX: display exception bits when supported */
+#define FPUS_EMASK 0x0000
+//#define FPUS_EMASK 0x007f
+
 void test_fcmp(double a, double b)
 {
-    printf("(%f<%f)=%d\n",
-           a, b, a < b);
-    printf("(%f<=%f)=%d\n",
-           a, b, a <= b);
-    printf("(%f==%f)=%d\n",
-           a, b, a == b);
-    printf("(%f>%f)=%d\n",
-           a, b, a > b);
-    printf("(%f<=%f)=%d\n",
-           a, b, a >= b);
+    long eflags, fpus;
+
+    fpu_clear_exceptions();
+    asm("fcom %2\n"
+        "fstsw %%ax\n"
+        : "=a" (fpus)
+        : "t" (a), "u" (b));
+    printf("fcom(%f %f)=%04lx \n", 
+           a, b, fpus & (0x4500 | FPUS_EMASK));
+    fpu_clear_exceptions();
+    asm("fucom %2\n"
+        "fstsw %%ax\n"
+        : "=a" (fpus)
+        : "t" (a), "u" (b));
+    printf("fucom(%f %f)=%04lx\n", 
+           a, b, fpus & (0x4500 | FPUS_EMASK));
     if (TEST_FCOMI) {
-        unsigned int eflags;
         /* test f(u)comi instruction */
-        asm("fcomi %2, %1\n"
+        fpu_clear_exceptions();
+        asm("fcomi %3, %2\n"
+            "fstsw %%ax\n"
             "pushf\n"
             "pop %0\n"
-            : "=r" (eflags)
+            : "=r" (eflags), "=a" (fpus)
             : "t" (a), "u" (b));
-        printf("fcomi(%f %f)=%08x\n", a, b, eflags & (CC_Z | CC_P | CC_C));
-    }
+        printf("fcomi(%f %f)=%04lx %02lx\n", 
+               a, b, fpus & FPUS_EMASK, eflags & (CC_Z | CC_P | CC_C));
+        fpu_clear_exceptions();
+        asm("fucomi %3, %2\n"
+            "fstsw %%ax\n"
+            "pushf\n"
+            "pop %0\n"
+            : "=r" (eflags), "=a" (fpus)
+            : "t" (a), "u" (b));
+        printf("fucomi(%f %f)=%04lx %02lx\n", 
+               a, b, fpus & FPUS_EMASK, eflags & (CC_Z | CC_P | CC_C));
+    }
+    fpu_clear_exceptions();
+    asm volatile("fxam\n"
+                 "fstsw %%ax\n"
+                 : "=a" (fpus)
+                 : "t" (a));
+    printf("fxam(%f)=%04lx\n", a, fpus & 0x4700);
+    fpu_clear_exceptions();
 }
 
@@ -595 +813 @@
     printf("(float)%f = %f\n", a, fa);
     printf("(long double)%f = %Lf\n", a, la);
-    printf("a=%016Lx\n", *(long long *)&a);
-    printf("la=%016Lx %04x\n", *(long long *)&la, 
+    printf("a=" FMT64X "\n", *(uint64_t *)&a);
+    printf("la=" FMT64X " %04x\n", *(uint64_t *)&la, 
            *(unsigned short *)((char *)(&la) + 8));
 
@@ -610 +828 @@
         printf("(short)a = %d\n", wa);
         printf("(int)a = %d\n", ia);
-        printf("(int64_t)a = %Ld\n", lla);
+        printf("(int64_t)a = " FMT64X "\n", lla);
         printf("rint(a) = %f\n", ra);
     }
@@ -647 +865 @@
     for(i=0;i<5;i++)\
         asm volatile ("fldl %0" : : "m" (dtab[i]));\
-    asm(save " %0\n" : : "m" (*(env)));\
-    asm(restore " %0\n": : "m" (*(env)));\
+    asm volatile (save " %0\n" : : "m" (*(env)));\
+    asm volatile (restore " %0\n": : "m" (*(env)));\
     for(i=0;i<5;i++)\
         asm volatile ("fstpl %0" : "=m" (rtab[i]));\
@@ -708 +926 @@
         : "=t" (res)\
         : "0" (a), "u" (b), "g" (eflags));\
-    printf("fcmov%s eflags=0x%04x-> %f\n", \
-           CC, eflags, res);\
+    printf("fcmov%s eflags=0x%04lx-> %f\n", \
+           CC, (long)eflags, res);\
 }
 
@@ -715 +933 @@
 {
     double a, b;
-    int eflags, i;
+    long eflags, i;
 
     a = 1.0;
@@ -745 +963 @@
     test_fcmp(2, 2);
     test_fcmp(2, 3);
+    test_fcmp(2, q_nan.d);
+    test_fcmp(q_nan.d, -1);
+    test_fcmp(-1.0/0.0, -1);
+    test_fcmp(1.0/0.0, -1);
     test_fcvt(0.5);
     test_fcvt(-0.5);
@@ -751 +973 @@
     test_fcvt(32768);
     test_fcvt(-1e20);
+    test_fcvt(-1.0/0.0);
+    test_fcvt(1.0/0.0);
+    test_fcvt(q_nan.d);
     test_fconst();
     test_fbcd(1234567890123456);
@@ -761 +986 @@
 
 /**********************************************/
+#if !defined(__x86_64__)
 
 #define TEST_BCD(op, op0, cc_in, cc_mask)\
@@ -771 +997 @@
          #op "\n\t"\
          "pushf\n\t"\
-         "popl %1\n\t"\
+         "pop %1\n\t"\
         : "=a" (res), "=g" (flags)\
         : "0" (res), "1" (flags));\
@@ -829 +1055 @@
     TEST_BCD(aad, 0x12340407, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A));
 }
+#endif
 
 #define TEST_XCHG(op, size, opconst)\
 {\
-    int op0, op1;\
-    op0 = 0x12345678;\
-    op1 = 0xfbca7654;\
+    long op0, op1;\
+    op0 = i2l(0x12345678);\
+    op1 = i2l(0xfbca7654);\
     asm(#op " %" size "0, %" size "1" \
         : "=q" (op0), opconst (op1) \
         : "0" (op0), "1" (op1));\
-    printf("%-10s A=%08x B=%08x\n",\
+    printf("%-10s A=" FMTLX " B=" FMTLX "\n",\
            #op, op0, op1);\
 }
@@ -844 +1071 @@
 #define TEST_CMPXCHG(op, size, opconst, eax)\
 {\
-    int op0, op1;\
-    op0 = 0x12345678;\
-    op1 = 0xfbca7654;\
+    long op0, op1, op2;\
+    op0 = i2l(0x12345678);\
+    op1 = i2l(0xfbca7654);\
+    op2 = i2l(eax);\
     asm(#op " %" size "0, %" size "1" \
         : "=q" (op0), opconst (op1) \
-        : "0" (op0), "1" (op1), "a" (eax));\
-    printf("%-10s EAX=%08x A=%08x C=%08x\n",\
-           #op, eax, op0, op1);\
+        : "0" (op0), "1" (op1), "a" (op2));\
+    printf("%-10s EAX=" FMTLX " A=" FMTLX " C=" FMTLX "\n",\
+           #op, op2, op0, op1);\
 }
 
 void test_xchg(void)
 {
-    TEST_XCHG(xchgl, "", "=q");
+#if defined(__x86_64__)
+    TEST_XCHG(xchgq, "", "=q");
+#endif
+    TEST_XCHG(xchgl, "k", "=q");
     TEST_XCHG(xchgw, "w", "=q");
     TEST_XCHG(xchgb, "b", "=q");
 
-    TEST_XCHG(xchgl, "", "=m");
+#if defined(__x86_64__)
+    TEST_XCHG(xchgq, "", "=m");
+#endif
+    TEST_XCHG(xchgl, "k", "=m");
     TEST_XCHG(xchgw, "w", "=m");
     TEST_XCHG(xchgb, "b", "=m");
 
-    TEST_XCHG(xaddl, "", "=q");
+#if defined(__x86_64__)
+    TEST_XCHG(xaddq, "", "=q");
+#endif
+    TEST_XCHG(xaddl, "k", "=q");
     TEST_XCHG(xaddw, "w", "=q");
     TEST_XCHG(xaddb, "b", "=q");
@@ -875 +1112 @@
     }
 
-    TEST_XCHG(xaddl, "", "=m");
+#if defined(__x86_64__)
+    TEST_XCHG(xaddq, "", "=m");
+#endif
+    TEST_XCHG(xaddl, "k", "=m");
     TEST_XCHG(xaddw, "w", "=m");
     TEST_XCHG(xaddb, "b", "=m");
 
-    TEST_CMPXCHG(cmpxchgl, "", "=q", 0xfbca7654);
+#if defined(__x86_64__)
+    TEST_CMPXCHG(cmpxchgq, "", "=q", 0xfbca7654);
+#endif
+    TEST_CMPXCHG(cmpxchgl, "k", "=q", 0xfbca7654);
     TEST_CMPXCHG(cmpxchgw, "w", "=q", 0xfbca7654);
     TEST_CMPXCHG(cmpxchgb, "b", "=q", 0xfbca7654);
 
-    TEST_CMPXCHG(cmpxchgl, "", "=q", 0xfffefdfc);
+#if defined(__x86_64__)
+    TEST_CMPXCHG(cmpxchgq, "", "=q", 0xfffefdfc);
+#endif
+    TEST_CMPXCHG(cmpxchgl, "k", "=q", 0xfffefdfc);
     TEST_CMPXCHG(cmpxchgw, "w", "=q", 0xfffefdfc);
     TEST_CMPXCHG(cmpxchgb, "b", "=q", 0xfffefdfc);
 
-    TEST_CMPXCHG(cmpxchgl, "", "=m", 0xfbca7654);
+#if defined(__x86_64__)
+    TEST_CMPXCHG(cmpxchgq, "", "=m", 0xfbca7654);
+#endif
+    TEST_CMPXCHG(cmpxchgl, "k", "=m", 0xfbca7654);
     TEST_CMPXCHG(cmpxchgw, "w", "=m", 0xfbca7654);
     TEST_CMPXCHG(cmpxchgb, "b", "=m", 0xfbca7654);
 
-    TEST_CMPXCHG(cmpxchgl, "", "=m", 0xfffefdfc);
+#if defined(__x86_64__)
+    TEST_CMPXCHG(cmpxchgq, "", "=m", 0xfffefdfc);
+#endif
+    TEST_CMPXCHG(cmpxchgl, "k", "=m", 0xfffefdfc);
     TEST_CMPXCHG(cmpxchgw, "w", "=m", 0xfffefdfc);
     TEST_CMPXCHG(cmpxchgb, "b", "=m", 0xfffefdfc);
@@ -897 +1149 @@
     {
         uint64_t op0, op1, op2;
-        int i, eflags;
+        long i, eflags;
 
         for(i = 0; i < 2; i++) {
@@ -908 +1160 @@
             asm("cmpxchg8b %1\n" 
                 "pushf\n"
-                "popl %2\n"
+                "pop %2\n"
                 : "=A" (op0), "=m" (op1), "=g" (eflags)
                 : "0" (op0), "m" (op1), "b" ((int)op2), "c" ((int)(op2 >> 32)));
-            printf("cmpxchg8b: op0=%016llx op1=%016llx CC=%02x\n", 
+            printf("cmpxchg8b: op0=" FMT64X " op1=" FMT64X " CC=%02lx\n", 
                     op0, op1, eflags & CC_Z);
         }
@@ -917 +1169 @@
 }
 
+#ifdef TEST_SEGS
 /**********************************************/
 /* segmentation tests */
@@ -930 +1183 @@
 #endif
 
+#define MK_SEL(n) (((n) << 3) | 7)
+
 uint8_t seg_data1[4096];
 uint8_t seg_data2[4096];
-
-#define MK_SEL(n) (((n) << 3) | 7)
 
 #define TEST_LR(op, size, seg, mask)\
@@ -1078 +1331 @@
     printf("func3() = 0x%08x\n", res);
 }
-
-extern char func_lret32;
-extern char func_iret32;
+#endif
+
+#if defined(__x86_64__)
+asm(".globl func_lret\n"
+    "func_lret:\n"
+    "movl $0x87654641, %eax\n"
+    "lretq\n");
+#else
+asm(".globl func_lret\n"
+    "func_lret:\n"
+    "movl $0x87654321, %eax\n"
+    "lret\n"
+
+    ".globl func_iret\n"
+    "func_iret:\n"
+    "movl $0xabcd4321, %eax\n"
+    "iret\n");
+#endif
+
+extern char func_lret;
+extern char func_iret;
 
 void test_misc(void)
 {
     char table[256];
-    int res, i;
+    long res, i;
 
     for(i=0;i<256;i++) table[i] = 256 - i;
     res = 0x12345678;
     asm ("xlat" : "=a" (res) : "b" (table), "0" (res));
-    printf("xlat: EAX=%08x\n", res);
-
-    asm volatile ("pushl %%cs ; call %1" 
+    printf("xlat: EAX=" FMTLX "\n", res);
+
+#if defined(__x86_64__)
+    {
+        static struct __attribute__((packed)) {
+            uint32_t offset;
+            uint16_t seg;
+        } desc;
+        long cs_sel;
+
+        asm volatile ("mov %%cs, %0" : "=r" (cs_sel));
+
+        asm volatile ("push %1\n"
+                      "call func_lret\n" 
+                      : "=a" (res)
+                      : "r" (cs_sel) : "memory", "cc");
+        printf("func_lret=" FMTLX "\n", res);
+
+        /* NOTE: we assume that &func_lret < 4GB */
+        desc.offset = (long)&func_lret;
+        desc.seg = cs_sel;
+        
+        asm volatile ("xor %%rax, %%rax\n"
+                      "rex64 lcall %1\n"
+                      : "=a" (res)
+                      : "m" (desc) 
+                      : "memory", "cc");
+        printf("func_lret2=" FMTLX "\n", res);
+
+        asm volatile ("push %2\n"
+                      "mov $ 1f, %%rax\n"
+                      "push %%rax\n"
+                      "ljmp %1\n"
+                      "1:\n"
+                      : "=a" (res)
+                      : "m" (desc), "b" (cs_sel)
+                      : "memory", "cc");
+        printf("func_lret3=" FMTLX "\n", res);
+    }
+#else
+    asm volatile ("push %%cs ; call %1" 
                   : "=a" (res)
-                  : "m" (func_lret32): "memory", "cc");
-    printf("func_lret32=%x\n", res);
-
-    asm volatile ("pushfl ; pushl %%cs ; call %1" 
+                  : "m" (func_lret): "memory", "cc");
+    printf("func_lret=" FMTLX "\n", res);
+
+    asm volatile ("pushf ; push %%cs ; call %1" 
                   : "=a" (res)
-                  : "m" (func_iret32): "memory", "cc");
-    printf("func_iret32=%x\n", res);
-
+                  : "m" (func_iret): "memory", "cc");
+    printf("func_iret=" FMTLX "\n", res);
+#endif
+
+#if defined(__x86_64__)
+    /* specific popl test */
+    asm volatile ("push $12345432 ; push $0x9abcdef ; pop (%%rsp) ; pop %0"
+                  : "=g" (res));
+    printf("popl esp=" FMTLX "\n", res);
+#else
     /* specific popl test */
     asm volatile ("pushl $12345432 ; pushl $0x9abcdef ; popl (%%esp) ; popl %0"
                   : "=g" (res));
-    printf("popl esp=%x\n", res);
+    printf("popl esp=" FMTLX "\n", res);
 
     /* specific popw test */
     asm volatile ("pushl $12345432 ; pushl $0x9abcdef ; popw (%%esp) ; addl $2, %%esp ; popl %0"
                   : "=g" (res));
-    printf("popw esp=%x\n", res);
+    printf("popw esp=" FMTLX "\n", res);
+#endif
 }
 
@@ -1117 +1434 @@
 #define TEST_STRING1(OP, size, DF, REP)\
 {\
-    int esi, edi, eax, ecx, eflags;\
+    long esi, edi, eax, ecx, eflags;\
 \
     esi = (long)(str_buffer + sizeof(str_buffer) / 2);\
     edi = (long)(str_buffer + sizeof(str_buffer) / 2) + 16;\
-    eax = 0x12345678;\
+    eax = i2l(0x12345678);\
     ecx = 17;\
 \
-    asm volatile ("pushl $0\n\t"\
+    asm volatile ("push $0\n\t"\
                   "popf\n\t"\
                   DF "\n\t"\
@@ -1130 +1447 @@
                   "cld\n\t"\
                   "pushf\n\t"\
-                  "popl %4\n\t"\
+                  "pop %4\n\t"\
                   : "=S" (esi), "=D" (edi), "=a" (eax), "=c" (ecx), "=g" (eflags)\
                   : "0" (esi), "1" (edi), "2" (eax), "3" (ecx));\
-    printf("%-10s ESI=%08x EDI=%08x EAX=%08x ECX=%08x EFL=%04x\n",\
+    printf("%-10s ESI=" FMTLX " EDI=" FMTLX " EAX=" FMTLX " ECX=" FMTLX " EFL=%04x\n",\
            REP #OP size, esi, edi, eax, ecx,\
-           eflags & (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A));\
+           (int)(eflags & (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)));\
 }
 
@@ -1142 +1459 @@
     TEST_STRING1(OP, "w", "", REP);\
     TEST_STRING1(OP, "l", "", REP);\
+    X86_64_ONLY(TEST_STRING1(OP, "q", "", REP));\
     TEST_STRING1(OP, "b", "std", REP);\
     TEST_STRING1(OP, "w", "std", REP);\
-    TEST_STRING1(OP, "l", "std", REP)
+    TEST_STRING1(OP, "l", "std", REP);\
+    X86_64_ONLY(TEST_STRING1(OP, "q", "std", REP))
 
 void test_string(void)
@@ -1168 +1487 @@
 }
 
+#ifdef TEST_VM86
 /* VM86 test */
 
@@ -1298 +1618 @@
     munmap(vm86_mem, 0x110000);
 }
+#endif
 
 /* exception tests */
-#ifndef REG_EAX
+#if defined(__i386__) && !defined(REG_EAX)
 #define REG_EAX EAX
 #define REG_EBX EBX
@@ -1315 +1636 @@
 #endif
 
+#if defined(__x86_64__)
+#define REG_EIP REG_RIP
+#endif
+
 jmp_buf jmp_env;
 int v1;
@@ -1329 +1654 @@
     printf("\n");
 
-    printf("trapno=0x%02x err=0x%08x",
-           uc->uc_mcontext.gregs[REG_TRAPNO],
-           uc->uc_mcontext.gregs[REG_ERR]);
-    printf(" EIP=0x%08x", uc->uc_mcontext.gregs[REG_EIP]);
+    printf("trapno=" FMTLX " err=" FMTLX,
+           (long)uc->uc_mcontext.gregs[REG_TRAPNO],
+           (long)uc->uc_mcontext.gregs[REG_ERR]);
+    printf(" EIP=" FMTLX, (long)uc->uc_mcontext.gregs[REG_EIP]);
     printf("\n");
     longjmp(jmp_env, 1);
@@ -1339 +1664 @@
 void test_exceptions(void)
 {
-    struct modify_ldt_ldt_s ldt;
     struct sigaction act;
     volatile int val;
@@ -1345 +1669 @@
     act.sa_sigaction = sig_handler;
     sigemptyset(&act.sa_mask);
-    act.sa_flags = SA_SIGINFO;
+    act.sa_flags = SA_SIGINFO | SA_NODEFER;
     sigaction(SIGFPE, &act, NULL);
     sigaction(SIGILL, &act, NULL);
@@ -1360 +1684 @@
     }
 
+#if !defined(__x86_64__)
     printf("BOUND exception:\n");
     if (setjmp(jmp_env) == 0) {
@@ -1367 +1692 @@
         asm volatile ("bound %0, %1" : : "r" (11), "m" (tab[0]));
     }
-
+#endif
+
+#ifdef TEST_SEGS
     printf("segment exceptions:\n");
     if (setjmp(jmp_env) == 0) {
@@ -1380 +1707 @@
     }
 
-    ldt.entry_number = 1;
-    ldt.base_addr = (unsigned long)&seg_data1;
-    ldt.limit = (sizeof(seg_data1) + 0xfff) >> 12;
-    ldt.seg_32bit = 1;
-    ldt.contents = MODIFY_LDT_CONTENTS_DATA;
-    ldt.read_exec_only = 0;
-    ldt.limit_in_pages = 1;
-    ldt.seg_not_present = 1;
-    ldt.useable = 1;
-    modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
-
-    if (setjmp(jmp_env) == 0) {
-        /* segment not present */
-        asm volatile ("movl %0, %%fs" : : "r" (MK_SEL(1)));
-    }
+    {
+        struct modify_ldt_ldt_s ldt;
+        ldt.entry_number = 1;
+        ldt.base_addr = (unsigned long)&seg_data1;
+        ldt.limit = (sizeof(seg_data1) + 0xfff) >> 12;
+        ldt.seg_32bit = 1;
+        ldt.contents = MODIFY_LDT_CONTENTS_DATA;
+        ldt.read_exec_only = 0;
+        ldt.limit_in_pages = 1;
+        ldt.seg_not_present = 1;
+        ldt.useable = 1;
+        modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
+        
+        if (setjmp(jmp_env) == 0) {
+            /* segment not present */
+            asm volatile ("movl %0, %%fs" : : "r" (MK_SEL(1)));
+        }
+    }
+#endif
 
     /* test SEGV reporting */
@@ -1458 +1789 @@
     }
 
+#if !defined(__x86_64__)
     printf("INTO exception:\n");
     if (setjmp(jmp_env) == 0) {
@@ -1463 +1795 @@
         asm volatile ("addl $1, %0 ; into" : : "r" (0x7fffffff));
     }
+#endif
 
     printf("OUTB exception:\n");
@@ -1501 +1834 @@
 }
 
+#if !defined(__x86_64__)
 /* specific precise single step test */
 void sig_trap_handler(int sig, siginfo_t *info, void *puc)
 {
     struct ucontext *uc = puc;
-    printf("EIP=0x%08x\n", uc->uc_mcontext.gregs[REG_EIP]);
+    printf("EIP=" FMTLX "\n", (long)uc->uc_mcontext.gregs[REG_EIP]);
 }
 
@@ -1626 +1960 @@
     }
 }
+#endif
+
+long enter_stack[4096];
+
+#if defined(__x86_64__)
+#define RSP "%%rsp"
+#define RBP "%%rbp"
+#else
+#define RSP "%%esp"
+#define RBP "%%ebp"
+#endif
+
+#define TEST_ENTER(size, stack_type, level)\
+{\
+    long esp_save, esp_val, ebp_val, ebp_save, i;\
+    stack_type *ptr, *stack_end, *stack_ptr;\
+    memset(enter_stack, 0, sizeof(enter_stack));\
+    stack_end = stack_ptr = (stack_type *)(enter_stack + 4096);\
+    ebp_val = (long)stack_ptr;\
+    for(i=1;i<=32;i++)\
+       *--stack_ptr = i;\
+    esp_val = (long)stack_ptr;\
+    asm("mov " RSP ", %[esp_save]\n"\
+        "mov " RBP ", %[ebp_save]\n"\
+        "mov %[esp_val], " RSP "\n"\
+        "mov %[ebp_val], " RBP "\n"\
+        "enter" size " $8, $" #level "\n"\
+        "mov " RSP ", %[esp_val]\n"\
+        "mov " RBP ", %[ebp_val]\n"\
+        "mov %[esp_save], " RSP "\n"\
+        "mov %[ebp_save], " RBP "\n"\
+        : [esp_save] "=r" (esp_save),\
+        [ebp_save] "=r" (ebp_save),\
+        [esp_val] "=r" (esp_val),\
+        [ebp_val] "=r" (ebp_val)\
+        :  "[esp_val]" (esp_val),\
+        "[ebp_val]" (ebp_val));\
+    printf("level=%d:\n", level);\
+    printf("esp_val=" FMTLX "\n", esp_val - (long)stack_end);\
+    printf("ebp_val=" FMTLX "\n", ebp_val - (long)stack_end);\
+    for(ptr = (stack_type *)esp_val; ptr < stack_end; ptr++)\
+        printf(FMTLX "\n", (long)ptr[0]);\
+}
+
+static void test_enter(void)
+{
+#if defined(__x86_64__)
+    TEST_ENTER("q", uint64_t, 0);
+    TEST_ENTER("q", uint64_t, 1);
+    TEST_ENTER("q", uint64_t, 2);
+    TEST_ENTER("q", uint64_t, 31);
+#else
+    TEST_ENTER("l", uint32_t, 0);
+    TEST_ENTER("l", uint32_t, 1);
+    TEST_ENTER("l", uint32_t, 2);
+    TEST_ENTER("l", uint32_t, 31);
+#endif
+
+    TEST_ENTER("w", uint16_t, 0);
+    TEST_ENTER("w", uint16_t, 1);
+    TEST_ENTER("w", uint16_t, 2);
+    TEST_ENTER("w", uint16_t, 31);
+}
+
+#ifdef TEST_SSE
+
+typedef int __m64 __attribute__ ((__mode__ (__V2SI__)));
+typedef int __m128 __attribute__ ((__mode__(__V4SF__)));
+
+typedef union {
+    double d[2];
+    float s[4];
+    uint32_t l[4];
+    uint64_t q[2];
+    __m128 dq;
+} XMMReg;
+
+static uint64_t __attribute__((aligned(16))) test_values[4][2] = {
+    { 0x456723c698694873, 0xdc515cff944a58ec },
+    { 0x1f297ccd58bad7ab, 0x41f21efba9e3e146 },
+    { 0x007c62c2085427f8, 0x231be9e8cde7438d },
+    { 0x0f76255a085427f8, 0xc233e9e8c4c9439a },
+};
+
+#define SSE_OP(op)\
+{\
+    asm volatile (#op " %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
+    printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
+           #op,\
+           a.q[1], a.q[0],\
+           b.q[1], b.q[0],\
+           r.q[1], r.q[0]);\
+}
+
+#define SSE_OP2(op)\
+{\
+    int i;\
+    for(i=0;i<2;i++) {\
+    a.q[0] = test_values[2*i][0];\
+    a.q[1] = test_values[2*i][1];\
+    b.q[0] = test_values[2*i+1][0];\
+    b.q[1] = test_values[2*i+1][1];\
+    SSE_OP(op);\
+    }\
+}
+
+#define MMX_OP2(op)\
+{\
+    int i;\
+    for(i=0;i<2;i++) {\
+    a.q[0] = test_values[2*i][0];\
+    b.q[0] = test_values[2*i+1][0];\
+    asm volatile (#op " %2, %0" : "=y" (r.q[0]) : "0" (a.q[0]), "y" (b.q[0]));\
+    printf("%-9s: a=" FMT64X " b=" FMT64X " r=" FMT64X "\n",\
+           #op,\
+           a.q[0],\
+           b.q[0],\
+           r.q[0]);\
+    }\
+    SSE_OP2(op);\
+}
+
+#define SHUF_OP(op, ib)\
+{\
+    a.q[0] = test_values[0][0];\
+    a.q[1] = test_values[0][1];\
+    b.q[0] = test_values[1][0];\
+    b.q[1] = test_values[1][1];\
+    asm volatile (#op " $" #ib ", %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
+    printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
+           #op,\
+           a.q[1], a.q[0],\
+           b.q[1], b.q[0],\
+           ib,\
+           r.q[1], r.q[0]);\
+}
+
+#define PSHUF_OP(op, ib)\
+{\
+    int i;\
+    for(i=0;i<2;i++) {\
+    a.q[0] = test_values[2*i][0];\
+    a.q[1] = test_values[2*i][1];\
+    asm volatile (#op " $" #ib ", %1, %0" : "=x" (r.dq) : "x" (a.dq));\
+    printf("%-9s: a=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
+           #op,\
+           a.q[1], a.q[0],\
+           ib,\
+           r.q[1], r.q[0]);\
+    }\
+}
+
+#define SHIFT_IM(op, ib)\
+{\
+    int i;\
+    for(i=0;i<2;i++) {\
+    a.q[0] = test_values[2*i][0];\
+    a.q[1] = test_values[2*i][1];\
+    asm volatile (#op " $" #ib ", %0" : "=x" (r.dq) : "0" (a.dq));\
+    printf("%-9s: a=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
+           #op,\
+           a.q[1], a.q[0],\
+           ib,\
+           r.q[1], r.q[0]);\
+    }\
+}
+
+#define SHIFT_OP(op, ib)\
+{\
+    int i;\
+    SHIFT_IM(op, ib);\
+    for(i=0;i<2;i++) {\
+    a.q[0] = test_values[2*i][0];\
+    a.q[1] = test_values[2*i][1];\
+    b.q[0] = ib;\
+    b.q[1] = 0;\
+    asm volatile (#op " %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
+    printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
+           #op,\
+           a.q[1], a.q[0],\
+           b.q[1], b.q[0],\
+           r.q[1], r.q[0]);\
+    }\
+}
+
+#define MOVMSK(op)\
+{\
+    int i, reg;\
+    for(i=0;i<2;i++) {\
+    a.q[0] = test_values[2*i][0];\
+    a.q[1] = test_values[2*i][1];\
+    asm volatile (#op " %1, %0" : "=r" (reg) : "x" (a.dq));\
+    printf("%-9s: a=" FMT64X "" FMT64X " r=%08x\n",\
+           #op,\
+           a.q[1], a.q[0],\
+           reg);\
+    }\
+}
+
+#define SSE_OPS(a) \
+SSE_OP(a ## ps);\
+SSE_OP(a ## ss);
+
+#define SSE_OPD(a) \
+SSE_OP(a ## pd);\
+SSE_OP(a ## sd);
+
+#define SSE_COMI(op, field)\
+{\
+    unsigned int eflags;\
+    XMMReg a, b;\
+    a.field[0] = a1;\
+    b.field[0] = b1;\
+    asm volatile (#op " %2, %1\n"\
+        "pushf\n"\
+        "pop %0\n"\
+        : "=m" (eflags)\
+        : "x" (a.dq), "x" (b.dq));\
+    printf("%-9s: a=%f b=%f cc=%04x\n",\
+           #op, a1, b1,\
+           eflags & (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A));\
+}
+
+void test_sse_comi(double a1, double b1)
+{
+    SSE_COMI(ucomiss, s);
+    SSE_COMI(ucomisd, d);
+    SSE_COMI(comiss, s);
+    SSE_COMI(comisd, d);
+}
+
+#define CVT_OP_XMM(op)\
+{\
+    asm volatile (#op " %1, %0" : "=x" (r.dq) : "x" (a.dq));\
+    printf("%-9s: a=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
+           #op,\
+           a.q[1], a.q[0],\
+           r.q[1], r.q[0]);\
+}
+
+/* Force %xmm0 usage to avoid the case where both register index are 0
+   to test intruction decoding more extensively */
+#define CVT_OP_XMM2MMX(op)\
+{\
+    asm volatile (#op " %1, %0" : "=y" (r.q[0]) : "x" (a.dq) \
+                  : "%xmm0");\
+    printf("%-9s: a=" FMT64X "" FMT64X " r=" FMT64X "\n",\
+           #op,\
+           a.q[1], a.q[0],\
+           r.q[0]);\
+}
+
+#define CVT_OP_MMX2XMM(op)\
+{\
+    asm volatile (#op " %1, %0" : "=x" (r.dq) : "y" (a.q[0]));\
+    printf("%-9s: a=" FMT64X " r=" FMT64X "" FMT64X "\n",\
+           #op,\
+           a.q[0],\
+           r.q[1], r.q[0]);\
+}
+
+#define CVT_OP_REG2XMM(op)\
+{\
+    asm volatile (#op " %1, %0" : "=x" (r.dq) : "r" (a.l[0]));\
+    printf("%-9s: a=%08x r=" FMT64X "" FMT64X "\n",\
+           #op,\
+           a.l[0],\
+           r.q[1], r.q[0]);\
+}
+
+#define CVT_OP_XMM2REG(op)\
+{\
+    asm volatile (#op " %1, %0" : "=r" (r.l[0]) : "x" (a.dq));\
+    printf("%-9s: a=" FMT64X "" FMT64X " r=%08x\n",\
+           #op,\
+           a.q[1], a.q[0],\
+           r.l[0]);\
+}
+
+struct fpxstate {
+    uint16_t fpuc;
+    uint16_t fpus;
+    uint16_t fptag;
+    uint16_t fop;
+    uint32_t fpuip;
+    uint16_t cs_sel;
+    uint16_t dummy0;
+    uint32_t fpudp;
+    uint16_t ds_sel;
+    uint16_t dummy1;
+    uint32_t mxcsr;
+    uint32_t mxcsr_mask;
+    uint8_t fpregs1[8 * 16];
+    uint8_t xmm_regs[8 * 16];
+    uint8_t dummy2[224];
+};
+
+static struct fpxstate fpx_state __attribute__((aligned(16)));
+static struct fpxstate fpx_state2 __attribute__((aligned(16)));
+
+void test_fxsave(void)
+{
+    struct fpxstate *fp = &fpx_state;
+    struct fpxstate *fp2 = &fpx_state2;
+    int i, nb_xmm;
+    XMMReg a, b;
+    a.q[0] = test_values[0][0];
+    a.q[1] = test_values[0][1];
+    b.q[0] = test_values[1][0];
+    b.q[1] = test_values[1][1];
+
+    asm("movdqa %2, %%xmm0\n"
+        "movdqa %3, %%xmm7\n"
+#if defined(__x86_64__)
+        "movdqa %2, %%xmm15\n"
+#endif
+        " fld1\n"
+        " fldpi\n"
+        " fldln2\n"
+        " fxsave %0\n"
+        " fxrstor %0\n"
+        " fxsave %1\n"
+        " fninit\n"
+        : "=m" (*(uint32_t *)fp2), "=m" (*(uint32_t *)fp) 
+        : "m" (a), "m" (b));
+    printf("fpuc=%04x\n", fp->fpuc);
+    printf("fpus=%04x\n", fp->fpus);
+    printf("fptag=%04x\n", fp->fptag);
+    for(i = 0; i < 3; i++) {
+        printf("ST%d: " FMT64X " %04x\n",
+               i, 
+               *(uint64_t *)&fp->fpregs1[i * 16],
+               *(uint16_t *)&fp->fpregs1[i * 16 + 8]);
+    }
+    printf("mxcsr=%08x\n", fp->mxcsr & 0x1f80);
+#if defined(__x86_64__)
+    nb_xmm = 16;
+#else
+    nb_xmm = 8;
+#endif
+    for(i = 0; i < nb_xmm; i++) {
+        printf("xmm%d: " FMT64X "" FMT64X "\n",
+               i, 
+               *(uint64_t *)&fp->xmm_regs[i * 16],
+               *(uint64_t *)&fp->xmm_regs[i * 16 + 8]);
+    }
+}
+
+void test_sse(void)
+{
+    XMMReg r, a, b;
+    int i;
+
+    MMX_OP2(punpcklbw);
+    MMX_OP2(punpcklwd);
+    MMX_OP2(punpckldq);
+    MMX_OP2(packsswb);
+    MMX_OP2(pcmpgtb);
+    MMX_OP2(pcmpgtw);
+    MMX_OP2(pcmpgtd);
+    MMX_OP2(packuswb);
+    MMX_OP2(punpckhbw);
+    MMX_OP2(punpckhwd);
+    MMX_OP2(punpckhdq);
+    MMX_OP2(packssdw);
+    MMX_OP2(pcmpeqb);
+    MMX_OP2(pcmpeqw);
+    MMX_OP2(pcmpeqd);
+
+    MMX_OP2(paddq);
+    MMX_OP2(pmullw);
+    MMX_OP2(psubusb);
+    MMX_OP2(psubusw);
+    MMX_OP2(pminub);
+    MMX_OP2(pand);
+    MMX_OP2(paddusb);
+    MMX_OP2(paddusw);
+    MMX_OP2(pmaxub);
+    MMX_OP2(pandn);
+
+    MMX_OP2(pmulhuw);
+    MMX_OP2(pmulhw);
     
-static void *call_end __init_call = NULL;
+    MMX_OP2(psubsb);
+    MMX_OP2(psubsw);
+    MMX_OP2(pminsw);
+    MMX_OP2(por);
+    MMX_OP2(paddsb);
+    MMX_OP2(paddsw);
+    MMX_OP2(pmaxsw);
+    MMX_OP2(pxor);
+    MMX_OP2(pmuludq);
+    MMX_OP2(pmaddwd);
+    MMX_OP2(psadbw);
+    MMX_OP2(psubb);
+    MMX_OP2(psubw);
+    MMX_OP2(psubd);
+    MMX_OP2(psubq);
+    MMX_OP2(paddb);
+    MMX_OP2(paddw);
+    MMX_OP2(paddd);
+
+    MMX_OP2(pavgb);
+    MMX_OP2(pavgw);
+
+    asm volatile ("pinsrw $1, %1, %0" : "=y" (r.q[0]) : "r" (0x12345678));
+    printf("%-9s: r=" FMT64X "\n", "pinsrw", r.q[0]);
+
+    asm volatile ("pinsrw $5, %1, %0" : "=x" (r.dq) : "r" (0x12345678));
+    printf("%-9s: r=" FMT64X "" FMT64X "\n", "pinsrw", r.q[1], r.q[0]);
+
+    a.q[0] = test_values[0][0];
+    a.q[1] = test_values[0][1];
+    asm volatile ("pextrw $1, %1, %0" : "=r" (r.l[0]) : "y" (a.q[0]));
+    printf("%-9s: r=%08x\n", "pextrw", r.l[0]);
+
+    asm volatile ("pextrw $5, %1, %0" : "=r" (r.l[0]) : "x" (a.dq));
+    printf("%-9s: r=%08x\n", "pextrw", r.l[0]);
+
+    asm volatile ("pmovmskb %1, %0" : "=r" (r.l[0]) : "y" (a.q[0]));
+    printf("%-9s: r=%08x\n", "pmovmskb", r.l[0]);
+    
+    asm volatile ("pmovmskb %1, %0" : "=r" (r.l[0]) : "x" (a.dq));
+    printf("%-9s: r=%08x\n", "pmovmskb", r.l[0]);
+
+    {
+        r.q[0] = -1;
+        r.q[1] = -1;
+
+        a.q[0] = test_values[0][0];
+        a.q[1] = test_values[0][1];
+        b.q[0] = test_values[1][0];
+        b.q[1] = test_values[1][1];
+        asm volatile("maskmovq %1, %0" : 
+                     : "y" (a.q[0]), "y" (b.q[0]), "D" (&r)
+                     : "memory"); 
+        printf("%-9s: r=" FMT64X " a=" FMT64X " b=" FMT64X "\n", 
+               "maskmov", 
+               r.q[0], 
+               a.q[0], 
+               b.q[0]);
+        asm volatile("maskmovdqu %1, %0" : 
+                     : "x" (a.dq), "x" (b.dq), "D" (&r)
+                     : "memory"); 
+        printf("%-9s: r=" FMT64X "" FMT64X " a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X "\n", 
+               "maskmov", 
+               r.q[1], r.q[0], 
+               a.q[1], a.q[0], 
+               b.q[1], b.q[0]);
+    }
+
+    asm volatile ("emms");
+
+    SSE_OP2(punpcklqdq);
+    SSE_OP2(punpckhqdq);
+    SSE_OP2(andps);
+    SSE_OP2(andpd);
+    SSE_OP2(andnps);
+    SSE_OP2(andnpd);
+    SSE_OP2(orps);
+    SSE_OP2(orpd);
+    SSE_OP2(xorps);
+    SSE_OP2(xorpd);
+
+    SSE_OP2(unpcklps);
+    SSE_OP2(unpcklpd);
+    SSE_OP2(unpckhps);
+    SSE_OP2(unpckhpd);
+
+    SHUF_OP(shufps, 0x78);
+    SHUF_OP(shufpd, 0x02);
+
+    PSHUF_OP(pshufd, 0x78);
+    PSHUF_OP(pshuflw, 0x78);
+    PSHUF_OP(pshufhw, 0x78);
+
+    SHIFT_OP(psrlw, 7);
+    SHIFT_OP(psrlw, 16);
+    SHIFT_OP(psraw, 7);
+    SHIFT_OP(psraw, 16);
+    SHIFT_OP(psllw, 7);
+    SHIFT_OP(psllw, 16);
+
+    SHIFT_OP(psrld, 7);
+    SHIFT_OP(psrld, 32);
+    SHIFT_OP(psrad, 7);
+    SHIFT_OP(psrad, 32);
+    SHIFT_OP(pslld, 7);
+    SHIFT_OP(pslld, 32);
+
+    SHIFT_OP(psrlq, 7);
+    SHIFT_OP(psrlq, 32);
+    SHIFT_OP(psllq, 7);
+    SHIFT_OP(psllq, 32);
+
+    SHIFT_IM(psrldq, 16);
+    SHIFT_IM(psrldq, 7);
+    SHIFT_IM(pslldq, 16);
+    SHIFT_IM(pslldq, 7);
+
+    MOVMSK(movmskps);
+    MOVMSK(movmskpd);
+
+    /* FPU specific ops */
+
+    {
+        uint32_t mxcsr;
+        asm volatile("stmxcsr %0" : "=m" (mxcsr));
+        printf("mxcsr=%08x\n", mxcsr & 0x1f80);
+        asm volatile("ldmxcsr %0" : : "m" (mxcsr));
+    }
+
+    test_sse_comi(2, -1);
+    test_sse_comi(2, 2);
+    test_sse_comi(2, 3);
+    test_sse_comi(2, q_nan.d);
+    test_sse_comi(q_nan.d, -1);
+
+    for(i = 0; i < 2; i++) {
+        a.s[0] = 2.7;
+        a.s[1] = 3.4;
+        a.s[2] = 4;
+        a.s[3] = -6.3;
+        b.s[0] = 45.7;
+        b.s[1] = 353.4;
+        b.s[2] = 4;
+        b.s[3] = 56.3;
+        if (i == 1) {
+            a.s[0] = q_nan.d;
+            b.s[3] = q_nan.d;
+        }
+
+        SSE_OPS(add);
+        SSE_OPS(mul);
+        SSE_OPS(sub);
+        SSE_OPS(min);
+        SSE_OPS(div);
+        SSE_OPS(max);
+        SSE_OPS(sqrt);
+        SSE_OPS(cmpeq);
+        SSE_OPS(cmplt);
+        SSE_OPS(cmple);
+        SSE_OPS(cmpunord);
+        SSE_OPS(cmpneq);
+        SSE_OPS(cmpnlt);
+        SSE_OPS(cmpnle);
+        SSE_OPS(cmpord);
+        
+        
+        a.d[0] = 2.7;
+        a.d[1] = -3.4;
+        b.d[0] = 45.7;
+        b.d[1] = -53.4;
+        if (i == 1) {
+            a.d[0] = q_nan.d;
+            b.d[1] = q_nan.d;
+        }
+        SSE_OPD(add);
+        SSE_OPD(mul);
+        SSE_OPD(sub);
+        SSE_OPD(min);
+        SSE_OPD(div);
+        SSE_OPD(max);
+        SSE_OPD(sqrt);
+        SSE_OPD(cmpeq);
+        SSE_OPD(cmplt);
+        SSE_OPD(cmple);
+        SSE_OPD(cmpunord);
+        SSE_OPD(cmpneq);
+        SSE_OPD(cmpnlt);
+        SSE_OPD(cmpnle);
+        SSE_OPD(cmpord);
+    }
+
+    /* float to float/int */
+    a.s[0] = 2.7;
+    a.s[1] = 3.4;
+    a.s[2] = 4;
+    a.s[3] = -6.3;
+    CVT_OP_XMM(cvtps2pd);
+    CVT_OP_XMM(cvtss2sd);
+    CVT_OP_XMM2MMX(cvtps2pi);
+    CVT_OP_XMM2MMX(cvttps2pi);
+    CVT_OP_XMM2REG(cvtss2si);
+    CVT_OP_XMM2REG(cvttss2si);
+    CVT_OP_XMM(cvtps2dq);
+    CVT_OP_XMM(cvttps2dq);
+
+    a.d[0] = 2.6;
+    a.d[1] = -3.4;
+    CVT_OP_XMM(cvtpd2ps);
+    CVT_OP_XMM(cvtsd2ss);
+    CVT_OP_XMM2MMX(cvtpd2pi);
+    CVT_OP_XMM2MMX(cvttpd2pi);
+    CVT_OP_XMM2REG(cvtsd2si);
+    CVT_OP_XMM2REG(cvttsd2si);
+    CVT_OP_XMM(cvtpd2dq);
+    CVT_OP_XMM(cvttpd2dq);
+
+    /* sse/mmx moves */
+    CVT_OP_XMM2MMX(movdq2q);
+    CVT_OP_MMX2XMM(movq2dq);
+
+    /* int to float */
+    a.l[0] = -6;
+    a.l[1] = 2;
+    a.l[2] = 100;
+    a.l[3] = -60000;
+    CVT_OP_MMX2XMM(cvtpi2ps);
+    CVT_OP_MMX2XMM(cvtpi2pd);
+    CVT_OP_REG2XMM(cvtsi2ss);
+    CVT_OP_REG2XMM(cvtsi2sd);
+    CVT_OP_XMM(cvtdq2ps);
+    CVT_OP_XMM(cvtdq2pd);
+
+    /* XXX: test PNI insns */
+#if 0
+    SSE_OP2(movshdup);
+#endif
+    asm volatile ("emms");
+}
+
+#endif
+
+extern void *__start_initcall;
+extern void *__stop_initcall;
+
 
 int main(int argc, char **argv)
@@ -1634 +2593 @@
     void (*func)(void);
 
-    ptr = &call_start + 1;
-    while (*ptr != NULL) {
+    ptr = &__start_initcall;
+    while (ptr != &__stop_initcall) {
         func = *ptr++;
         func();
@@ -1643 +2602 @@
     test_jcc();
     test_floats();
+#if !defined(__x86_64__)
     test_bcd();
+#endif
     test_xchg();
     test_string();
     test_misc();
     test_lea();
+#ifdef TEST_SEGS
     test_segs();
     test_code16();
+#endif
+#ifdef TEST_VM86
     test_vm86();
+#endif
     test_exceptions();
+#if !defined(__x86_64__)
     test_self_modifying_code();
     test_single_step();
+#endif
+    test_enter();
+#ifdef TEST_SSE
+    test_sse();
+    test_fxsave();
+#endif
     return 0;
 }

trunk/src/recompiler/tests/test-i386.h

@@ -1 +1 @@
 
 #define exec_op glue(exec_, OP)
+#define exec_opq glue(glue(exec_, OP), q)
 #define exec_opl glue(glue(exec_, OP), l)
 #define exec_opw glue(glue(exec_, OP), w)
 #define exec_opb glue(glue(exec_, OP), b)
 
-#define EXECOP2(size, res, s1, flags) \
+#define EXECOP2(size, rsize, res, s1, flags) \
     asm ("push %4\n\t"\
          "popf\n\t"\
-         stringify(OP) size " %" size "2, %" size "0\n\t" \
+         stringify(OP) size " %" rsize "2, %" rsize "0\n\t" \
          "pushf\n\t"\
-         "popl %1\n\t"\
+         "pop %1\n\t"\
          : "=q" (res), "=g" (flags)\
-         : "q" (s1), "0" (res), "1" (flags));
+         : "q" (s1), "0" (res), "1" (flags)); \
+    printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CCIN=%04lx CC=%04lx\n", \
+           stringify(OP) size, s0, s1, res, iflags, flags & CC_MASK);
 
-#define EXECOP1(size, res, flags) \
+#define EXECOP1(size, rsize, res, flags) \
     asm ("push %3\n\t"\
          "popf\n\t"\
-         stringify(OP) size " %" size "0\n\t" \
+         stringify(OP) size " %" rsize "0\n\t" \
          "pushf\n\t"\
-         "popl %1\n\t"\
+         "pop %1\n\t"\
          : "=q" (res), "=g" (flags)\
-         : "0" (res), "1" (flags));
+         : "0" (res), "1" (flags)); \
+    printf("%-10s A=" FMTLX " R=" FMTLX " CCIN=%04lx CC=%04lx\n", \
+           stringify(OP) size, s0, res, iflags, flags & CC_MASK);
 
 #ifdef OP1
-void exec_opl(int s0, int s1, int iflags)
+#if defined(__x86_64__)
+void exec_opq(long s0, long s1, long iflags)
 {
-    int res, flags;
+    long res, flags;
     res = s0;
     flags = iflags;
-    EXECOP1("", res, flags);
-    printf("%-10s A=%08x R=%08x CCIN=%04x CC=%04x\n",
-           stringify(OP) "l", s0, res, iflags, flags & CC_MASK);
-}
-
-void exec_opw(int s0, int s1, int iflags)
-{
-    int res, flags;
-    res = s0;
-    flags = iflags;
-    EXECOP1("w", res, flags);
-    printf("%-10s A=%08x R=%08x CCIN=%04x CC=%04x\n",
-           stringify(OP) "w", s0, res, iflags, flags & CC_MASK);
-}
-
-void exec_opb(int s0, int s1, int iflags)
-{
-    int res, flags;
-    res = s0;
-    flags = iflags;
-    EXECOP1("b", res, flags);
-    printf("%-10s A=%08x R=%08x CCIN=%04x CC=%04x\n",
-           stringify(OP) "b", s0, res, iflags, flags & CC_MASK);
-}
-#else
-void exec_opl(int s0, int s1, int iflags)
-{
-    int res, flags;
-    res = s0;
-    flags = iflags;
-    EXECOP2("", res, s1, flags);
-    printf("%-10s A=%08x B=%08x R=%08x CCIN=%04x CC=%04x\n",
-           stringify(OP) "l", s0, s1, res, iflags, flags & CC_MASK);
-}
-
-void exec_opw(int s0, int s1, int iflags)
-{
-    int res, flags;
-    res = s0;
-    flags = iflags;
-    EXECOP2("w", res, s1, flags);
-    printf("%-10s A=%08x B=%08x R=%08x CCIN=%04x CC=%04x\n",
-           stringify(OP) "w", s0, s1, res, iflags, flags & CC_MASK);
-}
-
-void exec_opb(int s0, int s1, int iflags)
-{
-    int res, flags;
-    res = s0;
-    flags = iflags;
-    EXECOP2("b", res, s1, flags);
-    printf("%-10s A=%08x B=%08x R=%08x CCIN=%04x CC=%04x\n",
-           stringify(OP) "b", s0, s1, res, iflags, flags & CC_MASK);
+    EXECOP1("q", "", res, flags);
 }
 #endif
 
-void exec_op(int s0, int s1)
+void exec_opl(long s0, long s1, long iflags)
 {
+    long res, flags;
+    res = s0;
+    flags = iflags;
+    EXECOP1("l", "k", res, flags);
+}
+
+void exec_opw(long s0, long s1, long iflags)
+{
+    long res, flags;
+    res = s0;
+    flags = iflags;
+    EXECOP1("w", "w", res, flags);
+}
+
+void exec_opb(long s0, long s1, long iflags)
+{
+    long res, flags;
+    res = s0;
+    flags = iflags;
+    EXECOP1("b", "b", res, flags);
+}
+#else
+#if defined(__x86_64__)
+void exec_opq(long s0, long s1, long iflags)
+{
+    long res, flags;
+    res = s0;
+    flags = iflags;
+    EXECOP2("q", "", res, s1, flags);
+}
+#endif
+
+void exec_opl(long s0, long s1, long iflags)
+{
+    long res, flags;
+    res = s0;
+    flags = iflags;
+    EXECOP2("l", "k", res, s1, flags);
+}
+
+void exec_opw(long s0, long s1, long iflags)
+{
+    long res, flags;
+    res = s0;
+    flags = iflags;
+    EXECOP2("w", "w", res, s1, flags);
+}
+
+void exec_opb(long s0, long s1, long iflags)
+{
+    long res, flags;
+    res = s0;
+    flags = iflags;
+    EXECOP2("b", "b", res, s1, flags);
+}
+#endif
+
+void exec_op(long s0, long s1)
+{
+    s0 = i2l(s0);
+    s1 = i2l(s1);
+#if defined(__x86_64__)
+    exec_opq(s0, s1, 0);
+#endif
     exec_opl(s0, s1, 0);
     exec_opw(s0, s1, 0);
     exec_opb(s0, s1, 0);
 #ifdef OP_CC
+#if defined(__x86_64__)
+    exec_opq(s0, s1, CC_C);
+#endif
     exec_opl(s0, s1, CC_C);
     exec_opw(s0, s1, CC_C);