Changeset 24959 in vbox for trunk/src/VBox/VMM

Timestamp:

Nov 25, 2009 3:31:10 PM (15 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

55257

Message:

CPUM,HWACCM: Moved the fixing up of csHid.n.u1Granularity to HWACCM because several SELM APIs expect it to be set correctly.

Location:

trunk/src/VBox/VMM

Files:

• CPUM.cpp (modified) (1 diff)
• VMMR0/HWSVMR0.cpp (modified) (1 diff)

trunk/src/VBox/VMM/CPUM.cpp

@@ -1948 +1948 @@
                 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
                     SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
-
-                /*
-                 * HACK ALERT! Workaround for missing granularity flag in CS on
-                 *             AMD-v.  This will cause trouble if the host now
-                 *             is using VT-x (teleporting, cold migration).
-                 * May consider moving this into SVM_READ_SELREG or there about.
-                 */
-                if (    !pVM->aCpus[i].cpum.s.Guest.csHid.Attr.n.u1Granularity
-                    &&   pVM->aCpus[i].cpum.s.Guest.csHid.u32Limit > UINT16_MAX)
-                    pVM->aCpus[i].cpum.s.Guest.csHid.Attr.n.u1Granularity = 1;
             }
         }

trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

@@ -1435 +1435 @@
     SVM_READ_SELREG(GS, gs);
 
+    /* Correct the hidden CS granularity flag.  Haven't seen it being wrong in
+       any other register (yet). */
+    if (   !pCtx->csHid.Attr.n.u1Granularity
+        &&  pCtx->csHid.Attr.n.u1Present
+        &&  pCtx->csHid.u32Limit > UINT32_C(0xffff))
+    {
+        Assert((pCtx->csHid.u32Limit & 0xfff) == 0xfff);
+        pCtx->csHid.Attr.n.u1Granularity = 1;
+    }
+#define SVM_ASSERT_SEL_GRANULARITY(reg) \
+        AssertMsg(!pCtx->reg##Hid.Attr.n.u1Present \
+                  || (   pCtx->reg##Hid.Attr.n.u1Granularity \
+                      ? (pCtx->reg##Hid.u32Limit & 0xfff) == 0xfff \
+                      :  pCtx->reg##Hid.u32Limit <= 0xffff), \
+                  ("%#x\n", pCtx->reg##Hid.u32Limit))
+    SVM_ASSERT_SEL_GRANULARITY(ss);
+    SVM_ASSERT_SEL_GRANULARITY(cs);
+    SVM_ASSERT_SEL_GRANULARITY(ds);
+    SVM_ASSERT_SEL_GRANULARITY(es);
+    SVM_ASSERT_SEL_GRANULARITY(fs);
+    SVM_ASSERT_SEL_GRANULARITY(gs);
+#undef  SVM_ASSERT_SEL_GRANULARITY
+
     /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
     SVM_READ_SELREG(LDTR, ldtr);