VirtualBox

Changeset 25192 in vbox


Ignore:
Timestamp:
Dec 4, 2009 1:56:27 PM (15 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
55665
Message:

Storage/DevATA: fix device reset if a transfer redo is pending. Triggered release assertions (which was good, because if that check was missing the guest would have been with a totally unresponsive hard disk) with message "I/O state inconsistent: state=0 request=1". Reproducing is pretty much impossible unless using an iSCSI target which becomes unresponsive at just the right time, i.e. when doing big transfers.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/Devices/Storage/DevATA.cpp

    r24761 r25192  
    776776                break;
    777777            case ATA_AIO_DMA:
    778                 LogRel(("dma transfer finished\n"));
     778                LogRel(("dma transfer continuation\n"));
    779779                break;
    780780            case ATA_AIO_PIO:
    781                 LogRel(("pio transfer finished\n"));
     781                LogRel(("pio transfer continuation\n"));
    782782                break;
    783783            case ATA_AIO_RESET_ASSERTED:
     
    46484648                        fRedo = g_apfnSourceSinkFuncs[s->iSourceSink](s);
    46494649                        pCtl->fRedo = fRedo;
    4650                         if (RT_UNLIKELY(fRedo))
     4650                        if (RT_UNLIKELY(fRedo && !pCtl->fReset))
    46514651                        {
    46524652                            /* Operation failed at the initial transfer, restart
     
    47554755                ataDMATransfer(pCtl);
    47564756
    4757                 if (RT_UNLIKELY(pCtl->fRedo))
     4757                if (RT_UNLIKELY(pCtl->fRedo && !pCtl->fReset))
    47584758                {
    47594759                    LogRel(("PIIX3 ATA: Ctl#%d: redo DMA operation\n", ATACONTROLLER_IDX(pCtl)));
     
    48004800                    fRedo = g_apfnSourceSinkFuncs[s->iSourceSink](s);
    48014801                    pCtl->fRedo = fRedo;
    4802                     if (RT_UNLIKELY(fRedo))
     4802                    if (RT_UNLIKELY(fRedo && !pCtl->fReset))
    48034803                    {
    48044804                        LogRel(("PIIX3 ATA: Ctl#%d: redo PIO operation\n", ATACONTROLLER_IDX(pCtl)));
     
    48754875                pCtl->uAsyncIOState = ATA_AIO_NEW;
    48764876                pCtl->fReset = false;
     4877                /* Ensure that half-completed transfers are not redone. A reset
     4878                 * cancels the entire transfer, so continuing is wrong. */
     4879                pCtl->fRedo = false;
     4880                pCtl->fRedoDMALastDesc = false;
    48774881                LogRel(("PIIX3 ATA: Ctl#%d: finished processing RESET\n",
    48784882                        ATACONTROLLER_IDX(pCtl)));
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