Changeset 25245 in vbox for trunk/src/VBox

Timestamp:

Dec 8, 2009 1:53:59 PM (15 years ago)

Author:

vboxsync

Message:

PGMAllShw.h: -Wshadow

File:

• trunk/src/VBox/VMM/VMMAll/PGMAllBth.h (modified) (15 diffs)

trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

@@ -538 +538 @@
                         {
                            /* Check by physical address. */
-                            PPGMVIRTHANDLER pCur;
                             unsigned        iPage;
                             rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + (pvFault & PAGE_OFFSET_MASK),
@@ -682 +681 @@
 
 #   if defined(LOG_ENABLED) && !defined(IN_RING0)
-                RTGCPHYS   GCPhys;
-                uint64_t   fPageGst;
-                PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys);
-                Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%RGp scan=%d\n",
-                     pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
+                RTGCPHYS   GCPhys2;
+                uint64_t   fPageGst2;
+                PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
+                Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
+                     pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
 #   endif /* LOG_ENABLED */
 
@@ -845 +844 @@
 #   endif
 #   ifdef VBOX_STRICT
-                        RTGCPHYS GCPhys;
+                        RTGCPHYS GCPhys2;
                         uint64_t fPageGst;
                         if (!HWACCMIsNestedPagingActive(pVM))
                         {
-                            rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys);
+                            rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
                             AssertMsg(RT_SUCCESS(rc) && (fPageGst & X86_PTE_RW), ("rc=%d fPageGst=%RX64\n"));
-                            LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
+                            LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
                         }
                         uint64_t fPageShw;
@@ -1717 +1716 @@
 
     /* Fetch the pgm pool shadow descriptor. */
-    int rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
-    AssertRCSuccessReturn(rc, rc);
+    int rc2 = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
+    AssertRCSuccessReturn(rc2, rc2);
     Assert(pShwPde);
 
@@ -1730 +1729 @@
     PX86PDPT        pPdptDst = NULL;            /* initialized to shut up gcc */
 
-    int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
-    AssertRCSuccessReturn(rc, rc);
+    int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
+    AssertRCSuccessReturn(rc2, rc2);
     Assert(pPDDst && pPdptDst);
     PX86PDEPAE      pPdeDst = &pPDDst->a[iPDDst];
@@ -1771 +1770 @@
 # if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
         /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
-        GCPhys |= (iPDDst & 1) * (PAGE_SIZE/2);
+        GCPhys |= (iPDDst & 1) * (PAGE_SIZE / 2);
 # endif
     }
@@ -1894 +1893 @@
                  */
                 /* Calculate the GC physical address of this 4KB shadow page. */
-                RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) | (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
+                GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) | (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
                 /* Find ram range. */
                 PPGMPAGE pPage;
@@ -2500 +2499 @@
              * Map the guest page table.
              */
-            PGSTPT pPTSrc;
-            rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
+            PGSTPT pPTSrc2;
+            rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc2);
             if (RT_SUCCESS(rc))
             {
-                PGSTPTE         pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
+                PGSTPTE         pPteSrc = &pPTSrc2->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
                 const GSTPTE    PteSrc = *pPteSrc;
                 if (pPteSrc->n.u1Present)
@@ -2612 +2611 @@
         Assert(pMapping);
 #   if PGM_GST_TYPE == PGM_TYPE_32BIT
-        int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
+        rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
 #   elif PGM_GST_TYPE == PGM_TYPE_PAE
-        int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
+        rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
 #   else
         AssertFailed();     /* can't happen for amd64 */
@@ -3129 +3128 @@
      * PD and PDE in the processes.
      */
-    int             rc      = VINF_SUCCESS;
+    int             rc     = VINF_SUCCESS;
 # if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
 #  if PGM_GST_TYPE == PGM_TYPE_32BIT
@@ -3178 +3177 @@
         PdpeSrc.u  = X86_PDPE_P;   /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
 #   endif
-        int rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
+        rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
         if (rc != VINF_SUCCESS)
         {
@@ -3204 +3203 @@
 #  endif
 
-        int rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
+        rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
         if (rc != VINF_SUCCESS)
         {
@@ -3703 +3702 @@
             PX86PDPT        pPdptDst  = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
 #  else
-            PX86PML4E       pPml4eSrc;
+            PX86PML4E       pPml4eSrcIgn;
             X86PDPE         PdpeSrc;
             PX86PDPT        pPdptDst;
             PX86PDPAE       pPDDst;
-            PGSTPD          pPDSrc    = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
+            PGSTPD          pPDSrc    = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
 
             rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
@@ -4326 +4325 @@
     RTHCPHYS    HCPhysGuestCR3;
     pgmLock(pVM);
-    PPGMPAGE    pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
-    AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
-    HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPage);
+    PPGMPAGE    pPageCR3 = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
+    AssertReturn(pPageCR3, VERR_INTERNAL_ERROR_2);
+    HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
     /** @todo this needs some reworking wrt. locking.  */
 # if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
@@ -4334 +4333 @@
     int rc = VINF_SUCCESS;
 # else
-    int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3 & GST_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3); /** @todo r=bird: This GCPhysCR3 masking isn't necessary. */
+    int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3); /** @todo r=bird: This GCPhysCR3 masking isn't necessary. */
 # endif
     pgmUnlock(pVM);