Changeset 25835 in vbox for trunk/src/VBox/VMM

Timestamp:

Jan 14, 2010 4:27:58 PM (15 years ago)

Author:

vboxsync

Message:

CPUM,VMM: Avoid calling CPUMGetGuestEFER until it's needed (see defect 4597). Also pushed the inlined CPUM predicates that was calling into CPUMGetSomething anyway into CPUMAllRegs.cpp since that's faster and smaller.

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• CPUMAllRegs.cpp (modified) (1 diff)
• PGMAllBth.h (modified) (3 diffs)
• PGMAllGst.h (modified) (4 diffs)
• PGMAllShw.h (modified) (3 diffs)

trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp

@@ -1698 +1698 @@
 }
 
+
+/**
+ * Tests if the guest has No-Execute Page Protection Enabled (NXE).
+ *
+ * @returns true if in real mode, otherwise false.
+ * @param   pVCpu       The virtual CPU handle.
+ */
+VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu)
+{
+    return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
+}
+
+
+/**
+ * Tests if the guest is running in real mode or not.
+ *
+ * @returns true if in real mode, otherwise false.
+ * @param   pVCpu       The virtual CPU handle.
+ */
+VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu)
+{
+    return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
+}
+
+
+/**
+ * Tests if the guest is running in protected or not.
+ *
+ * @returns true if in protected mode, otherwise false.
+ * @param   pVCpu       The virtual CPU handle.
+ */
+VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu)
+{
+    return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
+}
+
+
+/**
+ * Tests if the guest is running in paged protected or not.
+ *
+ * @returns true if in paged protected mode, otherwise false.
+ * @param   pVCpu       The virtual CPU handle.
+ */
+VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu)
+{
+    return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
+}
+
+
+/**
+ * Tests if the guest is running in long mode or not.
+ *
+ * @returns true if in long mode, otherwise false.
+ * @param   pVCpu       The virtual CPU handle.
+ */
+VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu)
+{
+    return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
+}
+
+
+/**
+ * Tests if the guest is running in PAE mode or not.
+ *
+ * @returns true if in PAE mode, otherwise false.
+ * @param   pVCpu       The virtual CPU handle.
+ */
+VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu)
+{
+    return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
+        && (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG)
+        && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA);
+}
+
+
+
 #ifndef IN_RING0  /** @todo I don't think we need this in R0, so move it to CPUMAll.cpp? */
 

trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

@@ -1668 +1668 @@
 
 # if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
-    bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
+    bool fNoExecuteBitValid = CPUMIsGuestNXEnabled(pVCpu);
 # endif
 
@@ -2132 +2132 @@
 # endif
 # if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
-    bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
+    bool fNoExecuteBitValid = CPUMIsGuestNXEnabled(pVCpu);
 # endif
     unsigned uPageFaultLevel;
@@ -2644 +2644 @@
         {
             PGMPOOLACCESS enmAccess;
-
 # if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
-            const bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
-            const bool fNoExecute = fNoExecuteBitValid && PdeSrc.n.u1NoExecute;
+            const bool fNoExecute = PdeSrc.n.u1NoExecute && CPUMIsGuestNXEnabled(pVCpu);
 # else
             const bool fNoExecute = false;

trunk/src/VBox/VMM/VMMAll/PGMAllGst.h

@@ -80 +80 @@
      * All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx). */
     X86PDEPAE   Pde = pgmGstGetPaePDE(&pVCpu->pgm.s, GCPtr);
-    bool        fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
 
 #elif PGM_GST_TYPE == PGM_TYPE_AMD64
@@ -86 +85 @@
     X86PDPE     Pdpe;
     X86PDEPAE   Pde = pgmGstGetLongModePDEEx(&pVCpu->pgm.s, GCPtr, &pPml4e, &Pdpe);
-    bool        fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
 
     Assert(pPml4e);
@@ -134 +132 @@
 # if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
             /* The NX bit is determined by a bitwise OR between the PT and PD */
-            if (fNoExecuteBitValid)
+            if (CPUMIsGuestNXEnabled(pVCpu))
                 *pfFlags |= (Pte.u & Pde.u & X86_PTE_PAE_NX);
 # endif
@@ -152 +150 @@
 # if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
             /* The NX bit is determined by a bitwise OR between the PT and PD */
-            if (fNoExecuteBitValid)
+            if (CPUMIsGuestNXEnabled(pVCpu))
                 *pfFlags |= (Pde.u & X86_PTE_PAE_NX);
 # endif

trunk/src/VBox/VMM/VMMAll/PGMAllShw.h

@@ -152 +152 @@
      */
 # if PGM_SHW_TYPE == PGM_TYPE_AMD64
-    bool            fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
     X86PDEPAE Pde;
 
@@ -185 +184 @@
 
 # elif PGM_SHW_TYPE == PGM_TYPE_PAE
-    bool            fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
     X86PDEPAE       Pde = pgmShwGetPaePDE(&pVCpu->pgm.s, GCPtr);
 
@@ -253 +251 @@
 # if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE)
         /* The NX bit is determined by a bitwise OR between the PT and PD */
-        if (fNoExecuteBitValid)
+        if (CPUMIsGuestNXEnabled(pVCpu))
             *pfFlags |= (Pte.u & Pde.u & X86_PTE_PAE_NX);
 # endif