VirtualBox

Changeset 25837 in vbox for trunk/src/VBox


Ignore:
Timestamp:
Jan 14, 2010 4:50:45 PM (15 years ago)
Author:
vboxsync
Message:

VMM: More micro optimizations around CPUM getters and predicates.

Location:
trunk/src/VBox/VMM
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

    r25835 r25837  
    16671667    && PGM_SHW_TYPE != PGM_TYPE_EPT
    16681668
    1669 # if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
    1670     bool fNoExecuteBitValid = CPUMIsGuestNXEnabled(pVCpu);
    1671 # endif
    1672 
    16731669    /*
    16741670     * Assert preconditions.
     
    17671763        &&  (PdeSrc.n.u1Write == PdeDst.n.u1Write || !PdeDst.n.u1Write)
    17681764# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
    1769         &&  (!fNoExecuteBitValid || PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
     1765        &&  (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute || !CPUMIsGuestNXEnabled(pVCpu))
    17701766# endif
    17711767       )
     
    21312127    bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
    21322128# endif
    2133 # if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
    2134     bool fNoExecuteBitValid = CPUMIsGuestNXEnabled(pVCpu);
    2135 # endif
    21362129    unsigned uPageFaultLevel;
    21372130    int rc;
     
    21592152    if (    (uErr & X86_TRAP_PF_RSVD)
    21602153        ||  !pPml4eSrc->n.u1Present
    2161         ||  (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
     2154        ||  ((uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute && CPUMIsGuestNXEnabled(pVCpu))
    21622155        ||  (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault || fWriteProtect))
    21632156        ||  (fUserLevelFault && !pPml4eSrc->n.u1User)
     
    21792172        ||  !pPdpeSrc->n.u1Present
    21802173# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
    2181         ||  (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
     2174        ||  ((uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute && CPUMIsGuestNXEnabled(pVCpu))
    21822175        ||  (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault || fWriteProtect))
    21832176        ||  (fUserLevelFault && !pPdpeSrc->lm.u1User)
     
    21962189        ||  !pPdeSrc->n.u1Present
    21972190# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
    2198         ||  (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
     2191        ||  ((uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute && CPUMIsGuestNXEnabled(pVCpu))
    21992192# endif
    22002193        ||  (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault || fWriteProtect))
     
    22922285        if (    !PteSrc.n.u1Present
    22932286#  if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
    2294             ||  (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
     2287            ||  ((uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute && CPUMIsGuestNXEnabled(pVCpu))
    22952288#  endif
    22962289            ||  (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault || fWriteProtect))
  • trunk/src/VBox/VMM/VMMAll/PGMAllGst.h

    r25835 r25837  
    132132# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
    133133            /* The NX bit is determined by a bitwise OR between the PT and PD */
    134             if (CPUMIsGuestNXEnabled(pVCpu))
    135                 *pfFlags |= (Pte.u & Pde.u & X86_PTE_PAE_NX);
     134            if ((Pte.u & Pde.u & X86_PTE_PAE_NX) && CPUMIsGuestNXEnabled(pVCpu)) /** @todo the code is ANDing not ORing NX like the comment says... */
     135                *pfFlags |= X86_PTE_PAE_NX;
    136136# endif
    137137        }
     
    149149                     | ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
    150150# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
    151             /* The NX bit is determined by a bitwise OR between the PT and PD */
    152             if (CPUMIsGuestNXEnabled(pVCpu))
    153                 *pfFlags |= (Pde.u & X86_PTE_PAE_NX);
     151            if ((Pde.u & X86_PTE_PAE_NX) && CPUMIsGuestNXEnabled(pVCpu))
     152                *pfFlags |= X86_PTE_PAE_NX;
    154153# endif
    155154        }
  • trunk/src/VBox/VMM/VMMAll/PGMAllShw.h

    r25835 r25837  
    251251# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE)
    252252        /* The NX bit is determined by a bitwise OR between the PT and PD */
    253         if (CPUMIsGuestNXEnabled(pVCpu))
    254             *pfFlags |= (Pte.u & Pde.u & X86_PTE_PAE_NX);
     253        if ((Pte.u & Pde.u & X86_PTE_PAE_NX) && CPUMIsGuestNXEnabled(pVCpu)) /** @todo the code is ANDing not ORing NX like the comment says... */
     254            *pfFlags |= X86_PTE_PAE_NX;
    255255# endif
    256256    }
  • trunk/src/VBox/VMM/VMMAll/SELMAll.cpp

    r23303 r25837  
    9898     * Deal with real & v86 mode first.
    9999     */
    100     if (    CPUMIsGuestInRealMode(pVCpu)
    101         ||  pCtxCore->eflags.Bits.u1VM)
     100    if (    pCtxCore->eflags.Bits.u1VM
     101        ||  CPUMIsGuestInRealMode(pVCpu))
    102102    {
    103103        RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff;
     
    118118
    119119    /* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0 (Intel® 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */
    120     if (    CPUMIsGuestInLongMode(pVCpu)
    121         &&  pCtxCore->csHid.Attr.n.u1Long)
     120    if (    pCtxCore->csHid.Attr.n.u1Long
     121        &&  CPUMIsGuestInLongMode(pVCpu))
    122122    {
    123123        switch (SelReg)
     
    167167     * Deal with real & v86 mode first.
    168168     */
    169     if (    CPUMIsGuestInRealMode(pVCpu)
    170         ||  pCtxCore->eflags.Bits.u1VM)
     169    if (    pCtxCore->eflags.Bits.u1VM
     170        ||  CPUMIsGuestInRealMode(pVCpu))
    171171    {
    172172        RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff;
     
    201201
    202202        /* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0 (Intel® 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */
    203         if (    CPUMIsGuestInLongMode(pVCpu)
    204             &&  pCtxCore->csHid.Attr.n.u1Long)
     203        if (    pCtxCore->csHid.Attr.n.u1Long
     204            &&  CPUMIsGuestInLongMode(pVCpu))
    205205        {
    206206            fCheckLimit = false;
     
    473473     * Deal with real & v86 mode first.
    474474     */
    475     if (    CPUMIsGuestInRealMode(pVCpu)
    476         ||  eflags.Bits.u1VM)
     475    if (    eflags.Bits.u1VM
     476        ||  CPUMIsGuestInRealMode(pVCpu))
    477477    {
    478478        RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff;
     
    507507        pvFlat        = (RTGCPTR)(pHiddenSel->u64Base + (RTGCUINTPTR)Addr);
    508508
    509         if (   !CPUMIsGuestInLongMode(pVCpu)
    510             || !pHiddenSel->Attr.n.u1Long)
     509        if (   !pHiddenSel->Attr.n.u1Long
     510            || !CPUMIsGuestInLongMode(pVCpu))
    511511        {
    512512            /* AMD64 manual: compatibility mode ignores the high 32 bits when calculating an effective address. */
     
    798798            {
    799799                /* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0 (Intel® 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */
    800                 if (    CPUMIsGuestInLongMode(pVCpu)
    801                     &&  pHidCS->Attr.n.u1Long)
     800                if (    pHidCS->Attr.n.u1Long
     801                    &&  CPUMIsGuestInLongMode(pVCpu))
    802802                {
    803803                    *ppvFlat = Addr;
     
    849849    PVMCPU pVCpu = &pVM->aCpus[0];
    850850
    851     if (    CPUMIsGuestInRealMode(pVCpu)
    852         ||  eflags.Bits.u1VM)
     851    if (    eflags.Bits.u1VM
     852        ||  CPUMIsGuestInRealMode(pVCpu))
    853853    {
    854854        *pcBits = 16;
     
    877877    PVMCPU pVCpu = VMMGetCpu(pVM);
    878878
    879     if (    CPUMIsGuestInRealMode(pVCpu)
    880         ||  eflags.Bits.u1VM)
     879    if (    eflags.Bits.u1VM
     880        ||  CPUMIsGuestInRealMode(pVCpu))
    881881        return selmValidateAndConvertCSAddrRealMode(pVM, SelCS, pHiddenCSSel, Addr, ppvFlat);
    882882
     
    939939         * Deal with real & v86 mode first.
    940940         */
    941         if (    CPUMIsGuestInRealMode(pVCpu)
    942             ||  eflags.Bits.u1VM)
     941        if (    eflags.Bits.u1VM
     942            ||  CPUMIsGuestInRealMode(pVCpu))
    943943            return CPUMODE_16BIT;
    944944
     
    946946    }
    947947#endif /* !IN_RING0 */
    948     if (    CPUMIsGuestInLongMode(pVCpu)
    949         &&  pHiddenSel->Attr.n.u1Long)
     948    if (    pHiddenSel->Attr.n.u1Long
     949        &&  CPUMIsGuestInLongMode(pVCpu))
    950950        return CPUMODE_64BIT;
    951951
  • trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

    r25553 r25837  
    12951295# ifdef HWACCM_VMX_EMULATE_REALMODE
    12961296    /* Intercept all exceptions in real mode as none of them can be injected directly (#GP otherwise). */
    1297     if (    CPUMIsGuestInRealModeEx(pCtx) 
     1297    if (    CPUMIsGuestInRealModeEx(pCtx)
    12981298        &&  pVM->hwaccm.s.vmx.pRealModeTSS)
    12991299        u32TrapMask |= HWACCM_VMX_TRAP_MASK_REALMODE;
     
    23562356            Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
    23572357    }
    2358     fWasInLongMode = CPUMIsGuestInLongMode(pVCpu);
     2358    fWasInLongMode = CPUMIsGuestInLongModeEx(pCtx);
    23592359#endif
    23602360
     
    23752375    Assert(!HWACCMR0SuspendPending());
    23762376    /* Not allowed to switch modes without reloading the host state (32->64 switcher)!! */
    2377     Assert(fWasInLongMode == CPUMIsGuestInLongMode(pVCpu));
     2377    Assert(fWasInLongMode == CPUMIsGuestInLongModeEx(pCtx));
    23782378
    23792379    /* Safety precaution; looping for too long here can have a very bad effect on the host */
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