Changeset 25837 in vbox for trunk/src/VBox
- Timestamp:
- Jan 14, 2010 4:50:45 PM (15 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/PGMAllBth.h
r25835 r25837 1667 1667 && PGM_SHW_TYPE != PGM_TYPE_EPT 1668 1668 1669 # if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)1670 bool fNoExecuteBitValid = CPUMIsGuestNXEnabled(pVCpu);1671 # endif1672 1673 1669 /* 1674 1670 * Assert preconditions. … … 1767 1763 && (PdeSrc.n.u1Write == PdeDst.n.u1Write || !PdeDst.n.u1Write) 1768 1764 # if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE) 1769 && ( !fNoExecuteBitValid || PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)1765 && (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute || !CPUMIsGuestNXEnabled(pVCpu)) 1770 1766 # endif 1771 1767 ) … … 2131 2127 bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE); 2132 2128 # endif 2133 # if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)2134 bool fNoExecuteBitValid = CPUMIsGuestNXEnabled(pVCpu);2135 # endif2136 2129 unsigned uPageFaultLevel; 2137 2130 int rc; … … 2159 2152 if ( (uErr & X86_TRAP_PF_RSVD) 2160 2153 || !pPml4eSrc->n.u1Present 2161 || ( fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)2154 || ((uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute && CPUMIsGuestNXEnabled(pVCpu)) 2162 2155 || (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault || fWriteProtect)) 2163 2156 || (fUserLevelFault && !pPml4eSrc->n.u1User) … … 2179 2172 || !pPdpeSrc->n.u1Present 2180 2173 # if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */ 2181 || ( fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)2174 || ((uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute && CPUMIsGuestNXEnabled(pVCpu)) 2182 2175 || (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault || fWriteProtect)) 2183 2176 || (fUserLevelFault && !pPdpeSrc->lm.u1User) … … 2196 2189 || !pPdeSrc->n.u1Present 2197 2190 # if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE) 2198 || ( fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)2191 || ((uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute && CPUMIsGuestNXEnabled(pVCpu)) 2199 2192 # endif 2200 2193 || (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault || fWriteProtect)) … … 2292 2285 if ( !PteSrc.n.u1Present 2293 2286 # if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE) 2294 || ( fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)2287 || ((uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute && CPUMIsGuestNXEnabled(pVCpu)) 2295 2288 # endif 2296 2289 || (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault || fWriteProtect)) -
trunk/src/VBox/VMM/VMMAll/PGMAllGst.h
r25835 r25837 132 132 # if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE) 133 133 /* The NX bit is determined by a bitwise OR between the PT and PD */ 134 if ( CPUMIsGuestNXEnabled(pVCpu))135 *pfFlags |= (Pte.u & Pde.u & X86_PTE_PAE_NX);134 if ((Pte.u & Pde.u & X86_PTE_PAE_NX) && CPUMIsGuestNXEnabled(pVCpu)) /** @todo the code is ANDing not ORing NX like the comment says... */ 135 *pfFlags |= X86_PTE_PAE_NX; 136 136 # endif 137 137 } … … 149 149 | ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT); 150 150 # if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE) 151 /* The NX bit is determined by a bitwise OR between the PT and PD */ 152 if (CPUMIsGuestNXEnabled(pVCpu)) 153 *pfFlags |= (Pde.u & X86_PTE_PAE_NX); 151 if ((Pde.u & X86_PTE_PAE_NX) && CPUMIsGuestNXEnabled(pVCpu)) 152 *pfFlags |= X86_PTE_PAE_NX; 154 153 # endif 155 154 } -
trunk/src/VBox/VMM/VMMAll/PGMAllShw.h
r25835 r25837 251 251 # if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE) 252 252 /* The NX bit is determined by a bitwise OR between the PT and PD */ 253 if ( CPUMIsGuestNXEnabled(pVCpu))254 *pfFlags |= (Pte.u & Pde.u & X86_PTE_PAE_NX);253 if ((Pte.u & Pde.u & X86_PTE_PAE_NX) && CPUMIsGuestNXEnabled(pVCpu)) /** @todo the code is ANDing not ORing NX like the comment says... */ 254 *pfFlags |= X86_PTE_PAE_NX; 255 255 # endif 256 256 } -
trunk/src/VBox/VMM/VMMAll/SELMAll.cpp
r23303 r25837 98 98 * Deal with real & v86 mode first. 99 99 */ 100 if ( CPUMIsGuestInRealMode(pVCpu)101 || pCtxCore->eflags.Bits.u1VM)100 if ( pCtxCore->eflags.Bits.u1VM 101 || CPUMIsGuestInRealMode(pVCpu)) 102 102 { 103 103 RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff; … … 118 118 119 119 /* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0 (Intel® 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */ 120 if ( CPUMIsGuestInLongMode(pVCpu)121 && pCtxCore->csHid.Attr.n.u1Long)120 if ( pCtxCore->csHid.Attr.n.u1Long 121 && CPUMIsGuestInLongMode(pVCpu)) 122 122 { 123 123 switch (SelReg) … … 167 167 * Deal with real & v86 mode first. 168 168 */ 169 if ( CPUMIsGuestInRealMode(pVCpu)170 || pCtxCore->eflags.Bits.u1VM)169 if ( pCtxCore->eflags.Bits.u1VM 170 || CPUMIsGuestInRealMode(pVCpu)) 171 171 { 172 172 RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff; … … 201 201 202 202 /* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0 (Intel® 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */ 203 if ( CPUMIsGuestInLongMode(pVCpu)204 && pCtxCore->csHid.Attr.n.u1Long)203 if ( pCtxCore->csHid.Attr.n.u1Long 204 && CPUMIsGuestInLongMode(pVCpu)) 205 205 { 206 206 fCheckLimit = false; … … 473 473 * Deal with real & v86 mode first. 474 474 */ 475 if ( CPUMIsGuestInRealMode(pVCpu)476 || eflags.Bits.u1VM)475 if ( eflags.Bits.u1VM 476 || CPUMIsGuestInRealMode(pVCpu)) 477 477 { 478 478 RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff; … … 507 507 pvFlat = (RTGCPTR)(pHiddenSel->u64Base + (RTGCUINTPTR)Addr); 508 508 509 if ( ! CPUMIsGuestInLongMode(pVCpu)510 || ! pHiddenSel->Attr.n.u1Long)509 if ( !pHiddenSel->Attr.n.u1Long 510 || !CPUMIsGuestInLongMode(pVCpu)) 511 511 { 512 512 /* AMD64 manual: compatibility mode ignores the high 32 bits when calculating an effective address. */ … … 798 798 { 799 799 /* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0 (Intel® 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */ 800 if ( CPUMIsGuestInLongMode(pVCpu)801 && pHidCS->Attr.n.u1Long)800 if ( pHidCS->Attr.n.u1Long 801 && CPUMIsGuestInLongMode(pVCpu)) 802 802 { 803 803 *ppvFlat = Addr; … … 849 849 PVMCPU pVCpu = &pVM->aCpus[0]; 850 850 851 if ( CPUMIsGuestInRealMode(pVCpu)852 || eflags.Bits.u1VM)851 if ( eflags.Bits.u1VM 852 || CPUMIsGuestInRealMode(pVCpu)) 853 853 { 854 854 *pcBits = 16; … … 877 877 PVMCPU pVCpu = VMMGetCpu(pVM); 878 878 879 if ( CPUMIsGuestInRealMode(pVCpu)880 || eflags.Bits.u1VM)879 if ( eflags.Bits.u1VM 880 || CPUMIsGuestInRealMode(pVCpu)) 881 881 return selmValidateAndConvertCSAddrRealMode(pVM, SelCS, pHiddenCSSel, Addr, ppvFlat); 882 882 … … 939 939 * Deal with real & v86 mode first. 940 940 */ 941 if ( CPUMIsGuestInRealMode(pVCpu)942 || eflags.Bits.u1VM)941 if ( eflags.Bits.u1VM 942 || CPUMIsGuestInRealMode(pVCpu)) 943 943 return CPUMODE_16BIT; 944 944 … … 946 946 } 947 947 #endif /* !IN_RING0 */ 948 if ( CPUMIsGuestInLongMode(pVCpu)949 && pHiddenSel->Attr.n.u1Long)948 if ( pHiddenSel->Attr.n.u1Long 949 && CPUMIsGuestInLongMode(pVCpu)) 950 950 return CPUMODE_64BIT; 951 951 -
trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp
r25553 r25837 1295 1295 # ifdef HWACCM_VMX_EMULATE_REALMODE 1296 1296 /* Intercept all exceptions in real mode as none of them can be injected directly (#GP otherwise). */ 1297 if ( CPUMIsGuestInRealModeEx(pCtx) 1297 if ( CPUMIsGuestInRealModeEx(pCtx) 1298 1298 && pVM->hwaccm.s.vmx.pRealModeTSS) 1299 1299 u32TrapMask |= HWACCM_VMX_TRAP_MASK_REALMODE; … … 2356 2356 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n")); 2357 2357 } 2358 fWasInLongMode = CPUMIsGuestInLongMode (pVCpu);2358 fWasInLongMode = CPUMIsGuestInLongModeEx(pCtx); 2359 2359 #endif 2360 2360 … … 2375 2375 Assert(!HWACCMR0SuspendPending()); 2376 2376 /* Not allowed to switch modes without reloading the host state (32->64 switcher)!! */ 2377 Assert(fWasInLongMode == CPUMIsGuestInLongMode (pVCpu));2377 Assert(fWasInLongMode == CPUMIsGuestInLongModeEx(pCtx)); 2378 2378 2379 2379 /* Safety precaution; looping for too long here can have a very bad effect on the host */
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