VirtualBox

Changeset 26014 in vbox


Ignore:
Timestamp:
Jan 25, 2010 3:28:14 PM (15 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
56898
Message:

HWVMXR0.cpp: -Wshadow.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

    r25837 r26014  
    778778            if (iGate != X86_XCPT_DF)
    779779            {
    780                 RTGCUINTPTR intInfo;
    781 
    782                 intInfo  = (iGate == X86_XCPT_GP) ? (uint32_t)X86_XCPT_DF : iGate;
    783                 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
    784                 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
    785                 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
    786 
    787                 return VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0 /* no error code according to the Intel docs */);
     780                uint32_t intInfo2;
     781
     782                intInfo2  = (iGate == X86_XCPT_GP) ? (uint32_t)X86_XCPT_DF : iGate;
     783                intInfo2 |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
     784                intInfo2 |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
     785                intInfo2 |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
     786
     787                return VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo2, 0, 0 /* no error code according to the Intel docs */);
    788788            }
    789789            Log(("Triple fault -> reset the VM!\n"));
    … …  
    939939    {
    940940        uint8_t     u8Vector;
    941         int         rc;
    942941        TRPMEVENT   enmType;
    943942        RTGCUINTPTR intInfo;
    … …  
    23002299#ifdef VBOX_STRICT
    23012300    {
    2302         RTCCUINTREG val;
    2303 
    2304         rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
    2305         AssertRC(rc);
    2306         Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
     2301        RTCCUINTREG val2;
     2302
     2303        rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val2);
     2304        AssertRC(rc);
     2305        Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val2));
    23072306
    23082307        /* allowed zero */
    2309         if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
     2308        if ((val2 & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
    23102309            Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
    23112310
    23122311        /* allowed one */
    2313         if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
     2312        if ((val2 & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
    23142313            Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
    23152314
    2316         rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
    2317         AssertRC(rc);
    2318         Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
     2315        rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val2);
     2316        AssertRC(rc);
     2317        Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val2));
    23192318
    23202319        /* Must be set according to the MSR, but can be cleared in case of EPT. */
    23212320        if (pVM->hwaccm.s.fNestedPaging)
    2322             val |=   VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
    2323                    | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
    2324                    | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
     2321            val2 |=   VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
     2322                    | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
     2323                    | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
    23252324
    23262325        /* allowed zero */
    2327         if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
     2326        if ((val2 & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
    23282327            Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
    23292328
    23302329        /* allowed one */
    2331         if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
     2330        if ((val2 & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
    23322331            Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
    23332332
    2334         rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
    2335         AssertRC(rc);
    2336         Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
     2333        rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val2);
     2334        AssertRC(rc);
     2335        Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val2));
    23372336
    23382337        /* allowed zero */
    2339         if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
     2338        if ((val2 & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
    23402339            Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
    23412340
    23422341        /* allowed one */
    2343         if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
     2342        if ((val2 & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
    23442343            Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
    23452344
    2346         rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
    2347         AssertRC(rc);
    2348         Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
     2345        rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val2);
     2346        AssertRC(rc);
     2347        Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val2));
    23492348
    23502349        /* allowed zero */
    2351         if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
     2350        if ((val2 & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
    23522351            Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
    23532352
    23542353        /* allowed one */
    2355         if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
     2354        if ((val2 & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
    23562355            Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
    23572356    }
    23582357    fWasInLongMode = CPUMIsGuestInLongModeEx(pCtx);
    2359 #endif
     2358#endif /* VBOX_STRICT */
    23602359
    23612360#ifdef VBOX_WITH_CRASHDUMP_MAGIC
    … …  
    24862485        bool    fPending;
    24872486
    2488         int rc = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
    2489         AssertRC(rc);
     2487        int rc2 = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
     2488        AssertRC(rc2);
    24902489        /* The TPR can be found at offset 0x80 in the APIC mmio page. */
    24912490        pVCpu->hwaccm.s.vmx.pVAPIC[0x80] = u8LastTPR;
    … …  
    31983197                    case OP_INT:
    31993198                    {
    3200                         RTGCUINTPTR intInfo;
     3199                        uint32_t intInfo2;
    32013200
    32023201                        LogFlow(("Realmode: INT %x\n", pDis->param1.parval & 0xff));
    3203                         intInfo  = pDis->param1.parval & 0xff;
    3204                         intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
    3205                         intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
    3206 
    3207                         rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
     3202                        intInfo2  = pDis->param1.parval & 0xff;
     3203                        intInfo2 |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
     3204                        intInfo2 |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
     3205
     3206                        rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo2, cbOp, 0);
    32083207                        AssertRC(rc);
    32093208                        fUpdateRIP = false;
    … …  
    32163215                        if (pCtx->eflags.Bits.u1OF)
    32173216                        {
    3218                             RTGCUINTPTR intInfo;
     3217                            uint32_t intInfo2;
    32193218
    32203219                            LogFlow(("Realmode: INTO\n"));
    3221                             intInfo  = X86_XCPT_OF;
    3222                             intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
    3223                             intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
    3224 
    3225                             rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
     3220                            intInfo2  = X86_XCPT_OF;
     3221                            intInfo2 |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
     3222                            intInfo2 |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
     3223
     3224                            rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo2, cbOp, 0);
    32263225                            AssertRC(rc);
    32273226                            fUpdateRIP = false;
    … …  
    32333232                    case OP_INT3:
    32343233                    {
    3235                         RTGCUINTPTR intInfo;
     3234                        uint32_t intInfo2;
    32363235
    32373236                        LogFlow(("Realmode: INT 3\n"));
    3238                         intInfo  = 3;
    3239                         intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
    3240                         intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
    3241 
    3242                         rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
     3237                        intInfo2  = 3;
     3238                        intInfo2 |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
     3239                        intInfo2 |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
     3240
     3241                        rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo2, cbOp, 0);
    32433242                        AssertRC(rc);
    32443243                        fUpdateRIP = false;
    … …  
    40414040    {
    40424041#ifdef VBOX_STRICT
    4043         RTCCUINTREG val = 0;
     4042        RTCCUINTREG val2 = 0;
    40444043
    40454044        Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
    40464045
    4047         VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
    4048         Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
    4049 
    4050         VMXReadVMCS(VMX_VMCS64_GUEST_CR0, &val);
    4051         Log(("VMX_VMCS_GUEST_CR0        %RX64\n", (uint64_t)val));
    4052 
    4053         VMXReadVMCS(VMX_VMCS64_GUEST_CR3, &val);
    4054         Log(("VMX_VMCS_GUEST_CR3        %RX64\n", (uint64_t)val));
    4055 
    4056         VMXReadVMCS(VMX_VMCS64_GUEST_CR4, &val);
    4057         Log(("VMX_VMCS_GUEST_CR4        %RX64\n", (uint64_t)val));
    4058 
    4059         VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
    4060         Log(("VMX_VMCS_GUEST_RFLAGS     %08x\n", val));
     4046        VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val2);
     4047        Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val2));
     4048
     4049        VMXReadVMCS(VMX_VMCS64_GUEST_CR0, &val2);
     4050        Log(("VMX_VMCS_GUEST_CR0        %RX64\n", (uint64_t)val2));
     4051
     4052        VMXReadVMCS(VMX_VMCS64_GUEST_CR3, &val2);
     4053        Log(("VMX_VMCS_GUEST_CR3        %RX64\n", (uint64_t)val2));
     4054
     4055        VMXReadVMCS(VMX_VMCS64_GUEST_CR4, &val2);
     4056        Log(("VMX_VMCS_GUEST_CR4        %RX64\n", (uint64_t)val2));
     4057
     4058        VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val2);
     4059        Log(("VMX_VMCS_GUEST_RFLAGS     %08x\n", val2));
    40614060
    40624061        VMX_LOG_SELREG(CS, "CS");
    … …  
    40694068        VMX_LOG_SELREG(LDTR, "LDTR");
    40704069
    4071         VMXReadVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
    4072         Log(("VMX_VMCS_GUEST_GDTR_BASE    %RX64\n", (uint64_t)val));
    4073         VMXReadVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
    4074         Log(("VMX_VMCS_GUEST_IDTR_BASE    %RX64\n", (uint64_t)val));
     4070        VMXReadVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val2);
     4071        Log(("VMX_VMCS_GUEST_GDTR_BASE    %RX64\n", (uint64_t)val2));
     4072        VMXReadVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val2);
     4073        Log(("VMX_VMCS_GUEST_IDTR_BASE    %RX64\n", (uint64_t)val2));
    40754074#endif /* VBOX_STRICT */
    40764075        rc = VERR_VMX_INVALID_GUEST_STATE;
    … …  
    43354334    case VERR_VMX_UNABLE_TO_RESUME_VM:
    43364335    {
    4337         int         rc;
     4336        int         rc2;
    43384337        RTCCUINTREG exitReason, instrError;
    43394338
    4340         rc  = VMXReadVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
    4341         rc |= VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
    4342         AssertRC(rc);
    4343         if (rc == VINF_SUCCESS)
     4339        rc2  = VMXReadVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
     4340        rc2 |= VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
     4341        AssertRC(rc2);
     4342        if (rc2 == VINF_SUCCESS)
    43444343        {
    43454344            Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
    4346             Log(("Current stack %08x\n", &rc));
     4345            Log(("Current stack %08x\n", &rc2));
    43474346
    43484347            pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
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