Changeset 26883 in vbox for trunk/src

Timestamp:

Feb 27, 2010 3:58:25 PM (15 years ago)

Author:

vboxsync

Message:

MADT, MPTABLES: implemented correct description of IRQ routing in dual PIC config we emulate - Snow Leo now works

Location:

trunk/src/VBox/Devices/PC

Files:

• DevACPI.cpp (modified) (10 diffs)
• DevFwCommon.cpp (modified) (5 diffs)

trunk/src/VBox/Devices/PC/DevACPI.cpp

@@ -476 +476 @@
 AssertCompileSize(ACPITBLIOAPIC, 12);
 
+/** Interrupt Source Override Structure */
+struct ACPITBLISO
+{
+    uint8_t             u8Type;                 /**< 2 ==  Interrupt Source Override*/
+    uint8_t             u8Length;               /**< 10 */
+    uint8_t             u8Bus;                  /**< Bus */
+    uint8_t             u8Source;               /**< Bus-relative interrupt source (IRQ) */
+    uint32_t            u32GSI;                 /**< Global System Interrupt */
+    uint16_t            u16Flags;               /**< MPS INTI flags Global */
+};
+AssertCompileSize(ACPITBLISO, 10);
+#define NUMBER_OF_IRQ_SOURCE_OVERRIDES 1
 
 /** HPET Descriptor Structure */
@@ -519 +531 @@
     uint32_t            m_cCpus;
 
+    /**
+     * Number of interrupt overrides.
+     */
+     uint32_t            m_cIsos;
+
 public:
     /**
@@ -546 +563 @@
 
     /**
+     * Address of ISO description
+     */
+    inline ACPITBLISO *ISO_addr(void) const
+    {
+        return (ACPITBLISO *)(u32Flags_addr() + 1);
+    }
+
+    /**
      * Address of per-CPU LAPIC descriptions
      */
     inline ACPITBLLAPIC *LApics_addr(void) const
     {
-        return (ACPITBLLAPIC *)(u32Flags_addr() + 1);
+        return (ACPITBLLAPIC *)(ISO_addr() + m_cIsos);
     }
 
@@ -581 +606 @@
      * Size of MADT for given ACPI config, useful to compute layout.
      */
-    static uint32_t sizeFor(ACPIState *s)
-    {
-        return AcpiTableMADT(s->cCpus).size();
+    static uint32_t sizeFor(ACPIState *s, uint32_t cIsos)
+    {
+        return AcpiTableMADT(s->cCpus, cIsos).size();
     }
 
@@ -589 +614 @@
      * Constructor, only works in Ring 3, doesn't look like a big deal.
      */
-    AcpiTableMADT(uint32_t cCpus)
+    AcpiTableMADT(uint32_t cCpus, uint32_t cIsos)
     {
         m_cCpus  = cCpus;
+        m_cIsos  = cIsos;
         m_pbData = NULL;                /* size() uses this and gcc will complain if not initilized. */
         uint32_t cb = size();
@@ -875 +901 @@
 {
     uint16_t cpus = s->cCpus;
-    AcpiTableMADT madt(cpus);
+    AcpiTableMADT madt(cpus, 1 /* one source override */ );
 
     acpiPrepareHeader(madt.header_addr(), "APIC", madt.size(), 2);
@@ -882 +908 @@
     *madt.u32Flags_addr()          = RT_H2LE_U32(PCAT_COMPAT);
 
+    /* LAPICs records */
     ACPITBLLAPIC* lapic = madt.LApics_addr();
     for (uint16_t i = 0; i < cpus; i++)
@@ -888 +915 @@
         lapic->u8Length    = sizeof(ACPITBLLAPIC);
         lapic->u8ProcId    = i;
+        /** Must match numbering convention in MPTABLES */
         lapic->u8ApicId    = i;
         lapic->u32Flags    = VMCPUSET_IS_PRESENT(&s->CpuSetAttached, i) ? RT_H2LE_U32(LAPIC_ENABLED) : 0;
@@ -893 +921 @@
     }
 
+    /* IO-APIC record */
     ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
-
     ioapic->u8Type     = 1;
     ioapic->u8Length   = sizeof(ACPITBLIOAPIC);
-    /** @todo is this the right id? */
+    /** Must match MP tables ID */
     ioapic->u8IOApicId = cpus;
     ioapic->u8Reserved = 0;
     ioapic->u32Address = RT_H2LE_U32(0xfec00000);
     ioapic->u32GSIB    = RT_H2LE_U32(0);
+
+    /* Interrupt Source Overrides */
+    ACPITBLISO* isos = madt.ISO_addr();
+    isos[0].u8Type     = 2;
+    isos[0].u8Length   = sizeof(ACPITBLISO);
+    isos[0].u8Bus      = 0; /* Must be 0 */
+    isos[0].u8Source   = 0; /* IRQ0 */
+    isos[0].u32GSI     = 2; /* connected to pin 2 */
+    isos[0].u16Flags   = 0; /* conform to the bus */
+    Assert(NUMBER_OF_IRQ_SOURCE_OVERRIDES == 1);
 
     madt.header_addr()->u8Checksum = acpiChecksum(madt.data(), madt.size());
@@ -2044 +2082 @@
     {
         GCPhysApic = GCPhysCur;
-        GCPhysCur = RT_ALIGN_32(GCPhysCur + AcpiTableMADT::sizeFor(s), 16);
+        GCPhysCur = RT_ALIGN_32(GCPhysCur + AcpiTableMADT::sizeFor(s, NUMBER_OF_IRQ_SOURCE_OVERRIDES), 16);
     }
     if (s->fUseHpet)

trunk/src/VBox/Devices/PC/DevFwCommon.cpp

@@ -232 +232 @@
     uint32_t        u32AddrLocalApic;
     uint16_t        u16ExtTableLength;
-    uint8_t         u8ExtTableChecksxum;
+    uint8_t         u8ExtTableChecksum;
     uint8_t         u8Reserved;
 } *PMPSCFGTBLHEADER;
@@ -733 +733 @@
     pCfgTab->u16EntryCount         =  cCpus /* Processors */
                                    +  1 /* ISA Bus */
+                                   +  1 /* PCI Bus */
                                    +  1 /* I/O-APIC */
-                                   + 16 /* Interrupts */;
+                                   + 16 /* Interrupts */
+                                   +  1 /* Local interrupts */;
     pCfgTab->u32AddrLocalApic      = 0xfee00000;
     pCfgTab->u16ExtTableLength     =  0;
-    pCfgTab->u8ExtTableChecksxum   =  0;
+    pCfgTab->u8ExtTableChecksum    =  0;
     pCfgTab->u8Reserved            =  0;
 
@@ -757 +759 @@
     {
         pProcEntry->u8EntryType        = 0; /* processor entry */
-        pProcEntry->u8LocalApicId      = i;
-        pProcEntry->u8LocalApicVersion = 0x11;
+        pProcEntry->u8LocalApicId      = i + 1;
+        pProcEntry->u8LocalApicVersion = 0x14;
         pProcEntry->u8CPUFlags         = (i == 0 ? 2 /* bootstrap processor */ : 0 /* application processor */) | 1 /* enabled */;
         pProcEntry->u32CPUSignature    = u32CPUSignature;
@@ -767 +769 @@
     }
 
+    uint32_t iBusIdPci0 = 0;
+    uint32_t iBusIdIsa  = 1;
+
     /* ISA bus */
     PMPSBUSENTRY pBusEntry         = (PMPSBUSENTRY)pProcEntry;
     pBusEntry->u8EntryType         = 1; /* bus entry */
-    pBusEntry->u8BusId             = 0; /* this ID is referenced by the interrupt entries */
+    pBusEntry->u8BusId             = iBusIdIsa; /* this ID is referenced by the interrupt entries */
     memcpy(pBusEntry->au8BusTypeStr, "ISA   ", 6);
-
-    /* PCI bus? */
+    pBusEntry++;
+
+    /* PCI bus */
+    pBusEntry->u8EntryType         = 1; /* bus entry */
+    pBusEntry->u8BusId             = iBusIdPci0; /* this ID can be referenced by the interrupt entries */
+    memcpy(pBusEntry->au8BusTypeStr, "PCI   ", 6);
+
 
     /* I/O-APIC.
@@ -779 +789 @@
      *           ... At least one I/O APIC must be enabled." */
     PMPSIOAPICENTRY pIOAPICEntry   = (PMPSIOAPICENTRY)(pBusEntry+1);
-    uint16_t apicId = cCpus;
+    uint16_t iApicId = 0;
     pIOAPICEntry->u8EntryType      = 2; /* I/O-APIC entry */
-    pIOAPICEntry->u8Id             = apicId; /* this ID is referenced by the interrupt entries */
+    pIOAPICEntry->u8Id             = iApicId; /* this ID is referenced by the interrupt entries */
     pIOAPICEntry->u8Version        = 0x11;
     pIOAPICEntry->u8Flags          = 1 /* enable */;
     pIOAPICEntry->u32Addr          = 0xfec00000;
 
+    /* Interrupt tables */
+    /* Bus vectors */
     PMPSIOIRQENTRY pIrqEntry       = (PMPSIOIRQENTRY)(pIOAPICEntry+1);
-    for (int i = 0; i < 16; i++, pIrqEntry++)
+    for (int iPin = 0; iPin < 16; iPin++, pIrqEntry++)
     {
         pIrqEntry->u8EntryType     = 3; /* I/O interrupt entry */
-        pIrqEntry->u8Type          = 0; /* INT, vectored interrupt */
-        pIrqEntry->u16Flags        = 0; /* polarity of APIC I/O input signal = conforms to bus,
-                                           trigger mode = conforms to bus */
-        pIrqEntry->u8SrcBusId      = 0; /* ISA bus */
-        pIrqEntry->u8SrcBusIrq     = i;
-        pIrqEntry->u8DstIOAPICId   = apicId;
-        pIrqEntry->u8DstIOAPICInt  = i;
-    }
+        /*
+         * 0 - INT, vectored interrupt,
+         * 3 - ExtINT, vectored interrupt provided by PIC
+         * As we emulate system with both APIC and PIC, it's needed for their coexistence.
+         */
+        pIrqEntry->u8Type          = (iPin == 0) ? 3 : 0;
+        pIrqEntry->u16Flags        = 0;              /* polarity of APIC I/O input signal = conforms to bus,
+                                                        trigger mode = conforms to bus */
+        pIrqEntry->u8SrcBusId      = iBusIdIsa;      /* ISA bus */
+        /* IRQ0 mapped to pin 2, other are identity mapped */
+        pIrqEntry->u8SrcBusIrq     = (iPin == 2) ? 0 : iPin; /* IRQ on the bus */
+        pIrqEntry->u8DstIOAPICId   = iApicId;        /* destintion IO-APIC */
+        pIrqEntry->u8DstIOAPICInt  = iPin;           /* pin on destination IO-APIC */
+    }
+    /* Local delivery */
+    pIrqEntry->u8EntryType     = 4; /* Local interrupt entry */
+    pIrqEntry->u8Type          = 3; /* ExtINT */
+    pIrqEntry->u16Flags        = (1 << 2) | 1; /* active-high, edge-triggered */
+    pIrqEntry->u8SrcBusId      = iBusIdIsa;
+    pIrqEntry->u8SrcBusIrq     = 0;
+    pIrqEntry->u8DstIOAPICId   = 0xff;
+    pIrqEntry->u8DstIOAPICInt  = 0;
+    pIrqEntry++;
 
     pCfgTab->u16Length             = (uint8_t*)pIrqEntry - pTable;