Changeset 26913 in vbox for trunk/src/VBox/Devices/PC
- Timestamp:
- Mar 1, 2010 1:57:49 PM (15 years ago)
- svn:sync-xref-src-repo-rev:
- 58197
- Location:
- trunk/src/VBox/Devices/PC
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/PC/DevACPI.cpp
r26883 r26913 476 476 AssertCompileSize(ACPITBLIOAPIC, 12); 477 477 478 /** Interrupt Source Override Structure */479 struct ACPITBLISO480 {481 uint8_t u8Type; /**< 2 == Interrupt Source Override*/482 uint8_t u8Length; /**< 10 */483 uint8_t u8Bus; /**< Bus */484 uint8_t u8Source; /**< Bus-relative interrupt source (IRQ) */485 uint32_t u32GSI; /**< Global System Interrupt */486 uint16_t u16Flags; /**< MPS INTI flags Global */487 };488 AssertCompileSize(ACPITBLISO, 10);489 #define NUMBER_OF_IRQ_SOURCE_OVERRIDES 1490 478 491 479 /** HPET Descriptor Structure */ … … 531 519 uint32_t m_cCpus; 532 520 533 /**534 * Number of interrupt overrides.535 */536 uint32_t m_cIsos;537 538 521 public: 539 522 /** … … 563 546 564 547 /** 565 * Address of ISO description566 */567 inline ACPITBLISO *ISO_addr(void) const568 {569 return (ACPITBLISO *)(u32Flags_addr() + 1);570 }571 572 /**573 548 * Address of per-CPU LAPIC descriptions 574 549 */ 575 550 inline ACPITBLLAPIC *LApics_addr(void) const 576 551 { 577 return (ACPITBLLAPIC *)( ISO_addr() + m_cIsos);552 return (ACPITBLLAPIC *)(u32Flags_addr() + 1); 578 553 } 579 554 … … 606 581 * Size of MADT for given ACPI config, useful to compute layout. 607 582 */ 608 static uint32_t sizeFor(ACPIState *s , uint32_t cIsos)609 { 610 return AcpiTableMADT(s->cCpus , cIsos).size();583 static uint32_t sizeFor(ACPIState *s) 584 { 585 return AcpiTableMADT(s->cCpus).size(); 611 586 } 612 587 … … 614 589 * Constructor, only works in Ring 3, doesn't look like a big deal. 615 590 */ 616 AcpiTableMADT(uint32_t cCpus , uint32_t cIsos)591 AcpiTableMADT(uint32_t cCpus) 617 592 { 618 593 m_cCpus = cCpus; 619 m_cIsos = cIsos;620 594 m_pbData = NULL; /* size() uses this and gcc will complain if not initilized. */ 621 595 uint32_t cb = size(); … … 901 875 { 902 876 uint16_t cpus = s->cCpus; 903 AcpiTableMADT madt(cpus , 1 /* one source override */);877 AcpiTableMADT madt(cpus); 904 878 905 879 acpiPrepareHeader(madt.header_addr(), "APIC", madt.size(), 2); … … 908 882 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT); 909 883 910 /* LAPICs records */911 884 ACPITBLLAPIC* lapic = madt.LApics_addr(); 912 885 for (uint16_t i = 0; i < cpus; i++) … … 915 888 lapic->u8Length = sizeof(ACPITBLLAPIC); 916 889 lapic->u8ProcId = i; 917 /** Must match numbering convention in MPTABLES */918 890 lapic->u8ApicId = i; 919 891 lapic->u32Flags = VMCPUSET_IS_PRESENT(&s->CpuSetAttached, i) ? RT_H2LE_U32(LAPIC_ENABLED) : 0; … … 921 893 } 922 894 923 /* IO-APIC record */924 895 ACPITBLIOAPIC* ioapic = madt.IOApic_addr(); 896 925 897 ioapic->u8Type = 1; 926 898 ioapic->u8Length = sizeof(ACPITBLIOAPIC); 927 /** Must match MP tables ID*/899 /** @todo is this the right id? */ 928 900 ioapic->u8IOApicId = cpus; 929 901 ioapic->u8Reserved = 0; 930 902 ioapic->u32Address = RT_H2LE_U32(0xfec00000); 931 903 ioapic->u32GSIB = RT_H2LE_U32(0); 932 933 /* Interrupt Source Overrides */934 ACPITBLISO* isos = madt.ISO_addr();935 isos[0].u8Type = 2;936 isos[0].u8Length = sizeof(ACPITBLISO);937 isos[0].u8Bus = 0; /* Must be 0 */938 isos[0].u8Source = 0; /* IRQ0 */939 isos[0].u32GSI = 2; /* connected to pin 2 */940 isos[0].u16Flags = 0; /* conform to the bus */941 Assert(NUMBER_OF_IRQ_SOURCE_OVERRIDES == 1);942 904 943 905 madt.header_addr()->u8Checksum = acpiChecksum(madt.data(), madt.size()); … … 2082 2044 { 2083 2045 GCPhysApic = GCPhysCur; 2084 GCPhysCur = RT_ALIGN_32(GCPhysCur + AcpiTableMADT::sizeFor(s , NUMBER_OF_IRQ_SOURCE_OVERRIDES), 16);2046 GCPhysCur = RT_ALIGN_32(GCPhysCur + AcpiTableMADT::sizeFor(s), 16); 2085 2047 } 2086 2048 if (s->fUseHpet) -
trunk/src/VBox/Devices/PC/DevFwCommon.cpp
r26883 r26913 232 232 uint32_t u32AddrLocalApic; 233 233 uint16_t u16ExtTableLength; 234 uint8_t u8ExtTableChecks um;234 uint8_t u8ExtTableChecksxum; 235 235 uint8_t u8Reserved; 236 236 } *PMPSCFGTBLHEADER; … … 733 733 pCfgTab->u16EntryCount = cCpus /* Processors */ 734 734 + 1 /* ISA Bus */ 735 + 1 /* PCI Bus */736 735 + 1 /* I/O-APIC */ 737 + 16 /* Interrupts */ 738 + 1 /* Local interrupts */; 736 + 16 /* Interrupts */; 739 737 pCfgTab->u32AddrLocalApic = 0xfee00000; 740 738 pCfgTab->u16ExtTableLength = 0; 741 pCfgTab->u8ExtTableChecks um= 0;739 pCfgTab->u8ExtTableChecksxum = 0; 742 740 pCfgTab->u8Reserved = 0; 743 741 … … 759 757 { 760 758 pProcEntry->u8EntryType = 0; /* processor entry */ 761 pProcEntry->u8LocalApicId = i + 1;762 pProcEntry->u8LocalApicVersion = 0x1 4;759 pProcEntry->u8LocalApicId = i; 760 pProcEntry->u8LocalApicVersion = 0x11; 763 761 pProcEntry->u8CPUFlags = (i == 0 ? 2 /* bootstrap processor */ : 0 /* application processor */) | 1 /* enabled */; 764 762 pProcEntry->u32CPUSignature = u32CPUSignature; … … 769 767 } 770 768 771 uint32_t iBusIdPci0 = 0;772 uint32_t iBusIdIsa = 1;773 774 769 /* ISA bus */ 775 770 PMPSBUSENTRY pBusEntry = (PMPSBUSENTRY)pProcEntry; 776 771 pBusEntry->u8EntryType = 1; /* bus entry */ 777 pBusEntry->u8BusId = iBusIdIsa; /* this ID is referenced by the interrupt entries */772 pBusEntry->u8BusId = 0; /* this ID is referenced by the interrupt entries */ 778 773 memcpy(pBusEntry->au8BusTypeStr, "ISA ", 6); 779 pBusEntry++; 780 781 /* PCI bus */ 782 pBusEntry->u8EntryType = 1; /* bus entry */ 783 pBusEntry->u8BusId = iBusIdPci0; /* this ID can be referenced by the interrupt entries */ 784 memcpy(pBusEntry->au8BusTypeStr, "PCI ", 6); 785 774 775 /* PCI bus? */ 786 776 787 777 /* I/O-APIC. … … 789 779 * ... At least one I/O APIC must be enabled." */ 790 780 PMPSIOAPICENTRY pIOAPICEntry = (PMPSIOAPICENTRY)(pBusEntry+1); 791 uint16_t iApicId = 0;781 uint16_t apicId = cCpus; 792 782 pIOAPICEntry->u8EntryType = 2; /* I/O-APIC entry */ 793 pIOAPICEntry->u8Id = iApicId; /* this ID is referenced by the interrupt entries */783 pIOAPICEntry->u8Id = apicId; /* this ID is referenced by the interrupt entries */ 794 784 pIOAPICEntry->u8Version = 0x11; 795 785 pIOAPICEntry->u8Flags = 1 /* enable */; 796 786 pIOAPICEntry->u32Addr = 0xfec00000; 797 787 798 /* Interrupt tables */799 /* Bus vectors */800 788 PMPSIOIRQENTRY pIrqEntry = (PMPSIOIRQENTRY)(pIOAPICEntry+1); 801 for (int i Pin = 0; iPin < 16; iPin++, pIrqEntry++)789 for (int i = 0; i < 16; i++, pIrqEntry++) 802 790 { 803 791 pIrqEntry->u8EntryType = 3; /* I/O interrupt entry */ 804 /* 805 * 0 - INT, vectored interrupt, 806 * 3 - ExtINT, vectored interrupt provided by PIC 807 * As we emulate system with both APIC and PIC, it's needed for their coexistence. 808 */ 809 pIrqEntry->u8Type = (iPin == 0) ? 3 : 0; 810 pIrqEntry->u16Flags = 0; /* polarity of APIC I/O input signal = conforms to bus, 811 trigger mode = conforms to bus */ 812 pIrqEntry->u8SrcBusId = iBusIdIsa; /* ISA bus */ 813 /* IRQ0 mapped to pin 2, other are identity mapped */ 814 pIrqEntry->u8SrcBusIrq = (iPin == 2) ? 0 : iPin; /* IRQ on the bus */ 815 pIrqEntry->u8DstIOAPICId = iApicId; /* destintion IO-APIC */ 816 pIrqEntry->u8DstIOAPICInt = iPin; /* pin on destination IO-APIC */ 817 } 818 /* Local delivery */ 819 pIrqEntry->u8EntryType = 4; /* Local interrupt entry */ 820 pIrqEntry->u8Type = 3; /* ExtINT */ 821 pIrqEntry->u16Flags = (1 << 2) | 1; /* active-high, edge-triggered */ 822 pIrqEntry->u8SrcBusId = iBusIdIsa; 823 pIrqEntry->u8SrcBusIrq = 0; 824 pIrqEntry->u8DstIOAPICId = 0xff; 825 pIrqEntry->u8DstIOAPICInt = 0; 826 pIrqEntry++; 792 pIrqEntry->u8Type = 0; /* INT, vectored interrupt */ 793 pIrqEntry->u16Flags = 0; /* polarity of APIC I/O input signal = conforms to bus, 794 trigger mode = conforms to bus */ 795 pIrqEntry->u8SrcBusId = 0; /* ISA bus */ 796 pIrqEntry->u8SrcBusIrq = i; 797 pIrqEntry->u8DstIOAPICId = apicId; 798 pIrqEntry->u8DstIOAPICInt = i; 799 } 827 800 828 801 pCfgTab->u16Length = (uint8_t*)pIrqEntry - pTable;
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