Changeset 27226 in vbox

Timestamp:

Mar 9, 2010 5:33:16 PM (15 years ago)

Author:

vboxsync

Message:

HPET: minor issues related to egde vs. level triggered interrupts

File:

• trunk/src/VBox/Devices/PC/DevHPET.cpp (modified) (6 diffs)

trunk/src/VBox/Devices/PC/DevHPET.cpp

@@ -37 +37 @@
  *     schedule interrupt earlier than in 1ms
  *   - statistics not implemented
+ *   - level-triggered mode not implemented
  */
 /*
@@ -87 +88 @@
 #define HPET_CFG_WRITE_MASK      0x3
 
-#define HPET_TN_ENABLE           0x004
-#define HPET_TN_PERIODIC         0x008
-#define HPET_TN_PERIODIC_CAP     0x010
-#define HPET_TN_SIZE_CAP         0x020
-#define HPET_TN_SETVAL           0x040
-#define HPET_TN_32BIT            0x100
-#define HPET_TN_INT_ROUTE_MASK   0x3e00
-#define HPET_TN_CFG_WRITE_MASK   0x3f4e
-#define HPET_TN_INT_ROUTE_SHIFT      9
-#define HPET_TN_INT_ROUTE_CAP_SHIFT 32
+#define HPET_TN_INT_TYPE                      (1 << 1)
+#define HPET_TN_ENABLE                        (1 << 2)
+#define HPET_TN_PERIODIC                      (1 << 3)
+#define HPET_TN_PERIODIC_CAP                  (1 << 4)
+#define HPET_TN_SIZE_CAP                      (1 << 5)
+#define HPET_TN_SETVAL                        (1 << 6)
+#define HPET_TN_32BIT                         (1 << 8)
+#define HPET_TN_INT_ROUTE_MASK                0x3e00
+#define HPET_TN_CFG_WRITE_MASK                0x3f4e
+#define HPET_TN_INT_ROUTE_SHIFT               9
+#define HPET_TN_INT_ROUTE_CAP_SHIFT           32
 #define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U
 
@@ -359 +361 @@
      *        PIT and RTC
      */
-    /*
-     * nike: Linux refuses to boot with HPET, claiming that 8259 timer not
-     * connected to IO-APIC, if we use IRQ2, so let's use IRQ0 for now.
-     */
     if ((pTimer->u8TimerNumber <= 1) &&
         (pTimer->CTX_SUFF(pHpet)->u64Config & HPET_CFG_LEGACY))
@@ -488 +486 @@
         {
             Log(("write HPET_TN_CFG: %d\n", iTimerNo));
+            if (iNewValue & HPET_TN_32BIT)
+            {
+                pTimer->u64Cmp = (uint32_t)pTimer->u64Cmp;
+                pTimer->u64Period = (uint32_t)pTimer->u64Period;
+            }
+            if ((iNewValue & HPET_TN_INT_TYPE) == HPET_TIMER_TYPE_LEVEL) 
+            {
+                LogRel(("level-triggered config not yet supported\n"));
+                Assert(false);
+            }
             /** We only care about lower 32-bits so far */
             pTimer->u64Config =
                     updateMasked(iNewValue, iOldValue, HPET_TN_CFG_WRITE_MASK);
-            if (iNewValue & HPET_TN_32BIT)
-            {
-                pTimer->u64Cmp = (uint32_t)pTimer->u64Cmp;
-                pTimer->u64Period = (uint32_t)pTimer->u64Period;
-            }
-            if (iNewValue & HPET_TIMER_TYPE_LEVEL)
-            {
-                LogRel(("level-triggered config not yet supported\n"));
-                Assert(false);
-            }
             break;
         }
@@ -984 +982 @@
     {
         Log4(("HPET: raising IRQ %d\n", irq));
-        if ((pTimer->u64Config & HPET_TIMER_TYPE_LEVEL) == 0)
-        {
+
+        /* ISR bits are only set in level-triggered mode */
+        if ((pTimer->u64Config & HPET_TN_INT_TYPE) == HPET_TIMER_TYPE_LEVEL)
             pThis->u64Isr |= (uint64_t)(1 << pTimer->u8TimerNumber);
+
+        /* We trigger flip/flop in edge-triggered mode and do nothing in level-triggered mode yet */
+        if ((pTimer->u64Config & HPET_TN_INT_TYPE) == HPET_TIMER_TYPE_EDGE)
             pThis->pHpetHlpR3->pfnSetIrq(pThis->CTX_SUFF(pDevIns), irq, PDM_IRQ_LEVEL_FLIP_FLOP);
-        }
+        /* @todo: implement IRQs in level-triggered mode */
     }
 }
@@ -1203 +1205 @@
 
     /* Query configuration. */
-#if 1
+#if 0
     rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fRCEnabled, true);
     if (RT_FAILURE(rc))