- Timestamp:
- Mar 10, 2010 3:03:11 PM (15 years ago)
- svn:sync-xref-src-repo-rev:
- 58644
- Location:
- trunk/src
- Files:
-
- 6 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/PC/DevHPET.cpp
r27229 r27254 355 355 * timer 0: IRQ0 for PIC and IRQ2 for APIC 356 356 * timer 1: IRQ8 for both PIC and APIC 357 * As primary usecase for HPET is APIC config, we pretend 358 * being always APIC, although for safety we shall check currect IC. 359 * @todo: implement private interface between HPET and PDM 360 * to allow figuring that out and enabling/disabling 361 * PIT and RTC 357 * 358 * ISA IRQ delivery logic will take care of correct delivery 359 * to the different ICs. 362 360 */ 363 361 if ((pTimer->u8TimerNumber <= 1) && 364 362 (pTimer->CTX_SUFF(pHpet)->u64Config & HPET_CFG_LEGACY)) 365 return (pTimer->u8TimerNumber == 0) ? 2: 8;363 return (pTimer->u8TimerNumber == 0) ? 0 : 8; 366 364 else 367 365 return (pTimer->u64Config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT; … … 974 972 static void irqUpdate(struct HpetTimer *pTimer) 975 973 { 976 uint32_t irq 974 uint32_t irq = getTimerIrq(pTimer); 977 975 HpetState* pThis = pTimer->CTX_SUFF(pHpet); 978 976 … … 990 988 if ((pTimer->u64Config & HPET_TN_INT_TYPE) == HPET_TIMER_TYPE_EDGE) 991 989 pThis->pHpetHlpR3->pfnSetIrq(pThis->CTX_SUFF(pDevIns), irq, PDM_IRQ_LEVEL_FLIP_FLOP); 990 else 991 Assert(false); 992 992 /* @todo: implement IRQs in level-triggered mode */ 993 993 } -
trunk/src/VBox/VMM/PDMDevHlp.cpp
r26939 r27254 1306 1306 1307 1307 PVM pVM = pDevIns->Internal.s.pVMR3; 1308 PDMIsaSetIrq(pVM, iIrq, iLevel , true); /* (The API takes the lock.) */1308 PDMIsaSetIrq(pVM, iIrq, iLevel); /* (The API takes the lock.) */ 1309 1309 1310 1310 LogFlow(("pdmR3DevHlp_ISASetIrq: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance)); … … 3167 3167 { 3168 3168 case PDMDEVHLPTASKOP_ISA_SET_IRQ: 3169 PDMIsaSetIrq(pVM, pTask->u.SetIRQ.iIrq, pTask->u.SetIRQ.iLevel , true /* ISA source */);3169 PDMIsaSetIrq(pVM, pTask->u.SetIRQ.iIrq, pTask->u.SetIRQ.iLevel); 3170 3170 break; 3171 3171 -
trunk/src/VBox/VMM/PDMDevMiscHlp.cpp
r27127 r27254 459 459 PDMDEV_ASSERT_DEVINS(pDevIns); 460 460 Log4(("pdmR3PciHlp_IsaSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel)); 461 PDMIsaSetIrq(pDevIns->Internal.s.pVMR3, iIrq, iLevel , /* ISA source */ true);461 PDMIsaSetIrq(pDevIns->Internal.s.pVMR3, iIrq, iLevel); 462 462 } 463 463 … … 598 598 PDMDEV_ASSERT_DEVINS(pDevIns); 599 599 LogFlow(("pdmR3HpetHlp_SetIrq: caller='%s'/%d: iIrq=%d iLevel=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, iIrq, iLevel)); 600 PDMIsaSetIrq(pDevIns->Internal.s.pVMR3, iIrq, iLevel , false /* Non-ISA source */);600 PDMIsaSetIrq(pDevIns->Internal.s.pVMR3, iIrq, iLevel); 601 601 return 0; 602 602 } -
trunk/src/VBox/VMM/VMMAll/PDMAll.cpp
r27123 r27254 100 100 * @param u8Level The new level. 101 101 */ 102 VMMDECL(int) PDMIsaSetIrq(PVM pVM, uint8_t u8Irq, uint8_t u8Level , bool fIsaSource)102 VMMDECL(int) PDMIsaSetIrq(PVM pVM, uint8_t u8Irq, uint8_t u8Level) 103 103 { 104 104 pdmLock(pVM); … … 124 124 * If changing, also update override rules in MADT and MPS. 125 125 */ 126 if (fIsaSource) 127 { 128 /* ISA IRQ0 routed to pin 2, all others ISA sources are identity mapped */ 129 if (u8Irq == 0) 130 u8Irq = 2; 131 } 126 /* ISA IRQ0 routed to pin 2, all others ISA sources are identity mapped */ 127 if (u8Irq == 0) 128 u8Irq = 2; 129 132 130 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), u8Irq, u8Level); 133 131 rc = VINF_SUCCESS; -
trunk/src/recompiler/VBoxREMWrapper.cpp
r27139 r27254 754 754 { REMPARMDESC_FLAGS_INT, sizeof(PVM), NULL }, 755 755 { REMPARMDESC_FLAGS_INT, sizeof(uint8_t), NULL }, 756 { REMPARMDESC_FLAGS_INT, sizeof(uint8_t), NULL }, 757 { REMPARMDESC_FLAGS_INT, sizeof(bool), NULL } 756 { REMPARMDESC_FLAGS_INT, sizeof(uint8_t), NULL } 758 757 }; 759 758 static const REMPARMDESC g_aArgsPDMR3CritSectInit[] = -
trunk/src/recompiler/VBoxRecompiler.c
r26939 r27254 4122 4122 void cpu_set_ferr(CPUX86State *env) 4123 4123 { 4124 int rc = PDMIsaSetIrq(env->pVM, 13, 1 , true);4124 int rc = PDMIsaSetIrq(env->pVM, 13, 1); 4125 4125 LogFlow(("cpu_set_ferr: rc=%d\n", rc)); NOREF(rc); 4126 4126 }
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