Changeset 27305 in vbox
- Timestamp:
- Mar 11, 2010 8:34:27 PM (15 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/Devices/PC/DevAPIC.cpp
r27221 r27305 44 44 #define MSR_IA32_APICBASE_BSP (1<<8) 45 45 #define MSR_IA32_APICBASE_ENABLE (1<<11) 46 #ifdef VBOX47 46 #define MSR_IA32_APICBASE_X2ENABLE (1<<10) 48 #endif49 47 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 50 48 … … 65 63 #define APIC_SAVED_STATE_VERSION_ANCIENT 1 66 64 65 /* version 0x14: Pentium 4, Xeon; LVT count depends on that */ 66 #define APIC_HW_VERSION 0x14 67 67 68 68 /** @def APIC_LOCK … … 882 882 break; 883 883 case 0x03: /* version */ 884 val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ 884 val = APIC_HW_VERSION | 885 ((APIC_LVT_NB - 1) << 16) /* Max LVT index */ | 886 (0 << 24) /* Support for EOI broadcast supression */; 885 887 break; 886 888 case 0x08: … … 939 941 Log(("apicReadMSR: read from write-only register %d ignored\n", index)); 940 942 break; 943 case 0x2f: 944 /** 945 * Correctable machine check exception vector, @todo: implement me! 946 */ 941 947 default: 942 948 AssertMsgFailed(("apicReadMSR: unknown index %x\n", index)); 949 /** 950 * @todo: according to spec when APIC writes to ESR it msut raise error interrupt, 951 * i.e. LVT[5] 952 */ 943 953 apic->esr |= ESR_ILLEGAL_ADDRESS; 944 954 val = 0; … … 1709 1719 break; 1710 1720 case 0x03: /* version */ 1711 val = 0x14 | ((APIC_LVT_NB - 1) << 16); /* version 0x14 */1721 val = APIC_HW_VERSION | ((APIC_LVT_NB - 1) << 16); 1712 1722 break; 1713 1723 case 0x08: … … 1783 1793 val = s->divide_conf; 1784 1794 break; 1795 case 0x2f: 1796 /** 1797 * Correctable machine check exception vector, @todo: implement me! 1798 */ 1785 1799 default: 1786 1800 AssertMsgFailed(("apic_mem_readl: unknown index %x\n", index));
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