Changeset 2789 in vbox for trunk/src/VBox/VMM/VMMR0
- Timestamp:
- May 23, 2007 8:30:17 AM (18 years ago)
- Location:
- trunk/src/VBox/VMM/VMMR0
- Files:
-
- 2 edited
-
HWACCMR0A.asm (modified) (7 diffs)
-
HWVMXR0.cpp (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/VMM/VMMR0/HWACCMR0A.asm
r2760 r2789 91 91 %endmacro 92 92 %endif 93 ;; @todo check ds,es saving/restoring on AMD64 93 94 94 %macro MYPUSHSEGS 2 95 95 mov %2, es … … 97 97 mov %2, ds 98 98 push %1 99 push fs 100 ; Special case for GS; OSes typically use swapgs to reset the hidden base register for GS on entry into the kernel. The same happens on exit 101 ; Note: do not step through this code with a debugger! 102 push rcx 103 mov ecx, MSR_K8_KERNEL_GS_BASE 104 rdmsr 105 pop rcx 106 push rdx 107 push rax 108 ; copy hidden base register into the MSR 109 swapgs 110 push rcx 111 mov ecx, MSR_K8_KERNEL_GS_BASE 112 rdmsr 113 pop rcx 114 push rdx 115 push rax 116 swapgs ; redundant unless in debugging mode 117 ; Now it's safe to step again 118 push gs 99 119 %endmacro 120 100 121 %macro MYPOPSEGS 2 122 ; Note: do not step through this code with a debugger! 123 pop gs 124 pop rax 125 pop rdx 126 push rcx 127 mov ecx, MSR_K8_KERNEL_GS_BASE 128 wrmsr 129 pop rcx 130 ; copy MSR into hidden base register 131 swapgs 132 pop rax 133 pop rdx 134 push rcx 135 mov ecx, MSR_K8_KERNEL_GS_BASE 136 wrmsr 137 pop rcx 138 ; Now it's safe to step again 139 140 pop fs 101 141 pop %1 102 142 mov ds, %2 … … 219 259 ALIGNCODE(16) 220 260 .vmlaunch_done: 221 jnc .vmxstart_good 222 223 ; Restore base and limit of the IDTR & GDTR 224 lidt [xSP] 225 add xSP, xS*2 226 lgdt [xSP] 227 add xSP, xS*2 228 229 pop xAX ; saved LDTR 230 lldt ax 231 232 add xSP, xS ; pCtx 233 234 ; Restore segment registers 235 MYPOPSEGS xAX, ax 236 237 ;/* Restore all general purpose host registers. */ 238 MYPOPAD 239 mov eax, VERR_VMX_INVALID_VMXON_PTR 240 jmp .vmstart_end 241 242 .vmxstart_good: 243 jnz .vmxstart_success 244 245 ; Restore base and limit of the IDTR & GDTR 246 lidt [xSP] 247 add xSP, xS*2 248 lgdt [xSP] 249 add xSP, xS*2 250 251 pop xAX ; saved LDTR 252 lldt ax 253 254 add xSP, xS ; pCtx 255 256 ; Restore segment registers 257 MYPOPSEGS xAX, ax 258 259 ; Restore all general purpose host registers. 260 MYPOPAD 261 mov eax, VERR_VMX_UNABLE_TO_START_VM 262 jmp .vmstart_end 263 264 .vmxstart_success: 261 jc .vmxstart_invalid_vmxon_ptr 262 jz .vmxstart_start_failed 265 263 266 264 ; Restore base and limit of the IDTR & GDTR … … 302 300 pop xBP 303 301 ret 302 303 304 .vmxstart_invalid_vmxon_ptr: 305 ; Restore base and limit of the IDTR & GDTR 306 lidt [xSP] 307 add xSP, xS*2 308 lgdt [xSP] 309 add xSP, xS*2 310 311 pop xAX ; saved LDTR 312 lldt ax 313 314 add xSP, xS ; pCtx 315 316 ; Restore segment registers 317 MYPOPSEGS xAX, ax 318 319 ; Restore all general purpose host registers. 320 MYPOPAD 321 mov eax, VERR_VMX_INVALID_VMXON_PTR 322 jmp .vmstart_end 323 324 .vmxstart_start_failed: 325 ; Restore base and limit of the IDTR & GDTR 326 lidt [xSP] 327 add xSP, xS*2 328 lgdt [xSP] 329 add xSP, xS*2 330 331 pop xAX ; saved LDTR 332 lldt ax 333 334 add xSP, xS ; pCtx 335 336 ; Restore segment registers 337 MYPOPSEGS xAX, ax 338 339 ; Restore all general purpose host registers. 340 MYPOPAD 341 mov eax, VERR_VMX_UNABLE_TO_START_VM 342 jmp .vmstart_end 343 304 344 ENDPROC VMXStartVM 305 345 … … 319 359 ;/* First we have to save some final CPU context registers. */ 320 360 %ifdef __AMD64__ 321 mov rax, qword vmresume_done361 mov rax, qword .vmresume_done 322 362 push rax 323 363 %else 324 push vmresume_done364 push .vmresume_done 325 365 %endif 326 366 mov eax, VMX_VMCS_HOST_RIP ;/* return address (too difficult to continue after VMLAUNCH?) */ … … 390 430 391 431 vmresume 392 jmp vmresume_done; ;/* here if vmresume detected a failure. */432 jmp .vmresume_done; ;/* here if vmresume detected a failure. */ 393 433 394 434 ALIGNCODE(16) 395 vmresume_done: 396 jnc vmresume_good 397 398 ; Restore base and limit of the IDTR & GDTR 399 lidt [xSP] 400 add xSP, xS*2 401 lgdt [xSP] 402 add xSP, xS*2 403 404 pop xAX ; saved LDTR 405 lldt ax 406 407 add xSP, xS ; pCtx 408 409 ; Restore segment registers 410 MYPOPSEGS xAX, ax 411 412 ; Restore all general purpose host registers. 413 MYPOPAD 414 mov eax, VERR_VMX_INVALID_VMXON_PTR 415 jmp vmresume_end 416 417 vmresume_good: 418 jnz vmresume_success 419 420 ; Restore base and limit of the IDTR & GDTR 421 lidt [xSP] 422 add xSP, xS*2 423 lgdt [xSP] 424 add xSP, xS*2 425 426 pop xAX ; saved LDTR 427 lldt ax 428 429 add xSP, xS ; pCtx 430 431 ; Restore segment registers 432 MYPOPSEGS xAX, ax 433 434 ; Restore all general purpose host registers. 435 MYPOPAD 436 mov eax, VERR_VMX_UNABLE_TO_RESUME_VM 437 jmp vmresume_end 438 439 vmresume_success: 435 .vmresume_done: 436 jc .vmxresume_invalid_vmxon_ptr 437 jz .vmxresume_start_failed 440 438 441 439 ; Restore base and limit of the IDTR & GDTR … … 474 472 mov eax, VINF_SUCCESS 475 473 476 vmresume_end:474 .vmresume_end: 477 475 pop xBP 478 476 ret 477 478 .vmxresume_invalid_vmxon_ptr: 479 ; Restore base and limit of the IDTR & GDTR 480 lidt [xSP] 481 add xSP, xS*2 482 lgdt [xSP] 483 add xSP, xS*2 484 485 pop xAX ; saved LDTR 486 lldt ax 487 488 add xSP, xS ; pCtx 489 490 ; Restore segment registers 491 MYPOPSEGS xAX, ax 492 493 ; Restore all general purpose host registers. 494 MYPOPAD 495 mov eax, VERR_VMX_INVALID_VMXON_PTR 496 jmp .vmresume_end 497 498 .vmxresume_start_failed: 499 ; Restore base and limit of the IDTR & GDTR 500 lidt [xSP] 501 add xSP, xS*2 502 lgdt [xSP] 503 add xSP, xS*2 504 505 pop xAX ; saved LDTR 506 lldt ax 507 508 add xSP, xS ; pCtx 509 510 ; Restore segment registers 511 MYPOPSEGS xAX, ax 512 513 ; Restore all general purpose host registers. 514 MYPOPAD 515 mov eax, VERR_VMX_UNABLE_TO_RESUME_VM 516 jmp .vmresume_end 517 479 518 ENDPROC VMXResumeVM 480 519 -
trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp
r2774 r2789 123 123 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT; 124 124 */ 125 #if HC_ARCH_BITS == 64 126 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT 127 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT; 128 #endif 125 129 /* Mask away the bits that the CPU doesn't support */ 126 130 /** @todo make sure they don't conflict with the above requirements. */
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